Abstract: A pulse-width modulation circuit includes an oscillator stage. The oscillator stage includes a first voltage comparator having a first input terminal, a second input terminal and an output terminal. A first capacitor is coupled to the first input terminal of the first voltage comparator. A charging path for the first capacitor is coupled between the first capacitor and the output terminal of the first voltage comparator, the charging path having a first resistance. A discharging path for the first capacitor is coupled between the first capacitor and the output terminal of the first voltage comparator, the discharging path having a second resistance that is different from the first resistance. A duty cycle of a clock signal generated by the oscillator stage is determined based on a first RC time constant for charging the first capacitor and a second RC time constant for discharging the first capacitor.

Abstract: The present disclosure relates to an active neutral-point clamped (ANPC) three-level converter, and a method and controller for controlling thereof. The ANPC three-level converter includes at least one bridge leg, and a controller. Each of the at least one bridge leg includes multiple input terminals, an output terminal, and multiple switches connected between the multiple input terminals and the output terminal. The multiple input terminals include a first input terminal, a second input terminal, and a third input terminal. The multiple switches include a first external switch, a first internal switch, a first clamp switch, a second external switch, a second internal switch, and a second clamp switch. The method for controlling the NPC three-level converter includes a method for controlling the ANPC three-level converter to stop operating, and a method for controlling the ANPC three-level converter to start to operate.

Abstract: A novel emergency traffic controller for emergency vehicles and a controlling method thereof are provided. The emergency traffic controller includes an emergency controlling unit, a target redirection unit and a source selection unit. The emergency controlling unit is used for receiving an emergency message and outputting a switching signal according to the emergency message. The target redirection unit is electrically coupled to an existing traffic light controller and the emergency controlling unit. The source selection unit is electrically coupled to the traffic light controller. The target redirection unit is used for receiving a lighting signal from the existing traffic light controller through the source selection unit and working with the emergency controlling unit to transmit the lighting signal to one of a plurality of traffic light signs according to the switching signal.

Abstract: According to some embodiments, an all digital ramp generator may use a string of series connected delays or digital to time-based circuits to perform voltage ramp generation. Thus in some embodiments conventional operational amplifier circuits and relaxation oscillators may be replaced for generating triangular ramp waveforms for DC to DC or direct time-based DC to DC converters. The use of delay lines may produce sufficient resolution for many applications. Thus time domain techniques may afford a more digital approach that scales with process technology and allows high speed operation in some embodiments. A design based on use of inverters and capacitors may scale well with process technology. The decoder and drive logic may be integrated into the voltage ramp generation in some embodiments.

Abstract: A ramp output control device includes a driver configured to receive at least two inputs from a microcontroller. The driver includes a time duration register configured to store a current clock count until a preset time duration is reached. The driver also includes a ramp output register configured to store a current output value at an output of the device. The driver also includes a calculation block configured to determine whether to increase the current output value at the output based on the at least two inputs.

Abstract: A method for generating a ramp comprises providing a voltage reference source, providing a summing amplifier, providing n switched capacitor elements coupled in parallel between the voltage reference source and the summing amplifier, and selectively activating a predetermined number of the switched capacitor elements to first store charge on each activated switched capacitor element and then to measure the sum of the charges on the activated capacitor switch elements in each of a fixed-integer number of time slots in a cyclical manner, the predetermined number being between 0 and n.

Abstract: Embodiments for at least one method and apparatus for controlling timing of switch control signals of a switching voltage regulator disclosed. One method includes generating a regulated output voltage based upon a switching voltage, generating the switching voltage through controlled closing and opening of a series switch element and a shunt switch element, and controlling, by a delay block, the closing and opening of the series switch element and a shunt switch element. The delay block control includes receiving, by the delay block, a timing signal, generating a one of a series switch control signal and a shunt switch control signal by controllably delaying the timing signal with a first delay, and generating one other of the series switch control signal and the shunt switch control signal by inverting, and controllably delaying the timing signal with a second delay.

Abstract: In an A/D conversion circuit and an imaging device, an upper counter acquires a first upper count value by performing counting using one output signal, which constitutes a first lower phase signal output from a delay circuit, as a count clock. After values of bits constituting the first upper count value are inverted, the upper counter acquires a second upper count value by performing counting using one output signal, which constitutes a second lower phase signal output from the delay circuit, as a count clock, and further performing counting based on an upper count clock output from a lower counter. A modification unit modifies a logic state of a count clock to a predetermined state when the count clock of the upper counter is switched.

Abstract: An integrated circuit includes a saw-tooth generator including a saw tooth node configured to have a saw-tooth voltage generated thereon; and a first switch having a first end connected to the saw tooth node. The integrated circuit further includes a second switch coupled between an output node and an electrical ground, wherein the first switch and the second switch are configured to operate synchronously. A first current source is connected to the saw tooth node. A second current source is connected to the output node.

Abstract: An integrated circuit includes a saw-tooth generator including a saw tooth node configured to have a saw-tooth voltage generated thereon; and a first switch having a first end connected to the saw tooth node. The integrated circuit further includes a second switch coupled between an output node and an electrical ground, wherein the first switch and the second switch are configured to operate synchronously. A first current source is connected to the saw tooth node. A second current source is connected to the output node.

Abstract: In accordance with an embodiment, a modulator includes a comparator and ramp generating circuitry. A first comparison signal is generated in response to comparing a first input signal with a compensation signal. A second comparison signal is generated in response to comparing a second input signal with the compensation signal. A first latch signal is generated in response to the first comparison signal and a second latch signal is generated in response to the second comparison signal.

Abstract: Provided are a data selection circuit, a data transmission circuit, a ramp wave generation circuit, and a solid-state imaging device. A delay section delays signals input to delay units of n (n is a natural number equal to or more than 3) stages that are connected to each other and have the same configuration and outputs delayed signals from the delay units. A delay control section controls a delay amount of the delay units. An output section performs a logical operation on signals output from i-th and j-th (i and j are natural numbers that are different from each other and equal to or more than 1 and equal to or less than n) delay units to generate a signal and outputs the signal to a k-th (k is a natural number equal to or more than 1 and equal to or less than m) first data selection pulse input terminal of a functional circuit having m (m is a natural number equal to or more than 2) first data selection pulse input terminals.

Abstract: A method of operating a neutral point clamped (NPC) three level converter is provided. The NPC converter includes at least two legs, each leg comprising first and second top switches connected in series at a first mid point. The converter further includes first and second bottom switches connected in series at a second mid point, and first and second middle switches connected in series at a third mid point therebetween. The first top and second bottom switches are connected in series at a DC link and the first and the second middle switches are connected between the first and the second mid points. Each of the top, bottom and middle switches has an antiparallel diode thereacross. The method includes alternately switching the first and second top switches to ON state when the first middle switch is in ON state and the second middle switch is in OFF state.

Abstract: A triangle waveform generator is set forth that comprises a capacitive element, a regulator, and a control circuit. The regulator is configured to charge the capacitive element in responsive to a first control signal and to discharge the capacitive element in response to a second control signal. The control circuit is responsive to a reference waveform to generate the first and second control signals. In one example, the control circuit generates the first and second control signals in response to the amplitude, frequency, phase, and symmetry of the reference waveform.

Abstract: A low power servo-controlled single clock ramp generator (100) includes a fast switched comparator (102), charge pump (110) and voltage-to-current converter (120) connected to provide a feedback control mechanism under control of a pulse comparison clock signal (pulse_comp) and a reset pulse clock signal (rst_pulse) that are generated from a single input clock signal (clkin) so that there are well defined time intervals between pulses in the pulse comparison clock signal and the reset pulse clock signal, thereby providing a ramp signal (Vramp_out) having a stable, frequency-independent amplitude that is not limited by the reference voltage.

Abstract: A semiconductor device includes a current control circuit for outputting and sinking a current in synchronization with a received clock signal; and a current/voltage conversion circuit having a first capacitor charged and discharged by the current control circuit outputting and sinking the current, respectively, and outputting a triangular wave based on the charge stored in the first capacitor.

Abstract: A triangular wave generating circuit includes: an integrating unit including a capacitor, the integrating unit having an output for providing a triangular wave signal; first and second constant current sources for charging and discharging the capacitor; a switch unit for coupling the first and second current sources to the integrating unit to charge and discharge the capacitor in response to an internal clock signal; a high/low level limiter including first and second comparing units for comparing the output of the integrating unit with upper and lower triangular wave peak limit reference voltages, respectively, and providing output signals indicating when the output of the integrating unit coincides with the peak limit reference voltages; a clock generator for providing the internal clock signal in response to the comparing unit output signals; and means for varying a peak-to-peak swing of the triangular wave signal over time to synchronize the internal clock signal with an externally supplied clock pulse.

Abstract: A pulse generator circuit that outputs pulses having a predetermined shape from an output terminal based on a start signal includes a timing generator circuit that generates (n) signals (n is an integer greater than or equal to 2), the phases of which sequentially change at predetermined time intervals from the point when the phase of the start signal changes, a pulse width signal generator circuit that generates a first pulse width signal and a second pulse width signal having a pulse width that corresponds to the duration of the pulses to be generated based on the start signal, a first filter circuit to which the first pulse width signal is inputted, the first filter circuit limiting the band of the first pulse width signal, a second filter circuit to which the second pulse width signal is inputted, the second filter circuit limiting the band of the second pulse width signal, first and second power supplies that supply predetermined potentials, a first variable impedance circuit whose impedance value is con

Abstract: A triangle wave generator with function of spreading frequency spectrum is provided. The triangle wave generator includes a switch control circuit, a current generator, an integrator, and a spread spectrum control circuit. The switch control circuit provides an internal clock and a switch control signal. The current generator is coupled to the switch control circuit and provides charge current according to the switch control signal. The integrator is coupled to the current generator and provides a triangle wave signal. The spread spectrum control circuit is coupled to the switch control circuit and the current generator for providing a current control signal according to the internal clock.

Abstract: A DC power source voltage is supplied to a center tap of a primary winding, and first and second semiconductor switches alternately turned on are disposed between each of both ends of the primary winding and a common potential point, and a current flowing through a load is fed back and PWM control of each of the semiconductor switches is performed. Also, snubber circuits are respectively connected between a ground and the center tap of the primary winding, and an abnormal high voltage at the time of switching is reduced. Also, a parallel running of plural inverters is simply performed by disposing PWM comparators corresponding to the first and second semiconductor switches.

Abstract: In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.

Abstract: Zero crossings for a non-symmetrical VIN may be determined by first amplifying and clipping VIN to create a non-symmetrical square wave whose zero crossings are those of VIN. A selected polarity edge of the non-symmetrical square wave may be taken as a 0° indicator and is used to create a fundamental sawtooth ramp of the same frequency and in phase with VIN. The fundamental sawtooth ramp starts at zero volts, linearly ramps to some peak and is AC coupled to a comparator whose other input is zero volts. That creates a square wave that is symmetrical as to its half-cycles, and whose every other edge is synchronous with the start of the fundamental sawtooth ramp, and whose intervening edges occur in the middle of the ramp. The intervening edge is detected and taken as a 180° indicator.

Abstract: A method, apparatus, and computer program product in a data processing system for testing differential clock or oscillator signals. A method is comprised of the following steps: A first single-ended receiver is connected to a positive leg of a differential pair, and a second single-ended receiver is connected to a negative leg of the differential pair. An output of the first single-ended receiver is inverted and delayed before being input into a first RS Flip-Flop. An output of the second single-ended receiver is delayed before being input into a second RS Flip-Flop. An output of a differential receiver is inverted and input into the first and second RS Flip Flops as reset signals. Then a Wire OK signal is output indicating the condition of the legs of the differential pair.

Abstract: A double frequency signal generator to which a synchronization signal having a duty cycle of 1% to 999% is inputted. The synchronization signal is used for triggering of a switching component at positive and negative edges to generate a triangular-wave signal. An average of voltages of the triangular-wave signal is acquired and compared with the triangular-wave signal at a comparator to generate a square-wave having a duty cycle of 50%. Then, the square-wave signal is used for triggering at positive and negative edges to generate a double frequency signal. As such, the high cost issue and the limitation of a square-wave input signal occurred in the prior art may be efficiently overcome.

Abstract: A distributed multi-axis motion control system comprises a multicast communications network having several node components. Each of the node components includes a clock and an actuator. The actuators are part of a motor system and a pattern profile table of the motor system is generated. The pattern profile table is translated into a separate single-direction-of-motion pattern table to separately direct the motion of each of the actuators of the node components. A grandmaster clock generates synchronization signals which are transmitted through the network at a sync interval and which synchronize the clocks. Time-bombs are generated at an interval which is a whole number multiple of the sync interval. The time-bombs cause concurrent execution of the first and subsequent steps from the single-direction-of-motion pattern tables to produce synchronized multi-axis motion of the motor system.

Abstract: A motion control system and method that includes a central controller configured to generate first and second demand control signals to be used to define actuation motion of respective first and second actuators. The central controller is in communication with first and second nodes by way of a data network, each node including at least a respective actuator configured to implement at an actuator time a motion or force-related effort based upon the respective demand control signal. Each node also includes a memory configured to store at least one respective propagation delay parameter related to a signal propagation delay between the central controller and the node. A timing mechanism establishes timing at each node based on the respective propagation delay parameter so that the actuator time at the nodes occurs simultaneously. Strictly cyclic and/or full-duplex high-speed communication can be supported. The network can be wired in a ring or as a tree and with twisted pair cabling or fiber.

Abstract: A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.

Abstract: A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiteratively test the time taken for a test data strobe to traverse a portion of the memory controller circuit, and to generate a calibration value based upon the time taken. The calibration procedure may be initiated in any one of several modes, including: according to a predetermined schedule; implemented in software; in response to changes in environmental factors such as temperature or voltages sampled at one or more locations; in response to a software-driven trigger; or in response to a user-initiated trigger, communicated to a system of the invention either by input via a user interface to the processor-based system or by a software command.

Abstract: A phase-locked loop with a delay element (DLL) is described which is essentially characterized in that the delay element (3) has a chain of a number n delay units (33n), the outputs (34n) of which are fed to a locking monitoring circuit (4) which determines whether the delay time Tdelay of the delay element (3) lies within a range a*Tperiod<Tdelay<b*Tperiod, where 0.5<a<1 and 1<b<2, and wherein the locking monitoring circuit (4) performs a correction of this delay time when this condition is not met.

Abstract: A variable delay circuit includes a ramp voltage generating unit having a storage capacitor, a charging transistor for charging the capacitor and a constant-current source for discharging the capacitor, and a comparator for comparing the output of the ramp voltage generating circuit against a voltage setting to output a delayed signal. The electric charge flowing out from the output node of the ramp voltage generating unit through the charging transistor during generating the ramp voltage is compensated by a compensating capacitor to output a linear ramp voltage.

Abstract: A first capacitor 7, a resistor 5, and a second capacitor 6 are connected in series between an output node A and a first power supply line 22. In addition, a first switch 8 is connected between the connected point of the first capacitor 7 and the resistor 5 and a second power supply line. A second switch 9 is connected in parallel with the second capacitor 6. The first and second switches 8 and 9 are opened or closed corresponding to the level of the input signal.

Abstract: A low-power differential switching amplifier (200, 210, 220, 230) is provided which utilizes a unique technique of generating interlaced ramps. The interlacing of the ramps causes the ramp discharge time to be effectively zero, which produces exceptionally accurate sawtooth waveforms with virtually no distortion. The timing of the differential switching amplifier circuitry can be synchronized with an external clock. A voltage null point is produced in the differential amplifier where zero voltage at the input of the amplifier produces essentially zero power dissipation within the load, even if the load is low-Q or substantially resistive. Also, by use of a phase balancing technique, residual errors resulting from component mismatches, which would otherwise have imposed power losses upon the load, are nulled out automatically during the operation of the amplifier.

Abstract: A signal generator generates a reference signal, centered about a reference voltage and having a predetermined period. The signal generator also generates output signals P and Z. The output signal P is a squarewave which changes levels at the peaks of the reference signal. The output signal Z is a squarewave which changes levels at the reference voltage crossings of the reference signal. A phase-shifted signal generator generates a phase-shifted signal using the output signals P and Z by switching in appropriate signal levels from the signal generator. The output signals P and Z are input to a switch control circuit which controls a network of switches, depending on a current region of the reference signal, to couple appropriate signals to an amplifier circuit. The switch control circuit determines the current region based on the state of the output signals P and Z. The amplifier circuit provides the phase-shifted signal in response to the signals coupled to it by the network of switches.

Abstract: A circuit for dividing a reference current is composed of a number n of transistors connected in cascade, in a Darlington configuration, between current generator and a fractionary current output node and by N+k (where k is an integer different from zero) directly biased diodes in series, connected between the generator and the fractionary current output node. The circuit does not employ current mirrors, so all transistors may have the minimum size, which also minimizes the effects of leakage currents. Additionally, compensation elements may be used for compensating the leakage currents from the base regions of the transistors. The circuit is useful as a capacitance multiplier, or as a slow ramp generator in a large number of design situations. Independence from intrinsic parameters of the transistors used and/or from temperature of operation may be provided by employing a specifically designed reference current generator. Several embodiments are described.