Abstract: A tera-sample-per-second waveform generator comprising: a first transmission line having a terminated end and an output end; an anti-reflection load coupled to the terminated end of the first transmission line; a plurality of current sources, wherein each current source is configured to inject current into the first transmission line; and a second transmission line configured to feed the first transmission line with a seed signal through the plurality of current sources such that the second transmission line has a different time delay between current sources than the first transmission line, wherein the seed signal triggers the current sources to inject current into the first transmission line in order to generate an output waveform.

Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for direct measurement of the capacitance of a Josephson junction. Roughly, the technique includes detecting the resonance frequency f of the junction under test, determining the DC voltage Vp across the junction under test at resonance frequency, and determining the capacitance of the junction under test in dependence upon the critical current Ic of the junction under test and the DC voltage Vp. This Abstract is not intended to limit the scope of the claims.

Abstract: A circuit can include a first Josephson junction (JJ), a second JJ, and a third JJ coupled in parallel using superconducting inductors. The first JJ, the second JJ, and the third JJ can be biased using one or more JJ-based current sources.

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A sensing region gate is formed by coupling the semiconductor layer with a second metal layer. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of a first surface of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. The sensing region and a portion of the device region of the superconductor layer are exposed. A sensing region contact is formed by coupling the first surface of the semiconductor layer with a first metal layer. A nanorod contact using the first metal within the portion of the device region outside the sensing region is formed. By depositing a second metal layer on a second surface of the semiconductor layer within the sensing region, a tunnel junction gate is formed.

Abstract: One example includes a superconducting clock conditioning system. The system includes a plurality of inductive stages. Each of the plurality of inductive stages includes an inductive signal path that includes at least one inductor and a Josephson junction. The superconducting clock conditioning system is configured to receive an input AC clock signal and to output a conditioned AC clock signal having an approximately square-wave characteristic and having a peak amplitude that is less than a peak amplitude of the input AC clock signal.

Abstract: Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.

Abstract: Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.

Abstract: One embodiment describes a Josephson current source system. The system includes a flux-shuttle loop that is inductively coupled with an AC input signal. The flux-shuttle loop includes a plurality of Josephson junctions spaced about the flux-shuttle loop and being configured, when activated, to sequentially trigger the plurality of Josephson junctions about the flux-shuttle loop in response to the AC input signal to generate a DC output current provided through an output inductor. The system also includes a flux injector that is configured to selectively activate and deactivate the flux-shuttle loop in response to an input signal to control an amplitude of the DC output current.

Abstract: Disclosed are apparatus and methodology subject matters for providing improved functionality of a meter in a 2-way communications arrangement, such as an Advanced Metering System (AMS) or Infrastructure (AMI). More particularly, the present technology relates to methodologies and apparatus for providing load sensing for utility meters which preferably are operable with remote disconnect features in an Advanced Metering Infrastructure (AMI) open operational framework. Meters per the present subject matter utilize a detection circuit, and separately utilize certain remote disconnect functionality. In particular, disconnect functionality is coupled with consideration of electric load information, such as load current as determined by the metering functionality.

Abstract: A reciprocal quantum logic (RQL) latch system is provided. The latch system comprises an output portion that retains a state of the latch system, and a bi-stable loop that comprises a set input, a reset input and an output coupled to the output portion. A positive single flux quantum (SFQ) pulse on the set input when the latch system is in a reset state results in providing a SFQ current in the output portion representative of the latch system being in a set state.

Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.

Abstract: A control system architecture for quantum computing includes an array of qubits, which is divided into a plurality of sub-arrays based on a first direction and a second direction, the second direction intersecting the first direction, a plurality of control lines each coupled to a corresponding sub-array of qubits in the first direction, a plurality of enable/unenable lines each coupled to a corresponding sub-array of qubits in the second direction, a controls signal source that generates a control signal, wherein the control lines are used to apply the control signal commonly to one or more sub-arrays of qubits in the first direction, an enable/unenable signal source that generates a enable signal, wherein the enable/unenable lines are used to apply the enable signal independently to the corresponding sub-array of qubits in the second direction to set a bias point of each qubit of the corresponding sub-array of qubits in the second direction between a first position, in which the qubit is unenabled and not r

Abstract: A power supply circuit includes a first voltage regulator to generate a first supply voltage for a first circuit of a phase-locked loop and a second voltage regulator to generate a second supply voltage for a second circuit of the phase-locked loop. The first and second supply voltages are independently generated by the first and second voltage regulators based on the same reference signal. The first circuit may be a charge pump and the second circuit may be a voltage-controlled oscillator. Different circuits may be supplied with the independently generated supply voltages in alternative embodiments.

Abstract: A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions defines a different island. An ancillary device is coupled to the first qubit. In a first example, the ancillary device is a readout mechanism respectively capacitively coupled to a first and second island in the plurality of islands of the first qubit by a first and second capacitance. Quantum nondemolition measurement of the first qubit's state may be performed. In a second example, the ancillary device is a second qubit. The second qubit's first and second islands are respectively capacitively coupled to the first and second islands of the first qubit by a capacitance. In this second example, the coupling is diagonal in the physical basis of the qubits.

Abstract: A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions defines a different island. An ancillary device is coupled to the first qubit. In a first example, the ancillary device is a readout mechanism respectively capacitively coupled to a first and second island in the plurality of islands of the first qubit by a first and second capacitance. Quantum nondemolition measurement of the first qubit's state may be performed. In a second example, the ancillary device is a second qubit. The second qubit's first and second islands are respectively capacitively coupled to the first and second islands of the first qubit by a capacitance. In this second example, the coupling is diagonal in the physical basis of the qubits.

Abstract: A non-radiation hardened N-channel transistor used in a power switching circuit functioning in a high-ionizing, radiation-dose environment. The circuit including at least one non-radiation hardened N-channel MOSFET switching transistors, the transistor having a gate, drain and a source. The circuit also includes a stored voltage source. The stored voltage source is in series with the gate of the at least one non-radiation hardened N channel MOSFET switching transistors. A high impedance bleeder resistor is connected to the stored voltage source for returning the positive terminal of the stored voltage source to the channel MOSFET source terminal.

Abstract: An oscillator to generate a low phase-noise reference signal at an oscillation frequency includes a frequency generator to generate the reference signal responsive to a control signal, and a delay element made of a high-temperature superconductor material. The delay element time-delays the reference signal and provides a low phase-noise time-delayed reference signal when cooled to a cryogenic temperature. The oscillator includes a phase detector to generate the control signal from a phase difference between the time-delayed reference signal and a phase-shifted reference signal. The delay element may comprise a coplanar waveguide having a length between 500 and 1000 meters arranged randomly on a substrate having a diameter of between five and thirteen centimeters. The delay element may provide a delay ranging from five to fifteen microseconds. The coplanar waveguide may be comprised of Yttrium-Barium-Copper Oxide disposed on either a Lanthanum-Aluminum Oxide or a Magnesium Oxide substrate.

Abstract: A programmable voltage standard element which consists of Josephson junction arrays having Josephson junction devices which are connected in series generates constant voltage by impression of bias current and microwave.

Abstract: A superconductor circuit (50) for providing active timing arbitration between SFQ pulses. The superconductor circuit (50) includes a first superconducting transmission line (52) having at least one inductor (54) for transmitting first input pulses, and a second superconducting transmission line (62) having at least one inductor (64) for transmitting second input pulses that are correlated to the first input pulses. The first and second superconducting transmission lines (52, 62) are coupled together in order to generate a flux attraction between the first and second input pulses for reducing relative timing uncertainty.

Abstract: The present invention discloses a method for amplifying voltage to which a test will be given in Josephon junction having external current, and more particularly, to a method for amplifying voltage in Josephon junction in which the voltage in a simple Josephon junction having an external current can be amplified by inserting an external colored noise into the external current.

Abstract: A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.

Abstract: A three-port Josephson memory cell has one input port (a data line) and two output ports (first and second sense lines). The memory cell receives a write enable pulse on a write line to store a bit of data from the data line as circulating supercurrent. The memory cell also receives a first read enable pulse on a first read line to enable assertion of the stored data onto the first sense line, and receives a second read enable pulse on a second read line to enable assertion of the stored data onto the second sense line.