Abstract: A detonator installation (10) in which a detonator fire capacitor (36) which is connected in series with an inductor (18) is charged from a low voltage source (16) by repeatedly opening and closing a switch (20) thereby to cause a collapsing magnetic field in the inductor (18) which results in a charging current flow to the capacitor (36).

Abstract: A semiconductor device includes a clock delay section configured to receive an external clock signal, reflect different delay amounts on the external clock signal, and generate a plurality of synchronization clock signals, a clock synchronization section configured to synchronize a clock enable signal with each of the plurality of synchronization clock signals in an order beginning with a synchronization clock signal, on which a largest delay amount is reflected, to a synchronization clock signal, on which a smallest delay amount is reflected, and to generate a synchronized clock enable signal, and an internal clock generation section configured to generate an internal clock signal corresponding to the external clock signal, and to be on/off controlled in its operation in response to the synchronized clock enable signal.

Abstract: In an exemplary embodiment of the present invention, a local clock buffer (LCB) fabricated in a semiconductor receives a global clock signal as input. The LCB implements a pulse width controller that is operationally coupled to the LCB and an output driver forming a ring oscillator. The output driver outputs a pulse width adjusted signal. The pulse width of the pulse width adjusted signal is adjustable by way of the pulse width controller and is related in frequency to the global clock signal. A second ring oscillator (also referred to as the nclk loop) can also be implemented to server as the global clock signal. The pulse width controller can be used to precisely adjust the pulse width of the pulse width adjusted signal. A pulse width multiplier can be implemented to allow direct observation and measurement of the pulse width of the pulse width adjusted signal.

Abstract: Methods are described that involve characterizing an oscillator's jitter or phase noise over a plurality of the oscillator's effective number of delay stages. The oscillator comprises a series of delay stages. Each one of the effective number of delay stages, if selected for the oscillator, describes a respective permissible range of inverter drive strengths that may be used within each delay stage of the oscillator to achieve a respective jitter or phase noise characteristic.

Abstract: A method and systems to evaluate the propagation delay within a semiconductor chip (305) that is embedded in an electronic system without requiring measurement apparatus and specific electrical contacts is disclosed. Since most of electronic systems use a microprocessor, the basic principle of the invention consists in using the microprocessor capabilities to measure the propagation delay of a chip embedded in such an electronic system. Thus, according to the invention, the microprocessor transmits an instruction to the semiconductor chip that performs propagation delay evaluation and then read the result in a dedicated memory register (415) of the chip. As a consequence, the chip does not require dedicated pins and measurement apparatus. In order to measure the propagation delay, the chip comprise a logic path (400) wherein propagation delay is created, then a rising edge detector (405) is used to analyze logic path signals, A counter (410) based on a system clock is used to measure propagation delay.

Abstract: In order to reproduce a clock having little jitter in the clock reproduction in data transmission, a reproduced clock is outputted by sampling an inputted base band signal by using sampling pulses by means of a sampler and shaped by means of a flip-flop. Errors of the sampling timing are detected by sampling the base band signal two times with a predetermined interval for each bit and by comparing magnitude of fluctuations of preceding sampled values with magnitude of fluctuations of succeeding sampled values. A clock reproduced circuit acts as a phase synchronizing loop circuit during bit synchronizing signal periods, while during data signal periods errors of the sampling timing are corrected by using an output of the error detection.

Abstract: A semiconductor memory device capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption even when the quick chip enable access is made possible. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths are set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions.

Abstract: A semiconductor memory device capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption even when the quick chip enable access is made possible. the semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths am set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable signal and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions.

Abstract: A current source gate drive circuit for simultaneous firing of a set of series or parallel thyristors is described. The circuit includes two current loops, each of which serves as a current transformer primary. Electrically insulating tubes enclose the current loops. Current transformer cores, around which are wound a certain number of secondary turns, surround the current loops, thus magnetically coupling the primary current of the current transformer to the secondary turns. Thyristor gate driver circuits are electrically coupled to the current transformer cores. Each of the thyristor gate driver circuits receives and rectifies ac current signals from the current loops and forms a current pulse train firing signal. Each thyristor gate driver circuit has a corresponding thyristor that is fired by the current pulse train firing signal. The thyristors operate at a high voltage, but are electrically isolated from the current loops by the insulating tubes.

Abstract: A drive circuit for use in UPS and like devices, designed to derive high-level switching signals from low-level logic signals. The drive circuit has an input circuit which drives the primary of an air-core transformer, the input drive circuit having an oscillator with a resonant circuit producing a carrier at a carrier frequency, the resonant circuit including the primary of the transformer and a coupling circuit for coupling the logic signals to the oscillator so as to modulate the carrier signal. The use of the resonant circuit enables generation of sufficient magnetization current for the low-cost transformer while reducing the current drive required of the input drive circuit, thereby enabling a reduced cost gate drive circuit.