Abstract: An adapter includes a control circuit, a control signal interface, a first input signal interface, a second input signal interface, and a first output signal interface. The control signal interface receives a tuning/detuning signal, and the control circuit switches, according to the tuning/detuning signal, the first input signal interface and the second input signal interface to be in conduction with the first output signal interface.

Abstract: A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage. This configuration has lower area penalty and better noise immunity.

Abstract: A receiving circuit with a simple circuit structure for performing wireless communication utilizing electromagnetic induction is provided. An LSI chip and a storage medium where wireless communication utilizing electromagnetic induction is performed and the circuit scale and circuit size can be reduced are provided. The following receiving circuit may be used: a parallel circuit where two diode elements whose directions are opposite are connected in parallel is used, one end of the parallel circuit is connected to the other end of a coil whose one end is connected to a ground potential line, and a capacitor is connected in series with the other end of the parallel circuit. A transistor whose leakage current is markedly reduced may be used as a diode in the receiving circuit. Such a receiving circuit may be used in an LSI chip or a storage medium.

Abstract: A phase error circuit including phase difference logic and delay and register logic. The phase difference logic provides a pulse difference signal including at least one difference pulse indicative of a timing difference between selected edges of a pair of clock signals. The delay and register logic receives the pulse difference signal and provides a phase error value representing phase error between the clock signals. The delay and register logic may include a delay line with multiple delay cells and taps coupled in series in which each tap provides an output state of a delay cell. The register logic registers a state of each tap to provide delay bits in response to each trailing edge of the difference pulses. Each delay bit may remain set until reset so that the longest pulse difference signal is registered to provide the peak phase error.

Abstract: A semiconductor circuit of the present invention comprises a capacitor for charging ON driven electric charges in response to an ON driving signal, a capacitor for charging OFF driven electric charges in response to an OFF driving signal, a signal generating circuit for generating a first trigger signal in response to the ON driving signal, a signal generating circuit for generating a second trigger signal in response to the OFF driving signal, a discharging circuit for discharging the ON driven electric charges in response to the second trigger signal, and a discharging circuit for discharging the OFF driven electric charges in response to the first trigger signal. With this configuration, it is possible to provide a semiconductor circuit and a semiconductor device both of which have a general-purpose malfunction prevention function by which a malfunction due to dV/dt can be prevented without being affected by any external factor.

Abstract: A method of fabricating a N+/P+ zener diode where the reverse breakdown occurs in a controlled, and uniform manner leading to improved speed of operation and increase in current handling capability.

Abstract: The present controllable synchronous rectifier employs a Lus semiconductor to set synchronous rectification action in quadrant 1 of output characteristics of the conventional power MOSFETs. By controlling the voltage level of the gate-source voltage, the drain current can be controlled in the synchronous rectifier. Further, in combination with a protect opposite circuit to transfer a sinusoidal wave power supply or pulse power supply to a direct current power output, the synchronous rectifier is an indispensable high efficiency rectifier in the industry.

Abstract: The present invention relates to a high voltage diode which has a fast turn-off, formed of a series connection of several diodes, the relative intrinsic dispersion of recovered charges between the diodes being smaller than 5%.

Abstract: A method and structure for wave-shaping of digital waveforms of integrated circuit processes that do not have area efficient dielectric capacitors is disclosed. The dielectric capacitors of the prior art are replaced with a first, linearizing diode and a second diode of a wave-shaping circuit, each diode having a junction capacitance that varies with voltage applied across the diode. The first, linearizing diode is supplied with a constant current from a constant current source. A current inversely proportional to the junction capacitance of the first, linearizing diode is produced at a node defined as the connection between the constant current source and the first linearizing diode. The current at the node is supplied to the second diode to produce an output voltage of the wave-shaping circuit that is linear with respect to time.

Abstract: The present invention is aimed at providing a method and a circuit for protecting the output stage of a power actuator against voltage transients of the surge type. In particular, it provides protection against voltage surge transients of the kind described by International Standard IEC 801-5, for a power transistor contained in the output stage of the actuator.The method of this invention provides for:the utilization of the power transistor (PW) intrinsic diode (DP) for dumping the transient energy to one of the supply generator terminals during a positive transient; andthe utilization of the power transistor (PW) restoration feature to the on state for dumping the energy thereinto during a negative transient, while simultaneously inhibiting the current limiting function.

Abstract: An electric multiple-valued register for electrically maintaining a multiple-valued digital signal of a ternary value of (0, 1/2, 1), quaternary value of (0, 1/3, 2/3, 1) or quinternary value of (0, 1/4, 2/4, 3/4, 1) instead of a binary digital signal such that 1 digit is of 0 or 1 is realized by inserting an element having a stair shaped voltage-current characteristic into a coupling circuit of a conventional flip-flop circuit. It may be used for a quantization circuit with the aid of a step characteristic, a multivalued memory, a multivalued register, a multivalued loop memory, a multivalued pattern matching circuit, a voice recognition divide, pattern recognition device, or a associative memory device.