Abstract: A pulse-width-modulated switching power converter is provided in which a comparator has a boosted speed to determine a trip point at which a ramp signal equals an error signal. In a linear comparator embodiment, a one-shot bias boosting circuit triggers an increased bias current to the linear comparator to boost the speed to determine the trip point. In a sense-amplifier-based comparator embodiment, a clock generator enables the sense-amplifier-based comparator prior to the trip point.

Abstract: A directional pulse injection system and method are described for injecting a pulse into a microelectronic system for electrostatic test. One example has a transformer coupled to a pulse source through a transmission line and to a conductive trace of a test board to apply the electrical pulse to the trace as a test pulse. The test board is connected to a microelectronic device under test. This example also has a cancellation pulse transmission line coupled to the pulse source and a cancellation pulse contact coupled to the pulse source through the cancellation pulse transmission line and to the trace on a side of the trace opposite the transformer to receive a cancellation signal from the pulse source and to couple the cancellation signal to the trace to cancel a portion of the test pulse.

Abstract: An example embodiment includes a fiber optic integrated circuit (IC). The fiber optic IC includes an integrated power supply. The integrated power supply includes a filter, an active switch, and a pulse width modulator (“PWM”). The filter is configured to convert a signal to an output signal of the integrated power supply. The active switch is configured to control introduction of the signal to the filter. The PWM is configured to generate a PWM output signal that triggers the active switch.

Abstract: An optical device is disclosed that may be employed in distance measuring devices. In at least one embodiment, the optical device includes a control unit that is adapted to cause at least one control signal generator unit to generate at least one control signal according to a predetermined temporal function on the basis of an elapsed time from a predetermined point in time. On the basis of the generated at least one control signal, at least one parameter of a receiver unit may be adjusted during the travel time of the optical pulse, wherein the at least one parameter affects the dynamic range of the receiver unit. In this way, the dynamic range of the receiver unit may be increased. A method is further disclosed for operating such an optical device, along with a distance measuring device including such an optical device and a surveying instrument including such a distance measuring device.

Abstract: A radio frequency noise reduction device and methods of operation are presented. The radio frequency noise reduction device identifies radio frequency noise on an isolated power plane of an electronic apparatus and generates an electrical signal that is injected into the isolated power plane and cancels the identified radio frequency noise. The generated electrical signal matches the frequency spectrum and amplitude of the identified radio frequency noise but the phase of the generated electrical signal is shifted by 180 degrees from the identified radio frequency noise.

Abstract: A logic circuit includes two two-terminal switching devices and receives first and second pulses as inputs. Each of the two devices has two different stable resistivity values for each applied voltage that is greater than a first threshold voltage (Vth1) and is smaller than a second threshold voltage (Vth2) that is larger than Vth1. Each switching device, when a voltage less than or equal to Vth1 is applied, becomes in a first state having the higher resistivity of the two resistivity values, whereas when a voltage more than or equal to Vth2 is applied, becomes in a second state having the lower resistivity of the two resistivity values. The two devices are connected in series in a direction with uniform polarity to each other. The first and second states are selectively generated in the first and second devices by a combination of inputs of the first and second pulses.

Abstract: The invention relates to an interconnection network and an integrated circuit and a method for manufacturing the same. Furthermore, the invention relates to a method for signal transfer between semiconductor structures. The invention is characterized in that a signal of a first semiconductor structure is supplied to a transmitter, which generates from the signal a plasmon wave, and couples the latter into a waveguide. The plasmons fed through the waveguide are received by a receiver, converted to an electric signal and forwarded to a second semiconductor structure.

Abstract: The invention includes a two terminal switching device having two stable resistivity values for each applied voltage, which when a voltage of not more than a first threshold voltage (Vth1) is applied, becomes in a first state having a higher resistivity, whereas when a larger second threshold voltage (Vth2) or more is applied, becomes in a second state having a lower resistivity; a resistance connected in series to the switching device; a terminal for applying a bias voltage (Vt) to both ends of a series circuit of the switching device and the resistance; a first pulse inputting terminal; and a second pulse inputting terminal. The invention provides a simple realization of a flip-flop circuit for a sequential logic circuit.

Abstract: The present invention relates to a SET/RESET latch circuit a Schmitt trigger circuit, and a MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. The SET/RESET latch circuit is configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied to very high speed digital circuits.

Abstract: An apparatus includes a quantizer circuit having a resonant tunneling device with an operational characteristic that includes a first region of unstable operation, and second and third regions of stable operation. An input terminal and an output terminal are each coupled to one end of the resonant tunneling device. A bias section is coupled to the resonant tunneling device, and responds to a clock signal by alternately operating in a first mode where the resonant tunneling device is forced to operate within the first region, and a second mode where the resonant tunneling device is permitted to operate in either of the second and third regions.

Abstract: An all-silicon nonlinear transmission line (NLTL) is integrated with a pulse-forming circuit in the form of a reverse-biased diode. Relatively short, e.g., 27 ps, optical signals can be generated from the all-silicon NLTL circuit by laser modulation of the electrical NTLT output in an electro-optical system.

Abstract: A high-speed comparator and an associated method are disclosed. The comparator utilizes input circuitry to receive the input signal and utilizes resonant tunneling diode (RTD) circuitry to provide a high or low level determination. The RTD circuitry may be made weak compared to the input circuitry to eliminate hysteresis, and the comparators may be cascaded together to provide a positive-gain. In addition, clocked switches may be added to the cascaded comparator circuitry to create a clocked quantizer for analog to digital conversion. If desired, the RTD circuitry may include two RTDs connected to the output signal, and the input circuitry may include a transistor connected as a source-follower and transistor connected as a current sink.

Abstract: In one aspect of the invention, a system for quantizing an input signal having a time-varying voltage includes a voltage-to-current converter operable to convert the input signal to a proportional current. The system also includes a first negative differential resistance element coupled in series with the voltage-to-current converter. The first negative differential resistance element is operable to switch from a first state to a second state based on the proportional current. In addition, the system includes a reset circuit coupled in parallel with the first negative differential resistance element. The reset circuit includes a second negative differential resistance element, and the reset circuit is operable to reset the first negative differential resistance element to the first state based on a reset signal.

Abstract: A system for quantizing an analog signal comprises an input terminal for receiving an analog input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A first negative-resistance device has a first terminal coupled to the clock terminal and a second terminal coupled to the input terminal. A second negative-resistance device has a first terminal coupled to the input terminal and a second terminal coupled to the inverted clock terminal. An output terminal coupled to the first negative-resistance device and the second negative-resistance device to provide a quantized output signal.

Abstract: The present invention includes: a series circuit which has a negative differential resistance element and another negative differential resistance element that has a control terminal capable of controlling a value of an element current; a transfer gate; a latch circuit which has negative differential resistance elements connected in series; and an inverter circuit which has an FET as a drive element and a negative differential resistance element as a load element. With this, such a flip-flop can be obtained that when a clock signal is applied to a power supply terminal of the series circuit and a control terminal of the transfer gate and an input signal is supplied to the control terminal of the negative differential resistance element, an output is placed at a terminal.

Abstract: A high-speed, compact, edge-triggered flip-flop circuit is provided which includes an input circuit section, a latch circuit section and an output circuit section. The input circuit section includes at least one transistor such as a field-effect transistor (FET) which determines the logic function of the flip-flop such as D, S-R, or T, and provides a first stage of latching. The input circuit section receives the logic control signals such as D, S-R, or T, and a clock signal. In one embodiment of the invention, the latch circuit section includes two series-connected negative differential resistance (NDR) diodes. In this embodiment, a common terminal of the two NDR diodes is connected to the data output of the input circuit section and to the data input of the output circuit section.

Abstract: A phase-locking system is provided that includes a bridge, a light source and an optical pulse injector. The bridge includes a plurality of negative differential resistance devices for storing an input signal. The light source is capable of producing an optical pulse. The optical pulse injector receives the optical pulse and transmits an optical signal to trigger the bridge in response to receiving the optical pulse.

Abstract: A latching comparator and associated method are disclosed that utilize resonant tunneling diodes, or other two-terminal devices possessing regions of negative differential operating resistance in their current-voltage characteristics, and Schottky diodes to provide high speed and reliable analog to digital conversions. In one embodiment, the latching comparator includes a differential amplifier, resonant tunneling diodes, and cross-coupled resistors. The latching comparator may include mode selection circuitry having a track mode signal and a latch mode signal as inputs. In addition, the latching comparator may include a plurality of Schottky diodes connected in series with the resonant tunneling diodes and the cross-coupled resistors.

Abstract: A system for storing digital data includes an input circuit, a clock circuit, and a bridge. The input circuit is coupled to receive an input signal. The clock circuit receives and transmits a clock signal. The bridge stores the digital data and includes a plurality of negative differential resistance devices. The bridge connects to the input circuit and the clock circuit.

Abstract: A high-speed differential comparator is disclosed. The comparator (100) includes a transconductance device (102 through 112) that receives first and second input voltages (V.sub.IN and -V.sub.IN) and generates first and second currents in response to the first and second input voltages. A first resonant tunneling diode (118) conducts the first current and generates a first output voltage (V.sub.OUT1) at a first output terminal (105) in response to the first current. A second resonant tunneling diode (126) conducts the second current and generates a second output voltage (V.sub.OUT2) at a second output terminal (109) in response to the second current. The comparator responds to input voltages at high speed and may be used for high frequency signal sampling and level determination.

Abstract: A high-speed differential comparator (300) is disclosed. A transconductance device is connected to the input terminal and the first and second output terminals (305 and 309, respectively) of the comparator. The transconductance device receives an input voltage (V.sub.IN) from the input terminal and generates a current between the first and second output terminals (305 and 309) in response to the input voltage. A load is connected between the first and second output terminals. The load, which includes a resonant tunneling diode (313), conducts the current and generates a voltage difference between the first and second output terminals (305 and 309) in response to the current. The comparator responds to input voltages at high speed and may be used for high frequency signal sampling and level determination.

Abstract: A resettable latched voltage comparator includes a resonant tunneling diode 10 connected in series with an amplifier 14 and a power source 16, and a reset circuit 12 connected between a circuit output terminal 18 and a second power source 20. Amplifier 14 converts the value of the voltage at an input terminal 22 into a proportional current at terminal 24; diode 10 detects the condition when the current at terminal 24 rises above a specific value equal to the resonant peak current of resonant tunneling diode 10; and reset circuit 12 controllably forces the voltage at terminal 18 of the circuit to a value approximately equal to the output voltage of power source 16 at terminal 29, thereby reducing the bias across diode 10 to approximately zero. A flash analog-to-digital converter configuration includes a plurality of comparators 200.sub.i having their reference voltage inputs biased from a series-connected chain of resistors 210.sub.i. The input terminals 22.sub.

Abstract: Resonant-tunneling transmission lines in the various architectures rely on discrete or continuous resonant-tunneling heterostructures to actively modify propagating logic signals. One embodiment utilizes amplification of logic signals to counteract ubiquitous losses and distortion associated with any transmission medium. Basically, the logic signal is incrementally reamplified and reshaped as it propagates along the transmission line. Another embodiment is directed to a clocking system that transmits a signal represented by a sinusoid. Then, in proximity to the logic gates or modules, the sinusoid is converted into a square wave that actually clocks the gates and other logic structures. The inventive active transmission line naturally performs this feature, thus enabling clock signal transmission over longer links coupled with sinusoid-to-square wave conversion in a limited area. Still other embodiments implement step or continuous variations in the physical width of the resonant-tunneling transmission line.

Abstract: The number of input latching comparators in a flash analog-to-digital converter is significantly reduced by merging the input latching function into exclusive OR gates used in the converter's decoding section. A latching exclusive OR gate used for this purpose employs resonant tunneling diodes as the latching devices, with hysteresis and impedance elements connected to ensure that the gate latches in a logic state that corresponds to the input analog signal. The latching logic gates operate in a current mode, enabling updated logic states to be latched in response to a periodic clock signal.