Abstract: The application relates to a data reading circuit of an embedded flash memory cell. The data reading circuit a switch circuit, a current clamp circuit, a current mirror circuit, a reference current source, a precharge circuit and a comparison circuit; the switch circuit includes a transmission gate, one end of the transmission gate is connected with a drain of the embedded flash memory cell, and the other end of the transmission gate is connected with a detection end of the current clamp circuit; a response end of the current clamp circuit is connected with a data node; the current mirror circuit is connected with the reference current source and the data node; an output end of the precharge circuit is connected with the data node; one input end of the comparison circuit is connected with the data node, and the other input end is connected with reference voltage.

Abstract: An electric assembly includes a semiconductor switching device with a maximum breakdown voltage rating across two load terminals in an off-state. A clamping diode is electrically connected to the two load terminals and parallel to the switching device. A semiconductor body of the clamping diode is made of silicon carbide. An avalanche voltage of the clamping diode is lower than the maximum breakdown voltage rating of the switching device.

Abstract: A display device for improving display quality includes a pulse compensator, a gate driver, a source driver and a display panel. The pulse compensator generates a clock signal of which amplitude decreases when peripheral temperature increases and increases when peripheral temperature decreases. The gate driver outputs a gate driving signal to the display panel based on the clock signal, wherein an amplitude of the gate driving signal decreases when the peripheral temperature increases and the amplitude of the gate driving signal increases when the peripheral temperature decreases. The source driver provides a gray-scale voltage based on gray-scale data, and the display panel displays an image corresponding to the gray-scale voltage in response to the gate driving signal. Therefore, the deterioration in the drive capability of the gate driver depending on the peripheral temperature may be prevented and display quality of the display device may be improved.

Abstract: A memory device includes: a memory array comprising a first plurality of bit cells arranged along a first column; and a negative bit line (NBL) circuit, coupled to the memory array. The NBL circuit includes: a first pair of conducting gates that are coupled to the first plurality of bit cells through a bit line (BL) and a bit bar line (BBL) of the first column, respectively; and a pair of trigger circuits, coupled to the first pair of conducting gates, respectively, and configured to monitor voltage levels present on the BL and BBL of the first column through the respective first pair of conducting gates, and based on the monitored voltage levels, to assert an NBL enable signal so as to cause a negative voltage to be applied on either the BL or the BBL of the first column.

Abstract: A method and apparatus for testing operability of a power converter with an existing power conversion assembly of a renewable energy system is disclosed. The method includes transferring a first pulse of energy from an existing power conversion assembly to a power filter of the power converter through first cells within a bridge circuit of the power converter. Another step includes determining a first current-voltage feedback associated with the first pulse. A next step includes transferring a second pulse of energy from the power filter to the existing power conversion assembly through second cells within the bridge circuit such that a portion of the first pulse moves back to the existing power conversion assembly. Another step includes determining a second current-voltage feedback associated with the second pulse. The first and second current-voltage feedbacks are compared with nominal tolerances of the power converter to ensure the power converter is operating properly.

Abstract: A differential power amplifier has at least an input stage and an output stage. A first output stage amplifier is configured to receive a first portion of a differential signal from the input stage at a first output stage input and provide a first amplified signal at a first output stage output. The second output stage amplifier is configured to receive a second portion of the differential signal from the input stage at a second output stage input and provide a second amplified signal at a second output stage output. Power limiter circuitry is connected to the first and/or output stage inputs and is configured to limit a power level of the differential signal prior to being received at the output stage, such that the differential power amplifier and associated filters are not damaged, while the nominal performance of the differential power amplifier at rated power is not significantly affected.

Abstract: A display device for improving display quality includes a pulse compensator, a gate driver, a source driver and a display panel. The pulse compensator generates a clock signal of which amplitude decreases when peripheral temperature increases and increases when peripheral temperature decreases. The gate driver outputs a gate driving signal to the display panel based on the clock signal, wherein an amplitude of the gate driving signal decreases when the peripheral temperature increases and the amplitude of the gate driving signal increases when the peripheral temperature decreases. The source driver provides a gray-scale voltage based on gray-scale data, and the display panel displays an image corresponding to the gray-scale voltage in response to the gate driving signal. Therefore, the deterioration in the drive capability of the gate driver depending on the peripheral temperature may be prevented and display quality of the display device may be improved.

Abstract: Systems and methods for managing memory in a dynamic translation computer system are provided. Embodiments may include receiving an instruction packet and processing the instruction packet. The instruction packet may include one or more instructions for obtaining a block of virtual memory for use in an emulated operating environment from a slab of virtual memory in a host environment, maintaining a mapping between the block of virtual memory and physical memory when the block is returned to the host environment, and for filling the block of virtual memory with zeros and a pattern based, at least in part, on a detected fill type.

Abstract: A circuit is described that includes a voltage follower device and a feed-forward device. In an implementation, the circuit includes a voltage follower device that includes an input and an output. The voltage follower device is configured to transfer a voltage signal at least substantially unchanged from the input to the output of the voltage follower device. The circuit also includes a feed-forward device that includes an input and an output. The input of the feed-forward device is connected to the input of the voltage follower device and the output of the feed-forward device is connected to the output of the voltage follower device. The feed-forward device is configured to output the voltage signal to the output of the voltage follower device.

Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter.

Abstract: An integrated circuit device comprising at least one voltage supply module arranged to receive at an input thereof at least one control signal and to provide at an output thereof a voltage signal in accordance with the received at least one control signal, and at least one control module comprising at least one feedback loop between the output of the at least one voltage supply module and the input of the at least one voltage supply module, and arranged to generate the at least one control signal based at least partly on the voltage level of the voltage signal output by the at least one voltage supply module. The at least one control module is further arranged to receive at an input thereof at least one instantaneous indication of a load current at the output of the at least one voltage supply module, and apply a compensation to the at least one control signal provided to the at least one voltage supply module based at least partly on the received at least one indication of the load current.

Abstract: According to one embodiment, an active clamp circuit includes a first switch element, a first diode, a first resistance, a first control circuit and a second control circuit. The first diode is connected to the first switch element and breaks down by an overvoltage applied to the first switch element. The first resistance is connected to the first diode and detects a current through the first diode. The first control circuit is configured to amplify a voltage across the first resistance and controls a current through the first switch element. The second control circuit is configured to control a conduction of the first switch element in accordance with the voltage across the first resistance.

Abstract: In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.

Abstract: The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node. A drive transistor supplies a drive current according to the control voltage of the output node of the error amplifier from an external power supply line to an internal power supply line. When the divided voltage exceeds a predetermined voltage, a clamp circuit changes the control voltage in the direction of decreasing the drive current.

Abstract: Methods and apparatus selecting settings for circuits according to various aspects of the present invention may operate in conjunction with a measurement element connected to the circuit. The circuit may include a voltage source adapted to supply a voltage to the measurement element. The voltage may be substantially independent of the characteristics of the measurement element. The circuit may further include a measurement sensor responsive to a current in the measurement element. The measurement sensor may generate a control signal according to the current in the measurement element.

Abstract: A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.

Abstract: A temperature stable comparator circuit, comprised of: a branch C having a first end, a second end, a first type-1 device and first type-2 device, wherein the first type-1 device and the first type-2 device are connected to a node O; a branch B having a first end, a second end, a second type-1 device, a second type-2 device, and a resistor; and a branch A having a first end, a second end, a third type-2 device and a current-control device; wherein the first ends of the branch A, branch B, and branch C are commonly connected, and the second ends of the branch B and branch C are commonly connected.

Abstract: A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.

Abstract: A current sensing circuit includes a power transistor, a sensing transistor configured to copy a current flowing through the power transistor at a predetermined ratio, a current sensing resistor configured to detect a voltage from the current copied by the sensing transistor, an input resistor configured to convert an input voltage to a current, a cross self-biasing cascade block configured to adjust currents at both ends of the input resistor, and a common gate transistor and a reference resistor configured to convert a current output of the input resistor to a final sense voltage.

Abstract: An inrush voltage clamping circuit for an electronic device for clamping an inrush voltage induced by hot plugging is disclosed. The clamp circuit includes a buffer unit and a clamp unit. The buffer unit is coupled to an input power end for receiving an inrush current of the inrush voltage. The clamp unit is coupled to the input power end and the buffer unit for controlling the buffer unit to receive the inrush current according to an input voltage of the input power end.

Abstract: In accordance with an aspect of the present invention, an external FET driving circuit includes a driving portion, a drain-to-gate clamp portion and a current feedback portion. The driving portion provides a driving signal to the external FET. The drain-to-gate clamp portion protects the external FET from flyback current, when the external FET is quickly turned OFF. The current feedback portion controls the driving signal provided by the driver.

Abstract: A power switch circuit includes an output transistor which is connected between a first power supply terminal and an output terminal, and drives a load, an abnormality detecting circuit which detects an abnormal state of the output transistor, a resistance element which generates a resistance component by a diffusion layer formed on a well region, and is provided between an input terminal and a control terminal of the output transistor, and a well potential switching circuit which switches a voltage to be supplied to the well region between a voltage of the output terminal and a voltage of a second power supply terminal based on a detection result by the abnormality detecting circuit.

Abstract: A device (100) for processing data, the device (100) comprising an integrator unit (103, 104) adapted for integrating an input signal (V1) and a correction unit (101, 102) adapted for correcting a clipping integrator unit (103, 104) by forcing a zero-crossing of an output signal (V1, V2) of the integrator unit (103, 104).

Abstract: A driver circuit includes an output, at least one transistor including a load section coupled between the output and a supply voltage, and a circuit coupled to a control terminal of the at least one transistor to apply a control voltage to the control terminal in at least one operation mode of the driver circuit. The control voltage is within a predetermined voltage range de-pending on a first predetermined voltage below a nominal voltage range of the output.

Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.

Abstract: An active voltage-clamping gate driving circuit comprises a difference comparison circuit for receiving a reference voltage, a gate driving signal, and a preset voltage level, and outputting a voltage comparison signal; and a gate driving circuit for receiving an input signal and the voltage comparison signal, and outputting a gate driving signal. The voltage comparison signal controls the gate driving circuit. When a level difference between the gate control signal and the reference voltage is equal to the preset voltage level, the gate driving circuit is turned off, so that the level of the gate control signal is clamped to the preset voltage level, and the gate driving circuit does not output quiescent direct current under the clamped state.

Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.

Abstract: This patent specification describes a backflow prevention circuit which includes a first switch configured to conduct or to shut down a current path from an input terminal to an output terminal, a logic circuit configured to binarize an input voltage at the input terminal based on an output voltage at the output terminal and to output a binary signal and a shutdown circuit configured to cause the first switch to shut down independently of a switching control signal in accordance with the binary signal output from the logic circuit. The switching control signal performs a switching control of the first switch. The logic circuit outputs a shutdown signal to shut down independently of the switching control signal when the input voltage becomes smaller than the output voltage.

Abstract: A direct current measuring apparatus includes a voltage generating part generating a voltage to be applied to a load being a measuring object; a current limiting part limiting a current flowing in the load to a set value; and an output terminal connected to the load. The current limiting part includes a D/A converter, a positive side limiting circuit, a D/A converter and a negative side limiting circuit. The positive side limiting circuit includes a negative feedback loop. The negative feedback loop includes a capacitor and a buffer circuit besides the feedback resistance. An output of the positive side limiting circuit positive side limiting circuit is connected to a non-inverting input terminal of the main amplifier through a diode.

Abstract: In one embodiment, the present invention includes an input buffer with a common gate amplifier having input terminals coupled to receive an incoming common mode voltage. The common gate amplifier may be configured to receive the incoming common mode voltage over a wide range of levels extending from a low end lower than a supply voltage of the input buffer to a high end exceeding the supply voltage.

Abstract: A current loop drive module includes a drive circuit and a compliance voltage controller. The drive circuit is configured to receive a compliance voltage and operable to generate a current loop signal based on the compliance voltage for receipt by an associated load coupled to the drive circuit. The compliance voltage controller is operable to adjust the compliance voltage based on the associated load. A method for generating a current loop signal includes generating a current loop signal based on a compliance voltage for receipt by an associated load and adjusting the compliance voltage based on the associated load.

Abstract: A method and a circuit for controlling at least one thyristor constitutive of a rectifying bridge with a filtered output, including closing the thyristor when the voltage thereacross becomes greater than zero, and making the gate current of the thyristor disappear when the current therein exceeds its latching current.

Abstract: An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order.

Abstract: In accordance with an aspect of an input/output device for providing fast translation between differential signals from a core of an integrated circuit and higher voltage signals that are external to the core, an I/O buffer includes low voltage devices for receiving core input signals, a cascode stage for setting a bias between the input devices and an output stage, and an output stage including a current mirror for providing a translated external output. Another aspect of the invention further includes a feedback path to cut off the current mirror to prevent static current and a keeper device to maintain an output level after cut off of the current mirror.

Abstract: A configurable feedback path is included in an amplitude control system having a signal source and an amplitude controller, and provides accurate tracking between a signal provided at a test port and a reference signal, whether or not the configurable feedback path is in an internally-leveled configuration or an externally-leveled configuration. The configurable feedback path includes a series of access ports, a detector that has an input coupled to the first access port, a filtered output coupled to the amplitude controller, and an unfiltered output providing the reference signal. The configurable feedback path also includes a signal separator that has an input terminal coupled to the signal source, a thru-terminal coupled to the third access port, and a coupled terminal that is coupled to the second access port. The fourth access port is coupled to the test port.

Abstract: A method and apparatus is provided for detecting the output power of an RF power amplifier for purposes of controlling the output power. A circuit for generating an output power control signal includes a power detector to detect the output power of an RF power amplifier. A variable gain amplifier is coupled to the power detector for amplifying the output of the power detector. The value of the generated control signal is a function of the gain of the variable gain amplifier.

Abstract: An invention is disclosed for protecting an input buffer. A current from a p-supply to an input buffer is lowered when an input voltage to the input buffer is tolerant HIGH. The p-supply being a VDD voltage supplied to a p-channel transistor in the input buffer. In addition, the p-supply is set to a particular voltage when the input voltage to the input buffer is LOW, the particular voltage being at a specific value such that input transistors within the input buffer do not experience overstress voltages. Optionally, p-supply can be prevented from supplying current to the input buffer when an input voltage to the input buffer is tolerant HIGH.

Abstract: An image sensing system includes an image sensor and a black clamping circuit which reside on the same substrate. Particular embodiments use common components for both imaging and black clamping, and digital control of an analog black clamp function.

Abstract: The present invention is a black clamp circuit for an electronic imager having black reference pixels. The circuit includes an average value circuit determining an average of a number of the black reference pixels, a correction circuit determining the black level correction from the average, and a modifier circuit modifying image pixels with the black level. The average value is used in a real time feedback loop that removes offset errors in the signal processing chain and establishes a corrected black level in output image data. The feedback can be either digital or analog. The correction circuit can include a comparator that allows a hysteresis in the feedback to avoid hunting as well as multiple levels of feedback based on several thresholds. The corrected black level can also be controlled by a digital transfer function. The black clamp circuit can be used for a series of images, an image frame and an image line.

Abstract: The clamp circuit clamps an input voltage at prescribed higher and lower clamp voltages which are stabilized under a temperature fluctuation. Transistors Q12 and Q14 are switched on in their linear region. In a lower voltage clamp circuit 18, an Vin detecting circuit 20 outputs Va1 by level-shifting Vin by Q13 and voltage-divides by series resistance circuit 23 the level-shifted Vin, while a reference voltage generating circuit 21 outputs Vr1 by level-shifting 0 V by Q15 and voltage-divides by series resistance circuit 25 the level-shifted voltage. Q11 is switched on, when a comparator 22 determines that Va1 descends and goes across Vr1. Here, Q12 is of the same characteristics as Q14, while Q13is of the same characteristics as Q15. Further, the resistance of the circuits 23 is the same as that of the circuit 25. The higher voltage clamp circuit 19 is similar to the circuit 18.

Abstract: An amplifying circuit includes an amplifying stage for receiving input signals to generate output signals. A swing detect unit detects signal levels of the output signals. A clamp unit variably limits signal levels of the input signals based on the signal levels of the output signals detected by the swing detect unit to improve the speed of the amplifying circuit.

Abstract: A variable resistance circuit and application circuits using the same capable of offsetting the variance in the manufacture of integrated circuit and the influence of ambient temperatures, including: a control circuit having a plurality of constant-current output terminals, with a constant current ratio of the output terminals varied by signals applied to a control terminal; an operational amplifier; a resistor; and a plurality of MOS transistors having the gates thereof connected in common; and one output terminal of the control circuit being connected to one end of the resistor and to an inverted input terminal of the operational amplifier and the other output terminal being connected to the drain of one MOS transistor connected at the gate thereof to an output terminal of the operational amplifier and being connected to a non-inverted input terminal of the operational amplifier; and the other end of said resistor and the source of said one MOS transistor being connected to a reference voltage terminal.

Abstract: A drive circuit including circuitry that can be easily adjusted, the output drive current can be kept balanced, and high-precision drive current can be supplied to the load circuit. Clamp circuit 10 is furnished to hold the drain voltage of current output transistor QN12, which supplies drive current to a load resistor. When transistor QN12 is in a conducting state, drain voltage VA of transistor QN12 is held at approximately the same level as source voltage VD of transistor QN14 by clamp circuit 10. So rise and fall in the drain output current of transistor QN12 can be kept balanced, and rise and fall delay time can be made approximately equal for input signal Sin.

Abstract: An amplifying circuit includes an amplifying stage for receiving input signals to generate output signals. A swing detect unit detects signal levels of the output signals. A clamp unit variably limits signal levels of the input signals based on the signal levels of the output signals detected by the swing detect unit to improve the speed of the amplifying circuit.

Abstract: The present invention relates to circuits having differential structure which uses complementary devices for processing single-ended signal. The single-ended differential circuit in accordance with the present invention, comprises first and second complementary devices having first, second, and third terminals, respectively, wherein current flowing from the second terminal to the third terminal has its quantity and direction being varying in dependant on the voltage driven to the first terminal, wherein the currents flowing through the first and second complementary devices vary in opposite relationship.

Abstract: A circuit includes a differential amplifier providing a differential signal to a voltage follower. The output of the voltage follower is fed back through resistors to an additional differential amplifier to the respective inputs to the voltage follower. The feedback is negative at low frequencies and less negative or positive about the clock frequency.

Abstract: A current mode step attenuation control circuit with digital technology. The circuit includes several stages of serially connected current attenuation circuits, each having a digital control input port, common mode feedback signal input port and bias input port, which are connected to corresponding a digital control signal, a common mode feedback current and a bias voltage, respectively. An analog input signal inputted to the circuit is controlled by the digital control signal to implement step attenuation. By using the conducting resistance of a MOS transistor to form equivalent resistance or match of current source for attenuation, the circuit eliminates dependence on resistance match of conventional technology. Because step attenuation is directly controlled by a digital control signal, the transmission speed is fast, phase delay is small, control accuracy is high and the device is suitable for digital integrated circuit manufacturing technology.

Abstract: In digital signal demodulation and detection circuits, especially digital radio signal reception and processing circuits, the signals are received in analog form and have to be converted into logic levels. This is done in practice by comparing the level of the signal with its mean level. The mean level is established by an RC lowpass filter which introduces an inconvenient delay into the preparation of the mean level. The mean level of the signal, established by an RC filter is compared and applied to an input B of a comparator COMP, at the level of the analog signal delayed by a phase-shifter and applied to another input A of the comparator. In order that the delay introduced by the phase-shifter into the analog signal may be substantially the same as the delay given to the mean value by the RC circuit, the phase-shifter is made with the same RC circuit and an amplifier mounted so as to set up a phase shift transfer function of the (1−RCp)/(1+RCp) type where p is the Laplace variable.

Abstract: A high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called “dual-gate” or “thick-oxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.

Abstract: Gate protection clamping circuits and techniques with controlled output discharge current are provided. Circuits and methods according to the invention are implemented to relatively rapidly disengage single or multiple loads from a power supply without creating thermal overload. This is accomplished by first rapidly shutting OFF the power device coupling the power source to the load, and then further discharging the output capacitance with a substantially smaller, preferably regulated, current. Additional external devices may be added if faster discharge of the output capacitance is desired.