By Using Diverse-type Nonlinear Devices Patents (Class 327/324)
  • Patent number: 10644687
    Abstract: A control device for a power semiconductor switch, includes an actuating device, a first current path, a second current path, which connects the second output of the actuating device to a circuit node of the control device in an electrically conductive manner, wherein the second current path incorporates an electrical switching off resistor which is electrically connected in-circuit between a second output of the actuating device and the circuit node of the control device, a third current path, which connects the circuit node of the control device to a control device terminal of the control device in an electrically conductive manner, and an switching off acceleration circuit, which is electrically connected in parallel with the switching off resistor, comprising a diode, an electrical resistor, and a capacitor which is electrically connected in parallel with said resistor, wherein the cathode of the diode is connected to a second electrical terminal of the capacitor in an electrically conductive manner, and
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: May 5, 2020
    Assignee: SEMIKRON ELEKTRONIK GmbH & CO. KG
    Inventor: J├╝rgen Schmidt
  • Patent number: 10175272
    Abstract: A remote differential voltage sensing circuit having a voltage input (Vin) and a voltage output (Vout), comprises a dual differential input stage including a common-source or common-collector differential input stage in parallel with a common-gate or common-base differential input stage. The common-source or collector differential input stage has differential inputs, one coupled to the voltage input (Vin) and the other coupled to the voltage output (Vout). The common-gate or common-base differential input stage has differential inputs, one coupled to a local ground (Agnd) and the other coupled to a remote ground (Rgnd). An output stage is driven by an output of the dual differential input stage and produces an output voltage at the voltage output (Vout). A compensation network is coupled between the voltage output (Vout) and the output of the dual differential input stage.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: January 8, 2019
    Assignee: INTERSIL AMERICAS LLC
    Inventors: Wei Chen, Xin Zhang, Gwilym Luff, Peter J. Mole
  • Patent number: 10079599
    Abstract: A device is suggested comprising at least two transistors, each of the transistors comprising a current path and a control terminal, wherein the current paths of the at least two transistors are arranged in parallel, wherein the control terminals of the at least two transistors are connected to a control node via at least one voltage drop component. Also, a method to efficiently control at least two transistors is provided.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: September 18, 2018
    Assignee: Infineon Technologies AG
    Inventors: Veli Kartal, Stephan Donath
  • Patent number: 9000825
    Abstract: Various active diode circuits are described. In one example, there is provided an active diode circuit having an active diode and a control circuit. The active diode includes an anode terminal, a cathode terminal and a control terminal. The control circuit is configured to generate a control current of the active diode on the control terminal proportional to the diode current of the active diode. The control circuit is also configured to control the diode voltage of the active diode below a predetermined threshold.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Stichting IMEC Nederland
    Inventor: Christinus Antonetta Paulus van Liempd
  • Patent number: 8970283
    Abstract: There is disclosed a switching arrangement comprising a switch with a plurality of individually controllable elementary switches connected in parallel between a first supply rail and a second supply rail. Each of the elementary switches can be in either one of a closed state and an open state independently of the others. A controller is adapted to dynamically control the closing or opening of the elementary switches, depending on the intensity of a current flowing through the switch. The number of elementary switches in the closed state is variable. The higher is the intensity of the current, the higher the number of elementary switches in the closed state. Thus, the impedance of the switch decreases when the current increases, and vice versa, and the voltage drop across the switch may be kept substantially constant.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Anton Rozen, Yaakov Seidenwar
  • Patent number: 8854103
    Abstract: A clamping circuit includes a clamping element with a control terminal and a load path that is coupled between a first circuit node and a second circuit node. A control circuit is coupled between the first circuit node and the second circuit node and is also coupled to the control terminal of the clamping element. The control circuit includes at least one snap-back unit with two load terminals and is only coupled between the first circuit node and the control terminal of the clamping element. The snap-back unit has an electrical resistance between the two load terminals and is configured to reduce the electrical resistance when a voltage between the two load terminals reaches a given threshold value.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: October 7, 2014
    Assignee: Infineon Technologies AG
    Inventor: Joost Willemen
  • Publication number: 20140002051
    Abstract: The present invention relates to a cascode circuit using MOS transistors. In one embodiment, an adaptive cascode circuit can include: (i) a main MOS transistor; (ii) n adaptive MOS transistors coupled in series to the drain of the main MOS transistor, where n can be an integer greater than one; (iii) a shutdown clamping circuit connected to the gates of the n adaptive MOS transistors, where the shutdown clamping circuit may have (n+1) shutdown clamping voltages no larger than rated gate-drain voltages of the main MOS transistor and n adaptive MOS transistors; and (iv) n conduction clamping circuits coupled correspondingly to the gates of the adaptive MOS transistors, where the n conduction clamping circuits may have n conduction clamping voltages no larger than the conduction threshold voltages of the adaptive MOS transistors.
    Type: Application
    Filed: September 5, 2013
    Publication date: January 2, 2014
    Applicant: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Michael Grimm, Jun Chen
  • Patent number: 8610485
    Abstract: A gate drive circuit includes a turn-on circuit having an upper limiter for receiving a gate drive signal. The upper limiter has an output terminal. The turn-on circuit also has a transistor having a base connected to the output terminal of the upper limiter. In addition, the terminal has a terminal connected to a gate of a power switching device. The upper limiter limits a voltage input to the base of the transistor to not exceed a first predetermined value.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: December 17, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazuaki Hiyama
  • Patent number: 8610484
    Abstract: An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: December 17, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Sudarshan Udayashankar, Jerry L. Doorenbos
  • Patent number: 8531226
    Abstract: In one general aspect, an apparatus can include a polarity insensitive input coupled to a gate of a metal-oxide-semiconductor field effect transistor (MOSFET) device. The MOSFET device can have a gate dielectric rating greater than twenty-five volts. The apparatus can also include a fixed polarity output coupled to a source of the MOSFET device.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: September 10, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph D. Montalbo, Steven Sapp
  • Patent number: 8283963
    Abstract: An output stage, especially a switching output stage for switching inductive loads, having a plurality of individual output stages that are connected in parallel, which include degenerative transistors, in the degenerative path of which one respective Zener diode is present. The electric power during a switching-off process can be distributed in a particularly uniform manner to the individual output stages or transistors by disposing the Zener diodes near the associated transistors so that they are thermally coupled to the respectively associated transistor and their Zener voltage increases with increasing temperature.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: October 9, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Uwe Lueders, Juergen Eckhardt, Bernd Mueller
  • Publication number: 20120242390
    Abstract: In one general aspect, an apparatus can include a polarity insensitive input coupled to a gate of a metal-oxide-semiconductor field effect transistor (MOSFET) device. The MOSFET device can have a gate dielectric rating greater than twenty-five volts. The apparatus can also include a fixed polarity output coupled to a source of the MOSFET device.
    Type: Application
    Filed: October 11, 2011
    Publication date: September 27, 2012
    Inventors: Joseph D. Montalbo, Steven Sapp
  • Patent number: 8248131
    Abstract: There are provided a timing generating circuit which can generate the rising edge or the falling edge of pulses with a resolution higher than the frequency of a repeat signal generating circuit, and a phase shift circuit which can be applied to the timing generating circuit. The phase shift circuit receiving a repeat signal generates a signal of which a phase is shifted by a predetermined quantity on the basis of the repeat signal, the phase shift controller controls what phase of signal the phase shift circuit output among first to M-th signals, and the counter circuit counts the number of output signals of the phase shift circuit and generates a count end signal when the count value reaches a set value, and thereby the counter circuit outputs a synthesized timing signal of the timing of the repeat signal and the timing shifted by the phase shift circuit.
    Type: Grant
    Filed: June 1, 2008
    Date of Patent: August 21, 2012
    Assignee: Nagasaki University, National University Corporation
    Inventor: Fujio Kurokawa
  • Publication number: 20110279163
    Abstract: A signal level crossing detector circuit includes a DC isolator and a detector circuit. The DC isolator has at least a first input, which is operable to receive a high voltage AC signal, and at least a first capacitor, a first plate of the first capacitor being electrically connected to the first input. The detector circuit is operable at a low voltage and has at least a first detector input, the first detector input being electrically connected to a second plate of the first capacitor, the low voltage detector circuit being operable to provide a change in output signal in dependence on a high voltage AC signal on the first input crossing a predetermined signal level. The signal level crossing detector may be single ended or differential.
    Type: Application
    Filed: May 12, 2011
    Publication date: November 17, 2011
    Applicant: BROADCOM CORPORATION
    Inventors: Iain Barnett, William Michael James Holland, Jonathan Ephraim David Hurwitz
  • Patent number: 8055223
    Abstract: A radio receiver includes a down-converter 110 for receiving a radio multiplexed signal containing a first signal and a second signal, multiplying the first signal and the second signal by a mixer 104 to thereby down-convert the radio multiplexed signal and generate an intermediate frequency signal 5e. The mixer 104 has a control section for controlling an operating bias of the mixer 104 in response to a signal strength of at least either one of the first signal or the second signal. Thus, the dynamic range of the mixer can be widened so that stable image characteristics can be obtained over a wide range of transmission distance.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: November 8, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinichi Handa, Eiji Suematsu, Atsushi Yamada, Keisuke Sato
  • Patent number: 7830196
    Abstract: When an insulated gate bipolar transistor turned on starts to transition to turn off, the insulated gate bipolar transistor has between the emitter and the collector a surge voltage caused in proportion to the magnitude of a current gradient provided when a current flowing through a coil in switching is interrupted and an electrode interconnect inductance internal to an inverter circuit. A MOS transistor is temporarily turned on within a period of time for which the insulated gate bipolar transistor turned on transitions to turn off. This can bypass a portion of the current to the MOS transistor. This can provide an alleviated apparent current gradient of the current and thus alleviate or prevent a surge voltage caused at the insulated gate bipolar transistor.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: November 9, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takeshi Omaru
  • Patent number: 7403060
    Abstract: A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body terminal of the transistor, and a clamping element coupled in parallel to the resistive element and configured to limit a voltage between the source terminal and the body terminal of the transistor. A method of manufacturing the forward biasing protection circuit is also provided.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: July 22, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Dong Pan
  • Patent number: 7323922
    Abstract: A signal processing system has a first, digitally controlled, gain element, a second, analogue controlled, gain element and a gain control unit configured to receive a gain request signal and to generate a first gain control signal to be input to the first gain element and a second gain control signal to be input to the second gain element such that the gain provided by the signal processing system corresponds to the gain request signal.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: January 29, 2008
    Assignee: Analog Devices, Inc.
    Inventor: Christopher Geraint Jones
  • Patent number: 7119586
    Abstract: A circuit arrangement for control of a regulated path and a semiconductor circuit (1) comprises a control connection, with an input, to which a switching signal (3) for control of the semiconductor circuit (1) is applied, an output, to which the control connector of the semiconductor circuit (1) is coupled, a control circuit (2) arranged between input and output. The switching signal (3) may be retained at the current value by means of a hold signal and an analytical circuit (2), which measures a voltage corresponding to the voltage across the controlled path and generates the holding signal for the control circuit (2) for a given duration when the voltage across the controlled path of the semiconductor circuit (1) has a rise which indicates a switching off of the semiconductor circuit (1).
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: October 10, 2006
    Assignee: Eupec Europaische fur Leistungshalbleiter mhH
    Inventor: Michael Hornkamp
  • Patent number: 6853232
    Abstract: A power switching device has a power switching transistor connected in series in a load circuit with an inductive load portion and a commutation circuit. The commutation circuit is connected in parallel with the gate-drain or base-collector path of the power transistor and has a first Zener diode, which determines the commutation clamping voltage for switching on the power switching transistor during commutation, and an oppositely biased normal diode that is connected in series with the first Zener diode. The commutation circuit further has control elements in order to reduce, during a short time, the commutation clamping voltage at the beginning of each commutation cycle or after an adjustable delay from the beginning of each commutation cycle.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: February 8, 2005
    Assignee: Infineon Technologies AG
    Inventors: Rainald Sander, Frank Kahlmann, Veli Kartal, Detlef Kalz, Helmut Hertrich
  • Patent number: 6756834
    Abstract: ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O's through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only one ESD clamp rather than two ESD-protection devices must turn on. The ESD clamps and ESD-protection devices can be gate-coupled n-channel transistors with coupling capacitors between the pad and the transistor gate. Devices can also be substrate-triggered transistors or active ESD clamps that include an inverter between a coupling capacitor to the CDL and the n-channel transistor gate.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: June 29, 2004
    Assignee: Pericom Semiconductor Corp.
    Inventors: Paul C. F. Tong, Siu-Weng Simon Wong, Ping Ping Xu, Zhi Qing Liu, Wensong Chen
  • Patent number: 6747501
    Abstract: An integrated circuit that includes a signal pad, a clamping circuit including a first NMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first NMOS transistor is coupled to the signal pad and the source of the first NMOS transistor is coupled to ground, and a control circuit coupled to the gate and substrate of the first NMOS transistor and the signal pad, the control circuit providing a first bias voltage signal to the gate and a second bias voltage signal to the substrate. The voltage level of the first bias voltage signal may be equal to, greater than, or less than the second bias voltage signal. By independently optimizing the trigger levels of the substrate and gate of the transistor in the clamping circuit, a robust ESD protection circuit can be obtained to suit the requirements of different process technologies.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: June 8, 2004
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Dou Ker, Kei-Kang Hung, Hsin-Chin Jiang
  • Patent number: 6744297
    Abstract: An inverter circuit includes an input end receiving an input signal having a low level and a high level, wherein the low level is greater than zero, a P-channel metal-oxide-semiconductor (PMOS) transistor having a gate electrode coupled to the input end and a source electrode coupled to a voltage source, a first N-channel metal-oxide-semiconductor (NMOS) transistor having a drain electrode coupled to a drain electrode of the PMOS transistor to serve as an output end, and a source electrode thereof coupled to ground, and a voltage drop device coupled to the gate electrode of the first NMOS transistor and the input end to provide a voltage drop from the input end to the gate electrode of the first NMOS transistor, thereby eliminating a current leakage of the first NMOS transistor at the low level of the input signal.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: June 1, 2004
    Assignee: Via Technologies, Inc.
    Inventor: Chao-Sheng Huang
  • Patent number: 6700428
    Abstract: A circuit configuration for driving a load is described. The circuit configuration has a first and a second connecting terminal for connecting the load, a first drive input for applying a first drive signal, and a first semiconductor switching element having a first load terminal connected to the first connecting terminal, a second load terminal connected to the second connecting terminal and a drive terminal coupled to the drive input. A voltage limiting circuit is provided and is connected between the first load terminal and the drive terminal of the first semiconductor switching element.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: March 2, 2004
    Assignee: Infineon Technologies AG
    Inventor: Rainald Sander
  • Publication number: 20030222697
    Abstract: An inverter circuit includes an input end receiving an input signal having a low level and a high level, wherein the low level is greater than zero, a P-channel metal-oxide-semiconductor (PMOS) transistor having a gate electrode coupled to the input end and a source electrode coupled to a voltage source, a first N-channel metal-oxide-semiconductor (NMOS) transistor having a drain electrode coupled to a drain electrode of the PMOS transistor to serve as an output end, and a source electrode thereof coupled to ground, and a voltage drop device coupled to the gate electrode of the first NMOS transistor and the input end to provide a voltage drop from the input end to the gate electrode of the first NMOS transistor, thereby eliminating a current leakage of the first NMOS transistor at the low level of the input signal.
    Type: Application
    Filed: April 14, 2003
    Publication date: December 4, 2003
    Inventor: Chao-Sheng Huang
  • Patent number: 6593794
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: July 15, 2003
    Assignee: Atheros Communications
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
  • Patent number: 6549061
    Abstract: An ESD clamping circuit arranged in a darlington configuration and constructed from SiGe or similar type material. The ESD clamping circuit includes additional level shifting circuitry in series with either the trigger or clamping device or both, thus allowing non-native voltages that exceed the BVCEO of the trigger and/or clamp devices.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: April 15, 2003
    Assignee: International Business Machines Corporation
    Inventors: Steven Howard Voldman, Alan Bernard Botula, David TinSun Hui
  • Patent number: 6518815
    Abstract: A MOS-type power device having a drain terminal, a source terminal, and a gate terminal; and a protection circuit having a first conduction terminal connected to the gate terminal, via a diffused resistor, and a second conduction terminal connected to the source terminal. The protection circuit has a resistance variable between a first value and a second value according to the operating condition of the power device. In a first embodiment of the protection circuit, an ON-OFF switch made by means of a horizontal MOS transistor has a control terminal connected to the drain terminal of the power device. In a second embodiment of the protection circuit, the ON-OFF switch is replaced with a gradual-intervention switch made by means of a P-channel JFET transistor having a control terminal connected to the gate terminal of the power device.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: February 11, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonio Grimaldi, Luigi Arcuri, Salvatore Pisano
  • Patent number: 6509779
    Abstract: An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: January 21, 2003
    Assignee: Atheros Communications, Inc.
    Inventors: Chik Patrick Yue, Siu-Weng Simon Wong, David Kuochieh Su, William John McFarland
  • Patent number: 6501318
    Abstract: A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: December 31, 2002
    Assignee: LSI Logic Corporation
    Inventors: Todd A. Randazzo, Brian E. Burdick, Edson W. Porter
  • Publication number: 20020021161
    Abstract: In the case where the amplitude of the input signal is large, the duty ratio of the signal output from the last stage is greatly changed as compared with the input signal. In the present invention, in order to solve this problem, there is provided a cascade connection type inverter circuit in which the inverters at the odd-number stage is fed back to the input circuit of the inverter at the first stage via an impedance element, the circuit being characterized in that a switching means is connected for supplying to an input circuit of the inverter at the first stage a compensation current for compensating a disparity between the logical threshold value of the inverter at the first stage and the central voltage of the input signal when the voltage generated between the output terminal of the inverter at the first stage and the input terminal thereof exceeds a predetermined threshold value level.
    Type: Application
    Filed: July 9, 2001
    Publication date: February 21, 2002
    Inventors: Hidehisa Murayama, Hiroyuki Yamada
  • Patent number: 6255887
    Abstract: A variable transconductance current mirror circuit includes a first field effect transistor having a gate, a source, and a drain, and a second field effect transistor having a gate, a source, and a drain. The gate of the second transistor is coupled to the gate of the first transistor, and a current source is coupled to the gates of the first and second transistors. The circuit also includes a voltage supply coupled to the sources of the first and second transistors. The circuit further includes a first diode having an anode and a cathode. The anode of the first diode is coupled to the gates of the first and second transistors, and the cathode of the first diode is coupled to the source of the first and second transistors. The first diode comprises a zener diode having a reverse breakdown voltage operable to prevent gate oxide breakdown of the first and second transistors.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: July 3, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Reed W. Adams, David J. Baldwin
  • Patent number: 6201427
    Abstract: The invention relates to circuitry for protecting n-channel load driving devices from reverse voltage conditions and for inhibiting the flow of destructive currents through such devices under reverse voltage conditions. According to one embodiment of the invention, a circuit is provided for protecting an n-channel high side load driving device from negative battery and negative transient operating conditions.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: March 13, 2001
    Assignee: Delco Electronics Corporation
    Inventors: Douglas Bruce Osborn, Douglas Joseph Huhmann, Mark Wendell Gose
  • Patent number: 6166579
    Abstract: A digitally controlled signal attenuator circuit which allows an incoming DC-clamped signal to be selectively attenuated using a set of digital control signals while maintaining its DC clamping. Multiple stages of such a circuit can be cascaded to provide for multiple forms of signal attenuation without affecting the clamping. Preferred forms of the attenuator circuit use pass transistors and transmission gates as switches for selectively altering the resistance values of resistive circuits connected in shunt to and in series with the signal being attenuated. In the case of where the subject signal is a variable DC signal such a brightness control voltage, such circuit configurations also allow the output signal voltage range to include values which are more negative than the DC clamp voltage as well as more positive.
    Type: Grant
    Filed: July 7, 1999
    Date of Patent: December 26, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Peyman Hojabri, Andrew Morrish
  • Patent number: 6154082
    Abstract: A device for the protection of an integrated circuit input/output pin against electrostatic discharges includes a first diode between a positive power supply line and an internal connection node for connection to the pin, and a second diode between the internal node and a second negative or zero supply line. The device also includes a protection transistor series-connected between the positive power supply line and the first diode, and a stack of N diodes, where N is equal to one or more, series-connected between the control electrode of the protection transistor and the first diode.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: November 28, 2000
    Assignee: STMicroelectronics S.A.
    Inventors: Patrick Bernard, Christophe Garnier, Michael Tchagaspanian
  • Patent number: 6097235
    Abstract: A field device electrostatic discharge protective circuit is described. The field device electrostatic discharge protective circuit comprises an N-type FET, an NMOS, an impedance device and a resistor. The gate and the drain of the N-type FET connect to the input port. The drain of the NMOS connects to the internal circuit. The source of the NMOS connects to ground. The gate of the NMOS connects to the source of the N-type FET. The impedance device is set between the source of the N-type FET and the ground. The resistor is set between the drain of the N-type FET and the drain of the NMOS.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: August 1, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Chung Hsu, Tien-Hao Tang
  • Patent number: 6084458
    Abstract: A bi-directional transistor structure is provided, which can help solve the problem of degraded performance due to hot carrier injection (HCI) effect that is otherwise prominent in conventional bi-directional transistors.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: July 4, 2000
    Assignee: United Microelectronics Corp.
    Inventor: Kuan-Yu Fu
  • Patent number: 6075391
    Abstract: A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower and controlled, in a manner to emulate a high voltage charging diode of the capacitance. The LDMOS transistor is controlled via a bootstrap capacitor charged by a diode at the supply voltage of the circuit, and by an inverter driven by a logic control circuit as a function of a Low Gate Drive Signal and of a second logic signal which is active during a phase wherein the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit uses a first zener diode to charge the bootstrap capacitor and the source of the transistor is connected to the supply node through a second zener diode.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: June 13, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Tarantola, Giuseppe Cantone, Angelo Genova, Roberto Gariboldi
  • Patent number: 5949273
    Abstract: A power semiconductor circuit provides a simple gate drive for switch components for the use in parallel-connected half-bridges, taking into consideration a gate voltage limitation to achieve short-circuit resistance. The circuit consists of drive circuits and main power circuits. The present invention contributes to solving the problems of the influence of the main power circuit on the drive circuit. According to the invention, switching transistors connected in parallel to the driver through separate activation and deactivation resistors, the former of relatively low resistance and the latter of relatively high resistance. Each of the switching transistors has an emitter resistor connected in parallel with a respective clamping diode to a sum point at ground, the cathode to the emitter. Each of the activation resistors is connected in series to the driver through a respective diode whose cathode is connected to the activation resistor.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: September 7, 1999
    Assignee: Semikron Elektronik GmbH
    Inventors: Paul Mourick, Dejan Schreiber, Erik Anderlohr
  • Patent number: 5939921
    Abstract: A drive circuit for a field-effect-controlled semiconductor component reduces a charging current for driving the field-effect-controlled semiconductor component when a load current limiting responds. That prevents an increase in current consumption of the drive circuit while maintaining a short switching time.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: August 17, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Silvester Strauss, Heinz Zitta
  • Patent number: 5821799
    Abstract: A level shifting circuit includes first and second load, gain and reference transistors. The first and second load transistors each have a source-drain path arranged between Vdd and Vss power supply voltages, and a gate coupled to the Vss power supply voltage. The first and second gain transistors each have a source-drain path arranged between the respective source-drain paths of the first and second load transistors and the Vss power supply voltage, and gates serving as respective differential input nodes. The first and second reference transistors each have a source-drain path arranged between the Vdd and Vss power supply voltages, and a gate coupled to respective first and second nodes serving as respective differential output nodes, the first node connecting the source-drain path of the first load transistor with the source-drain path of the first gain transistor, and the second node connecting the source-drain path of the second load transistor with the source-drain path of the second gain transistor.
    Type: Grant
    Filed: December 11, 1996
    Date of Patent: October 13, 1998
    Assignee: Cypress Semiconductor Corporation
    Inventor: Satish C. Saripella
  • Patent number: 5793245
    Abstract: A switch mode regulator circuit is provided to facilitate the conversion from one voltage level to another in a substantially power lossless manner. The circuit is particularly advantageous in instances where the power supply can be operable in a discontinuous mode, as inductor-capacitor oscillatory transients ("ringing"), along with its associated voltage spikes at the associated output transistor source, can be avoided. Such transients and their associated voltages are avoided by clamping the gate-source voltage on the circuit's output NMOS transistor over the entire positive operation voltage range.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: August 11, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Andrew Marshall, Joseph A. Devore, Raymond T. Summerlin
  • Patent number: 5668496
    Abstract: A circuit arrangement for limiting the current to be switched of an electrical load, with the power input of the electrical load being controlled by means of a Triac, said Triac being connected in series with the electrical load, with a Diac being connected to the gate terminal of the Triac, said Diac being connected in series with a resistor arrangement whose resistance value is variable for the purpose of controlling the Triac, said Triac being disconnectible from the power supply by means of a first switch, wherein a second switch is provided by means of which the series arrangement comprised of the resistor arrangement and the Diac is disconnectible from the power supply, and wherein, on turning the electrical load on, the first switch is closed first, while the second switch is closed with a time delay. Advantageously, on turning the electrical load off, the second switch is opened first, while opening of the first switch occurs with a time delay.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: September 16, 1997
    Assignee: Braun Aktiengesellschaft
    Inventor: Antonio Rebordosa
  • Patent number: 5564095
    Abstract: An enhanced nonlinear signal processor for RFI suppression using either biased null zone amplifier or a biased inverting limiter. Two or more nonlinear interference processors are connected in cascade. As a result, a deliberate tracking error, selected to provide only a small amount of relative interference rejection, is introduced into each processor. The effect of each stage is cumulative until some limit to performance improvement, determined by the input/output characteristic of each stage, is reached. The benefits of this discovery are increased dynamic range capability (higher levels of interference-to-wanted signal ratio can be fully rejected), simplification of gain control, and increased flexibility in hardware implementation options resulting from reduced sensitivity to RFI tracking error.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: October 8, 1996
    Assignee: Comsat Corporation
    Inventors: Donald S. Arnstein, Todd R. Czerner, James H. Buzzelli
  • Patent number: 5528189
    Abstract: In one form of the invention, a circuit is disclosed, the circuit comprising: a transistor Q having an input terminal 14 with an avalanche breakdown voltage to electrical ground; and one or more diodes 16 arranged in a series between the input terminal 14 and electrical ground, the diode series 16 having a forward-biased voltage drop that is smaller than the avalanche breakdown voltage.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: June 18, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: M. Ali Khatibzadeh
  • Patent number: 5483189
    Abstract: A stage of both input and output configurable for operation with low and high voltages, comprises:first (M1), second (M2) and third (M3) transistors, each having first and second terminals and a control terminal, the first and second terminals and control terminal of the first transistor (M1) being respectively connected to a first terminal of a voltage supply, the first terminal of the second transistor (M2), and a drive circuit means, the second terminal and control terminal of the second transistor (M2) being respectively connected to a circuit node (A), forming an input/output terminal of the stage (1), and to the drive circuit means, the first and second terminals and control terminal of the third transistor (M3) being respectively connected to a second terminal of the voltage supply, the circuit node (A), and the drive circuit means;at least one diode (D2) connected between the first and the second terminal of the second transistor (M2); andan input circuit (3) having a first input terminal connected to
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: January 9, 1996
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Paolo Cordini, Giorgio Pedrazzini, Domenico Rossi
  • Patent number: 5465068
    Abstract: An excitation stage having a predetermined number of semiconductor-based amplification modules parallel-connected at the input of a coupling device to couple the outputs of the amplification modules to the input of the transmission tube, as well as a diode-based limiter device positioned inside the coupling device to limit the pulses that short-circuit electrodes of the transmission tube appearing at the output of the coupling device.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: November 7, 1995
    Assignee: Thomson-CSF
    Inventor: Bernard Darges