Abstract: In certain aspects, a clamp circuit includes a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror. The clamp circuit also includes a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror. The first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror.

Abstract: An apparatus includes a plurality of parallel-connected semiconductor switches (e.g., wide bandgap transistors) and a plurality of driver circuits having outputs configured to be coupled to control terminals of respective ones of the plurality of semiconductor switches and configured to drive the parallel-connected semiconductor switches responsive to a common switch state control signal. The apparatus further includes a control circuit configured to sense respective states of respective ones of the parallel-connected semiconductor switches and to control respective ones of the driver circuits responsive to respective ones of the sensed states.

Abstract: A semiconductor device includes a first circuit unit, comprising a first buffer, a second buffer, and a first processing unit, connected to a first power supply system, and a second circuit unit, comprising a third buffer, connected to a second power supply system different from the first power supply system. The semiconductor device includes a first oscillation signal generating circuit connected to the first power supply system, and a second oscillation signal generating circuit connected to the second power supply system. A first oscillation signal generated by the first oscillation signal generating circuit is input to the first buffer. A second oscillation signal generated by the second oscillation signal generating circuit is input to the second buffer through the third buffer. The first buffer selectively outputs the input first oscillation signal and the second buffer selectively outputs the input second oscillation signal based on a value of a control signal.

Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.

Abstract: An apparatus includes a first AC (alternating current) coupling circuit configured to receive a first end of a differential signal and output a first coupled signal in accordance with a bias voltage; a second AC coupling circuit configured to receive a second end of the differential signal and output a second coupled signal in accordance with the bias voltage; a first complementary joint-control cascode pair configured to shunt the first end of the differential signal to a DC (direct current) node in accordance with a joint control by the first coupled signal and the second coupled signal; and a second complementary joint-control cascode pair configured to shunt the second end of the differential signal to the DC node in accordance with a joint control by the first coupled signal and the second coupled signal. A related method is also provided.

Abstract: A method includes providing a resonant attenuation circuit comprising a first active shorting device connected to a proximal end of an inductive element and a second active shorting device connected to a distal end of the inductive element. The method also includes providing a first control signal to the first active shorting device that places the first active shorting device in a region of operation where incremental increases or decreases in voltage change a shorting impedance of the second active shorting device. A signal attenuator includes a signal propagation path and a plurality of shorting units sequentially attached to the signal propagation path and a control circuit configured to control a level of attenuation provided by each shorting unit. The control circuit and a corresponding method activates subsequent shorting units only if all previous shorting units are at least partially activated.

Abstract: Disclosed is a current sampling circuit including a proportional current output circuit and a full differential common mode negative feedback circuit, specifically the proportional current output circuit is configured to calculate a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current, and to output the first proportional current and the second proportional current to the full differential common mode negative feedback circuit; and the full differential common mode negative feedback circuit is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current. Further disclosed is a current sampling method.

Abstract: Apparatus and methods for ultrasound transmit switching are provided. In certain implementations, a transmit switch includes a bias polarity control circuit, a bias circuit, a first high voltage field effect transistor (HVFET), and a second HVFET. The sources of the first and second HVFETs are connected to one another at a source node, the gates of the first and second HVFETs are connected to one another at a gate node, and the drains of the first and second HVFETs are connected to an input terminal and an output terminal, respectively. The bias circuit and the bias polarity control circuit are each electrically connected between the source node and the gate node. The bias polarity control circuit can turn on or off the HVFETs by controlling a polarity of a bias voltage across the bias circuit, such as by controlling a direction of current flow through the bias circuit.

Abstract: Disclosed is a semiconductor device that includes an N-channel MOS transistor and a control voltage generation circuit. The N-channel MOS transistor controls the supply of a power supply voltage obtained by stepping down a DC voltage. The control voltage generation circuit clips the gate voltage of the N-channel MOS transistor at a control voltage not higher than a predetermined voltage in accordance with the DC voltage.

Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

Abstract: An automatic quadrature network with amplitude and phase detection produces quadrature signals for an input oscillator signal, the quadrature signals being equal in amplitude and having ideal quadrature phase between them. An RC circuit provides one quadrature path, and a CR circuit provides another quadrature path. The outputs from the RC/CR circuits are amplitude detected to produce an amplitude control signal. The outputs also are amplitude limited, and the phase between the limiter outputs is detected to produce a phase control signal. The amplitude and phase control signals are combined to generate respective control signals for the RC/CR circuits to automatically align them so that the quadrature signals are of equal amplitude and ideal quadrature phase.

Abstract: A semiconductor integrated circuit includes a first voltage supply unit, a second voltage supply unit configured to supply a voltage with a level different from that of the first voltage supply unit, and a voltage stabilizing unit connected between the first and second voltage supply units, and including at least one discharge path that includes a clamping section configured to temporarily drop a level of a voltage introduced from the first or second voltage supply unit, and a discharge section configured to discharge the voltage having passed through the clamping section to the second or first voltage supply unit.

Abstract: A signal processing circuit includes a detection circuit detecting a high frequency signal being input; and an output signal adjustment circuit which is provided in a rear end of the detection circuit and includes a first field effect transistor and a second field effect transistor. The first field effect transistor has a drain connected to an output end of the detection circuit, a source connected to a gate of the second field effect transistor, and a gate connected to a drain of the second field effect transistor. The second field effect transistor has a source connected to a ground. An output signal is output from the source of the first field effect transistor. When an input level of the high frequency signal is equal to or higher than a predetermined level, a magnitude of the output signal is maintained at a predetermined magnitude.

Abstract: A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (PFC) circuit comprising the semiconductor device. A power supply comprising the PFC circuit.

Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter.

Abstract: The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to the gate of the power element. The switching field-effect transistors have small off-state current.

Abstract: A switching circuit device has a first transistor which has a drain coupled to a high-potential terminal, a source coupled to a low-potential power supply, and, a driving circuit, which outputs, to a gate of the first transistor in response to an input control signal, a pulse having a potential higher than a threshold voltage of the first transistor and a potential of the low-potential power supply, wherein the driving circuit has a first inverter including a second transistor provided between the gate and the source of the first transistor, wherein when the first transistor changes from on to off due to the pulse, the second transistor conducts and short-circuits the gate and the source of the first transistor.

Abstract: A power management integrated circuit includes pairs of high-side and low-side drivers, sensing circuitry, and a processor. The high-side and low-side drivers are used in combination with external discrete NFETs to drive multiple windings of a motor. The N-channel LDMOS transistor of each high-side driver has an associated isolation structure and a tracking and clamping circuit. If the voltage on a terminal of the integrated circuit pulses negative during a switching of current flow to the motor, then the isolation structure and tracking and clamping circuit clamps the voltage on the isolation structure and blocks current flow from the substrate to the drain. An associated ESD protection circuit allows the voltage on the terminal to pulse negative. As a result, a large surge of current that would otherwise flow through the high-side driver is blocked, and is conducted outside the integrated circuit through a body diode of an external NFET.

Abstract: A voltage swing decomposition circuit includes first and second clamp circuits and a protection circuit. The first clamp circuit is configured to clamp an output node of the first clamp circuit at a first voltage level when an input node of the voltage swing decomposition circuit has a voltage higher than the first voltage level. The second clamp circuit is configured to clamp an output node of the second clamp circuit at a second voltage level, higher than the first level, when the voltage of the input node is lower than the second voltage level. The protection circuit is coupled to the output nodes of the first and second clamp circuits, and is configured to selectively set an output node of the protection circuit to the first or second voltage level. The first and second clamp circuits are coupled together by the output node of the protection circuit.

Abstract: A contactless card includes an inductive circuit configured to send and receive signals, a rectifier circuit coupled to the inductive circuit and configured to generate a DC voltage from an AC voltage generated by the inductive circuit, a clamp circuit configured to limit the DC voltage, a regulator circuit configured to regulate the DC voltage and a control circuit configured to selectively enable and disable the clamp circuit and the regulator circuit.

Abstract: A voltage clamping circuit for protecting an input/output (I/O) terminal of an integrated circuit from over shoot and under shoot voltages includes transistors connected to form a current conducting path. A voltage at the I/O pin is detected using a voltage detection circuit. The current conducting path is switched on when the voltage at the I/O pin exceeds a predetermined value.

Abstract: Conventional circuits often have undesirable characteristics to due “hot spots” or use a large amount of area. Here, however, a charging circuit is provides that uses an improved driver. Namely, an amplifier within a current sensor is used to control the rate that a switch can charge an external capacitor. This is accomplished through the adjustment of the gain of the amplifier during a charging mode.

Abstract: A current driving circuit includes a constant current source circuit delivering a driving current to a load, and an output voltage difference amplifier circuit detecting a voltage change produced at a load driving end during a preset time period and delivering a current or a voltage corresponding to the voltage change to the load during a time period different from the preset time period. During first time period, capacitance circuit compares potential during a preceding time period to that during the current time period, and causes a potential at the load driving end during the current time period to store in any of capacitance elements depending on result of comparison. The amplifier circuit buffering an average value of the potential values stored in the capacitance elements during the second time period following the first time period, to deliver the average value to the load.

Abstract: The present disclosure provides a brushless motor driving circuit capable of clamping an output voltage at a proper voltage, even when a power source voltage changes. Namely, a pre-driver circuit generates a voltage for driving a brushless motor from a source voltage by turning on/off first and second PMOS transistors and first and second NMOS transistors in an H bridge circuit of a drive voltage generating circuit, and applies the voltage to a coil of the brushless motor. A first clamp circuit turns on/off the first NMOS transistor on the ground side so that the output voltage at a first output terminal becomes equal to or lower than the source voltage. A second clamp circuit turns on/off the second NMOS transistor on the ground side so that output voltage at a second output terminal becomes equal to or lower than the source voltage.

Abstract: A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.

Abstract: A level shifter shifts the level of an input signal from a second voltage domain to a first voltage domain. To accommodate different input signal levels (e.g., including sub-threshold input signal levels) that may arise due to changes in the supply voltage for the second voltage domain, current for a latch circuit of the level shifter is limited based on the supply voltage for the second voltage domain. In this way, a drive circuit of the level shifter that controls the latch circuit based on the input signal is able to initiate a change of state of the latch circuit over a wide range of input signal levels.

Abstract: Apparatus and methods are disclosed, such as those involving an electronic device. One such apparatus includes a transmitter; a receiver; and a transmit/receive switch configured to electrically block the receiver from the transmitter during a transmit period. The transmit/receive switch includes one or more MOSFETs coupled between an input node and an output node, the input node being electrically coupled to the transmitter, the output node being electrically coupled to the receiver. The one or more MOSFETs are configured to be off during the transmit period. The transmit/receive switch further includes a clamp circuit configured to couple the output node to ground during the transmit period. This configuration effectively protects the receiver while minimizing switching artifacts.

Abstract: A receiver circuit is provided which receives an external signal of high voltage and provides a corresponding internal signal of low voltage. The receiver circuit includes a voltage limiter, a level down shifter and an inverter of low operation voltage. The level down shifter has a front node and a back node, and includes a transistor with a gate and a source respectively coupled to the voltage limiter and the inverter at the front node and the back node. The voltage limiter limits level of the external signal transmitted to the front node, the level down shifter shifts down a signal of the front node by a cross voltage to generate a signal of the back node, and the inverter inverts the signal of the back node to generate the internal signal.

Abstract: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

Abstract: In current driving circuit a desired value of a driving current is promptly written in a load of each pixel despite load variations that may occur in each pixel. A constant current source circuit delivers a driving current Idata to a load. An output voltage difference amplifier circuit detects a voltage change produced at a load driving end within a preset time period, and delivers a current or a voltage corresponding to the voltage change during a time period different from the preset time period. The output voltage difference amplifier circuit temporally repeats detection of the voltage change and delivery of the current or the voltage to the load.

Abstract: A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.

Abstract: A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.

Abstract: An attenuator includes a first terminal, a second terminal, a first circuit coupled between the first and second terminals and including a field effect transistor including a gate terminal coupled to a resistor, a second circuit coupled between the first circuit and the second terminal and coupled to the first circuit via a node, and a third circuit coupled to the node.

Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.

Abstract: A method and a device for reducing noise induced errors. The device includes: a latch that includes a latch input node; a voltage limiting transfer circuit connected between a first input node and between the latch; wherein the voltage limiting transfer circuit is adapted to selectively transfer an input signal from the first input node to the latch during transfer mode; and to prevent a transfer of an input signal from the first input node to the latch by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range.

Abstract: Apparatus and methods are disclosed, such as those involving an electronic device. One such apparatus includes a transmitter; a receiver; and a transmit/receive switch configured to electrically block the receiver from the transmitter during a transmit period. The transmit/receive switch includes one or more MOSFETs coupled between an input node and an output node, the input node being electrically coupled to the transmitter, the output node being electrically coupled to the receiver. The one or more MOSFETs are configured to be off during the transmit period. The transmit/receive switch further includes a clamp circuit configured to couple the output node to ground during the transmit period. This configuration effectively protects the receiver while minimizing switching artifacts.

Abstract: A semiconductor apparatus operates based on a first voltage, a second voltage lower than the first voltage, and a third voltage in between the first and second voltages, and includes an output circuit including at least one transistor where a signal having an amplitude ranging from the second to first voltages is input to a gate, and a control circuit that generates a first control signal controlling a gate voltage of a transistor included in the output circuit, a second control signal controlling a voltage in a back-gate region of the transistor, and a third control signal controlling a voltage in a deep well region. The control circuit sets a voltage difference between the first and second control signals to be equal to or smaller than the larger one of a voltage difference between the first and third voltages and a voltage difference between the second and third voltages.

Abstract: A preset circuit of an audio power amplifier includes an inverter and a voltage drop device. The inverter receives an input signal to output an output signal, and includes a first switch and a second switch. The first switch is controlled with the input signal, and has a first terminal coupled to a power voltage and a second terminal for outputting the output signal. The second switch is controlled with the input signal, and has a third terminal for outputting the output signal and a fourth terminal coupled to a low reference voltage. The voltage drop device is coupled between the first terminal of the first switch and the power voltage and configured to lower the power voltage. The output signal is kept at a low level when the voltage drop device and the first switch are de-actuated due to the power voltage having a level below a first threshold.

Abstract: A clamp circuit includes a clamp circuit which limits an output of a source follower circuit, includes a first Nch transistor, a first constant current source connected between ground and the output terminal, a second Nch transistor having a gate that receives a bias voltage and a source connected to the output terminal of the source follower circuit, a second constant current source connected between the power supply and a drain of the second Nch transistor, and a first Pch transistor having a gate connected to the drain of the second Nch transistor, a source connected to the power supply, and a drain connected to the output terminal of the source follower circuit.

Abstract: An on-chip mode-setting circuit and method are provided for a chip having an output driver with an output terminal connected to a pin of the chip. The pin may be defined between two states from exterior of the chip. The on-chip mode-setting circuit includes an electronic element connected to a bias input of the output driver for producing a voltage when the pin is defined at one of the two states, and a voltage detector for monitoring the voltage to determine which one of the two states the pin is at, and producing a mode-setting signal accordingly.

Abstract: A semiconductor integrated circuit includes a first clock pin controller that receives a mirror function signal and a test mode signal to generate a first input buffer control signal in response to the mirror function signal in a normal mode. A second clock pin controller receives the mirror function signal and the test mode signal to generate a second input buffer control signal, which is an inverted signal of the first input buffer control signal, in response to the mirror function signal in the normal mode. An input buffer unit generates output signals of first and second pins in response to the first input buffer control signal and the second input buffer control signal, respectively.

Abstract: Clamp networks are provided to insure successful operation of a variety of electronic circuits that are realized in the form of integrated circuit chips. These networks are especially suited for use in chips in which on-chip circuits generate a voltage to bias the chip substrate relative to the chip ground. The clamp networks are configured to drive a current between the chip ground and the chip substrate whenever the chip substrate begins to rise above the chip ground during turn on of the chip input voltage. The clamp networks thus insure that the chip substrate is properly biased when the input voltage has been established and that the chip, therefore, functions as intended.

Abstract: The invention relates to the field of signal processing. It is an object of the invention to provide for limitation of a signal voltage to a predetermined maximum voltage (Vmax). To this end, an input signal (Vin) is applied to a voltage divider which includes a variable-resistance component (T1) whose resistance is controlled by a control signal. An output signal (Vin?) is picked-up at the variable-resistance component (T1). The control signal is generated as an amplified difference between the output signal (Vin?) and a fixed reference voltage (Vmax/2), so that for an “overvoltage case” in which the value of the input signal (Vin) exceeds that of a predetermined maximum voltage (Vmax) the output signal (Vin?) is kept substantially constant.

Abstract: A method and a device for reducing noise induced errors. The device includes: a latch that includes a latch input node; a voltage limiting transfer circuit connected between a first input node and between the latch; wherein the voltage limiting transfer circuit is adapted to selectively transfer an input signal from the first input node to the latch during transfer mode; and to prevent a transfer of an input signal from the first input node to the latch by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range.

Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

Abstract: An active over-voltage clamp system includes at least one over-voltage detector that is responsive to an input voltage and provides a first current. The system also includes a replica over-voltage circuit that provides a second current, and circuitry subtracting the second current from the first current to produce a difference current. The system further includes a differential clamp activated in response to the difference current. The differential clamp prevents the input voltage from increasing beyond a target voltage.

Abstract: An active clamp circuit for avalanching and clamping voltage at a gate terminal of a first transistor connected to a power source. The active clamp circuit includes a second transistor for turning ON the first transistor; a third transistor having EPI breakdown voltage less than that of the first transistor; a resistor coupled between a node and source and gate terminals of the third transistor; and an amplifier for comparing voltage on the resistor to a reference voltage and providing an output signal to control the second transistor, wherein, when the third transistor avalanches and the voltage across the resistor exceeds the reference voltage, the output signal turns ON the second transistor thereby clamping the gate terminal of the first transistor, wherein the active clamp circuit tracks the channel characteristic of the first transistor.

Abstract: Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (Vt) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the Vt of an NMOS TFT (Vtn) and the Vt of a PMOS TFT (Vtp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.

Abstract: A semiconductor integrated circuit device may include a first internal circuit operating at a first voltage higher than a power supply voltage of the device, and a second internal circuit operating at a second voltage lower than the first voltage. An interface circuit may be provided to restrict a voltage transferred from the first internal circuit to the second internal circuit. The first internal circuit may include a metal oxide semiconductor (MOS) transistor having a relatively thick gate insulation layer, and the second internal circuit may have a MOS transistor having a relatively thin gate insulation layer. The interface circuit, by restricting voltage, may reduce an electric field applied to the gate insulation layer of the second MOS transistor in an effort to prevent a reduction in turn-on speed of the second MOS transistor.

Abstract: A clamping circuit clamps a voltage received by an n-type semiconductor region without using a Schottky transistor. The clamping circuit includes a current mirror as well as first and second bipolar transistors. The current mirror receives a first current and supplies a second current in response. The first current is received by the first bipolar transistor, and the second current is received by the second bipolar transistor. The difference between the base-emitter junction voltages of the first and second bipolar transistors, in part, defines the voltage at which the n-type region is clamped. To start-up the circuit properly, current is withdrawn from the base/gate terminals of the transistors disposed in the current mirror. The circuit optionally includes a pair of cross-coupled transistors to reduce the output impedance and improve the power supply rejection ratio.