Abstract: A system to control convergence of a loop to a reference value. A device, under control of the control loop, generates an output signal. A comparator compares the output signal to a reference value. Responsive to the output signal being less than the reference value, outputting an up signal and, responsive to the output signal being greater than the reference value, outputting a down signal. A counter is configured to maintain a counter value which is incremented in response to an up signal and decremented in response to a down signal. The counter outputs a gain control value. An up/down signal tracker is configured to track a pattern of up signals and down signals and compare the tracked pattern to one or more predetermined patterns such that, responsive to the up signals and down signals matching one of the one or more predetermined patterns, the counter size is decreased.

Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a first phase, selecting a global signal line, selecting a first string select line, unselecting a second string select line, selecting a first word line, and unselecting a second word line; sensing during a second phase; in a third phase, keeping voltages of the global signal line, the selected first word line and the unselected second word line, unselecting the first string select line and selecting the second string select line to switch voltages of the first and the second string select lines; and sensing during a fourth phase.

Abstract: An embodiment LED driver system comprises a power transistor configured to be selectively activated for generating a driving current for an array of LEDs, the power transistor having a first conduction terminal coupled to the array of LEDs and a second conduction terminal coupled to a reference resistor; an operational amplifier having a non-inverting input for receiving a reference voltage, an inverting input coupled to the second conduction terminal of the power transistor, and an output terminal coupled to a first conduction terminal of a transmission gate having a second conduction terminal coupled to a control terminal of the power transistor and a control terminal for receiving an enable signal; and a slew rate control unit configured to control the slew rate of the driving current.

Abstract: A level adjusting circuit includes a parallel resistor-capacitor (RC) sub-circuit, a first diode and an adjustable voltage supply. The RC sub-circuit includes an input capacitor and an input resistor, and includes an input node electrically connected to a driving signal source for receiving a driving signal therefrom, and an output node that outputs an adjusted driving signal. The first diode and the adjustable voltage supply are electrically connected, and are further electrically connected to the output node and a reference voltage node, respectively.

Abstract: A gate-driving circuit includes a unidirectional module and two driving modules, and has a low-potential terminal, an output terminal, and two input terminals via which two driving signals are received. Each of the driving modules includes a capacitor and a resistor that are connected in parallel and between the output terminal and the respective one of input terminals, a power source that is connected between the output terminal and the low-potential terminal, and a diode that is connected between the output terminal and the power source. The unidirectional module is connected between the output terminal and one of the driving modules, and allows an electrical signal to pass only from the one of the driving modules to the output terminal.

Abstract: Different embodiments on hearing enhancement enhancing a user's hearing. For example, a system can include an interface unit with a directional speaker and a microphone. The microphone captures input audio signals that are transformed into ultrasonic signals. The speaker transmits the ultrasonic signals, which are transformed into output audio signals by interaction with air. At least part of the output audio signals is modified to enhance the hearing of the user. Based on the system, the user's ear remains free from any inserted objects and thus is free from annoying occlusion effects. Compared to existing hearing aids, the system is relatively inexpensive. In another embodiment, the system can also be used as a phone. In another embodiment, the system can also access audio signals from other portable or non-portable instruments, wired or wirelessly, such as from home entertainment units, phones, microphones at a conference or speakers at a movie theater.

Abstract: A compensation device for compensating leakage currents has a differential current measurement device, a first signal generation device, an amplifier and a feeder device. The first signal generation device is designed to generate a first compensation current specification signal (I_COMP_S1) suitable for the compensation from the first signal (I_DIFF) from the differential current measurement device by way of analog signal processing and to feed this first compensation current specification signal (I_COMP_S1) to the amplifier in analog or digitized form. The amplifier is designed to generate a compensation current (I_COMP) on the basis of the first compensation current specification signal (I_COMP_S1), and the feeder device is designed to allow the compensation current to be fed in at at least one of the active conductors.

Abstract: A compensation device (20) for compensating for leakage currents has a differential current measuring device (22), a supply network detection device (42; 45), a control device (26), an amplifier (27), a compensation current selection device (36) and a feed-in device (39, 41). The supply network detection device (42; 45) generates a second signal (V_GRID; V_ES) characterizing the supply network (L1, L2, L3, N) connected to the active conductors (51, 52, 53, 54) and to supply it to the control device (26). The compensation current selection device (36) feeds in the compensation current (I_COMP) on the basis of a third signal (V_SEL) on at least one of the at least two different active conductors (51, 54), and the third signal (V_SEL) is dependent on the second signal (V_GRID; V_ES) to select at least one active conductor (51, 54) suitable for the connected supply network for the feed-in operation.

Abstract: Structures for a circuit including field-effect transistors and methods for fabricating and operating such circuits. A plurality of logic cells with a first well and a second well. The first well is directly connected with ground. A tap cell includes an inverter having an output connected with the second well. The inverter is configured to provide a bias voltage having a first state in which a positive voltage is supplied to the second well and a second state in which the second well is connected with ground.

Abstract: In an embodiment, an apparatus may include first input and a second input to receive a differential input signal and may include a diode including an anode coupled to the first input and including a cathode coupled to the second input. The apparatus may further include a feedback circuit having an input coupled to the cathode and an output coupled to the anode. The feedback circuit may be configured to apply a feedback signal to the diode to maintain a substantially constant direct current across the diode. The apparatus may also include a comparator coupled to the feedback circuit and configured to compare the feedback signal to a threshold to detect radio frequency energy in the input signal in response to changes in the feedback signal.

Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Abstract: Mixers are described which allow for information sharing in redundant systems, while providing sufficient isolation between redundant system components to enable fault-tolerant operation.

Abstract: Provided is a power supply voltage monitoring circuit capable of accurately detecting a power supply voltage with a small circuit scale and low power consumption. The power supply voltage monitoring circuit includes: a signal output circuit configured to output a signal voltage representing saturation characteristics with respect to an increase in power supply voltage; and a signal voltage monitoring circuit configured to output a signal representing that the signal voltage of the signal output circuit is normal, the signal voltage monitoring circuit including: a PMOS transistor including a gate connected to an output terminal of the signal output circuit; a first constant current circuit connected to a drain of the PMOS transistor; and an inverter including an input terminal connected to the drain of the PMOS transistor.

Abstract: A resistive divider circuit for differential signaling is disclosed. The resistive divider includes a first branch and a second branch and each branch has an input, a first resistive component comprised of a number of unit resistors, a second resistive component comprised of a number of unit resistors, and an output connected between the first resistive component and the second resistive component, the output forming a differential mode output. The first resistive component and the second resistive component are comprised of an equal number of unit resistors.

Abstract: According to at least one example embodiment, a method and corresponding system, or circuit, for calibrating a reference voltage of a single-ended receiver, include applying a clock signal and a reference voltage signal as inputs to the differential amplifier of the single-ended receiver. The differential amplifier provides an output signal, the output signal is processed, and an indication of a duty cycle associated with an output signal of the amplifier is evaluated. Based on the evaluated indication of the duty cycle, a control logic module, or circuit, adjusts a level of the reference voltage signal. The process of evaluating the indication of the duty cycle and adjusting the reference voltage level is repeated for a number of iterations.

Abstract: The even order harmonic distortion in a differential circuit is reduced or eliminated by treating the amplitude and phase mismatch sources that cause the distortion as impedance mismatches, and utilizing switched resistor circuitry that adjusts the load resistance to reduce the effects of the amplitude mismatch sources, and switched capacitor circuitry that adds shunt capacitance to reduce the effects of the phase mismatch sources.

Abstract: An electronic component includes: a first amplifier configured to amplify one of differential signals; a second amplifier configured to amplify another one of the differential signals; a sensor configured to measure voltages of a first output signal outputted from the first amplifier and a second output signal outputted from the second amplifier; and a controller configured to control, based on the voltages measured by the sensor, either one or both of a current and a resistance value of the first amplifier so that a common voltage of the first output signal and a common voltage of the second output signal are approximate to each other.

Abstract: A semiconductor device includes a reference current generator suitable for generating a reference current, a current-voltage converter suitable for generating a first reference voltage and a second reference voltage in response to the reference current, and an analog-digital converter suitable for generating a digital code value based on a voltage difference between the first and second reference voltages, wherein the reference current generator includes a current control unit for controlling the reference current in response to the digital code value.

Abstract: A method and system are disclosed for calibrating a mid-voltage node in an integrated circuit including an input-output circuit having charge-recycling stacked voltage domains including at least first and second voltage domains. In one embodiment, the method comprises transmitting data through the input-output circuit, including transmitting a first portion of the data across the first voltage domain, and transmitting a second portion of the data across the second voltage domain. The method further comprises measuring a specified characteristic of the data transmitted through the input-output circuit; and based on the measured specified characteristic, adjusting a voltage of said mid-voltage node to a defined value. The voltage of the mid-voltage node may be adjusted to accomplish a number of objectives, for example, to achieve a desired trade-off between power and performance, or so that the two voltage domains have the same performance.

Abstract: A switching circuit device has a first transistor which has a drain coupled to a high-potential terminal, a source coupled to a low-potential power supply, and, a driving circuit, which outputs, to a gate of the first transistor in response to an input control signal, a pulse having a potential higher than a threshold voltage of the first transistor and a potential of the low-potential power supply, wherein the driving circuit has a first inverter including a second transistor provided between the gate and the source of the first transistor, wherein when the first transistor changes from on to off due to the pulse, the second transistor conducts and short-circuits the gate and the source of the first transistor.

Abstract: A semiconductor apparatus includes an input terminal to which an input voltage is applied; an output terminal at which an output voltage is obtained; a power supply circuit unit configured to generate the output voltage from the input voltage, the output voltage having a value corresponding to a duty cycle of a voltage setting signal that is externally applied to the semiconductor apparatus; and a determination circuit unit determining whether the voltage setting signal has a predetermined signal level for the duration of a first predetermined time or longer. The determination circuit unit activates the power supply circuit unit when the voltage setting signal does not have the predetermined signal level for the duration of the first predetermined time or longer. The power supply circuit unit is deactivated when the voltage setting signal has the predetermined signal level for the duration of the first predetermined time or longer.

Abstract: In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.

Abstract: A signal swing trimming apparatus calibrates a swing level of an output signal generated from a transmitting device to a receiving device including: a comparing device coupled to the output signal for comparing the swing level of the output signal with a target swing level and generating a comparison output signal, and an adjusting device coupled to the comparing device and the transmitting device for controlling the transmitting device to adjust the swing level of the output signal according to the comparison output signal, wherein the signal swing trimming apparatus is configured to calibrate the swing level of the output signal during a hand-shake process between the transmitting device and the receiving device.

Abstract: An adaptive phase-lead compensation (zero) circuit is disclosed that can be added to a circuit (e.g., a CMOS-based LDO) to ease the compensation and increase the phase margin of the circuit. By using the disclosed adaptive phase-lead compensation circuit, an adjustable resistance can be connected to any nodes in the compensated circuit rather than just to the voltage source (VDD) or ground (GND), allowing the Miller Effect to be used via a Miller capacitor.

Abstract: A regulating circuit is used with a buffer circuit. The buffer circuit at least includes a metal-oxide-semiconductor transistor and a voltage output terminal. The voltage output terminal is connected to a drain terminal of the metal-oxide-semiconductor transistor of the buffer circuit. The regulating circuit includes a first metal-oxide-semiconductor transistor and a second metal-oxide-semiconductor transistor. The first metal-oxide-semiconductor transistor has a source terminal and a drain terminal connected to a voltage source and a connecting node, respectively. The connecting node is electrically connected to a substrate of the metal-oxide-semiconductor transistor of the buffer circuit. The second metal-oxide-semiconductor transistor has a drain terminal and a source terminal connected to the connecting node and the voltage output terminal, respectively. A substrate of the second metal-oxide-semiconductor transistor is electrically connected to the connecting node.

Abstract: Provided is an offset-voltage calibration circuit. The circuit includes a comparator configured to receive at least two comparison voltages and output a result of a comparison between the comparison voltages, an up/down counter (UDC) configured to output an up-counting or down-counting output signal in response to an output signal of the comparator, and a current digital-to-analog converter (DAC) configured to control the amount of current supplied from a node to which the comparison voltage is applied, in response to the output signal of the UDC and control the magnitude of the comparison voltage.

Abstract: A digital level control circuit, such as an Automatic Gain Control, includes a plurality of digitally selectable signal levels with transitions between levels gradually varied to avoid signal output level discontinuities. An up/down counter may be used to incrementally stepwise transition an output signal between the digitally selectable output levels. Stepwise application of a control signal to the appropriate switching elements (e.g., FETs) forming an attenuator circuit may be implemented to moderate a switching time of the switching elements to provide a more gradual transition between element operating states. A deglitch circuit may be employed to latch the switching elements to achieve the desired state at the end of a desired switching transition period.

Abstract: A method and a circuit may have an ability to provide constant currents of a certain set value, the rising and falling edges of which may be shorter than the design minimum on-phase. Essentially, these results may be obtained by keeping an operational amplifier that controls the output power switch in an active state during off-phases of an impulsive drive signal received by the current source circuit in order to maintain the output voltage of the operational amplifier at or just below the voltage to be applied to the control terminal of the output power switch during a successive on-phase of a received drive pulse signal.

Abstract: Simulation method and system for analyzing the stability of a modeled electronic circuit. Simulation of the transient response to a desired input stimulus is performed in a piece-wise fashion, in a sequence of transient time points. At one or more user-specified time points (“tpunch” points) within the transient interval, the state of the circuit in the transient response at that time point is applied to the model as if it were a DC operating point, and the small-signal stability of the circuit under those conditions is analyzed. Transient instability of the circuit is thus discovered by way of simulation, allowing the designer to determine the cause and cure of that instability.

Abstract: Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages.

Abstract: A semiconductor apparatus includes an input terminal to which an input voltage is applied; an output terminal at which an output voltage is obtained; a power supply circuit unit configured to generate the output voltage from the input voltage, the output voltage having a value corresponding to a duty cycle of a voltage setting signal that is externally applied to the semiconductor apparatus; and a determination circuit unit determining whether the voltage setting signal has a predetermined signal level for the duration of a first predetermined time or longer. The determination circuit unit activates the power supply circuit unit when the voltage setting signal does not have the predetermined signal level for the duration of the first predetermined time or longer. The power supply circuit unit is deactivated when the voltage setting signal has the predetermined signal level for the duration of the first predetermined time or longer.

Abstract: An alternating-current (AC) coupling integrated circuit (IC) suppresses signal errors introduced by a steady-state input signal. The IC includes an operational amplifier, a true direct-current (DC) bias network, a complimentary DC-bias network and first and second feedback elements. The operational amplifier has an inverting input, a non-inverting input and an output. The true DC-bias network has first and second branches that are coupled to one another and the non-inverting input. The complimentary DC-bias network has third and fourth branches that are coupled to one another and the inverting input. First and second feedback elements generate first and second control signals in response to a characteristic of one of the true input signal and the complimentary input signal. The control signals prevent the voltage at the inputs to the operational amplifier from reaching an equivalent, steady-state, DC-bias voltage.

Abstract: A mixer circuit includes: a mixer circuit including a first transistor pair to output a first differential input signal and a second transistor pair to output a second differential input signal by inversing the first differential signal; a local signal supply circuit to supply a pair of local signals to gates of the first transistor pair and the second transistor pair; an operational amplifier including an input pair coupled to an output pair of the mixer circuit and an output pair coupled to the input pair via feedback resistors, the operational amplifier to amplify the first differential input signal and output a differential output signal; a common mode feedback circuit to control a center voltage of the differential output signal so that the center voltage maintains a common voltage; and a common voltage generator circuit to generate the common voltage according to an amplitude of the local signal.

Abstract: A switched-capacitor current reference contains an amplifier, a current mirror circuit and a feedback circuit. In an embodiment, the feedback circuit receives a time-varying voltage waveform at a node connected to a switched-capacitor block used within the current mirror circuit, and is operated to provide a constant voltage waveform on an input terminal of the amplifier. Ripple in the output reference current provided by the switched-capacitor current reference is minimized or eliminated.

Abstract: An output slew-rate controlled interface is provided. The output slew-rate controlled interface includes: a standard slew-rate range generating circuit, for generating at least one standard signal defining a standard slew-rate range; a slew-rate comparing circuit, coupled to the standard slew-rate range generating circuit and a load circuit coupled to the interface, for comparing a response slew-rate of a response signal from the load circuit with the standard slew-rate range and producing a comparison result; and an outputting circuit, coupled to the slew-rate comparing circuit, for adjusting an output slew-rate of an output signal according to the comparison result and outputting the output signal to the load circuit.

Abstract: AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.

Abstract: A method for automatic gain control of a front-end for a digital video receiver is provided. The method includes the following steps. First, a radio frequency signal is received and converted to an intermediate frequency signal. Then, the IF signal is amplified according to a gain. Next, the amplified IF signal is demodulated into a base-band signal, and the base-band signal is encoded into a transport stream. After that, a DC level of a pulse width modulation signal is controlled by at least one variable resistor to adjust the gain, the PWM signal being related to a setting of the gain. Afterwards, a BER measurement at each potential setting of the gain and the variable resistor under one or more power levels of the RF signal is read, and an optimum setting of the gain and the variable resistor is selected according to the BER measurements.

Abstract: A peak detect-and-hold circuit and method thereof using ramp sampling technique includes utilizing two sampling signals of different slopes to sample an input voltage for respective tracking voltages; comparing the held tracking voltage sampled with the sampling signal of a smaller slope and the input voltage to determine whether the input voltage is rising or falling, and if the input voltage starts falling, the held tracking voltage sampled with the sampling signal of a larger slope is taken as the peak. The peak detect-and-hold circuit using ramp sampling technique controls respective tracking voltages by comparing the input voltage with the sampling signals rather than the feedback tracking voltage. Also, it uses the input voltage directly rather than an operational transconductance amplifier to charge holding capacitors for the tracking voltages. Therefore, the errors of peak detecting and holding, namely the pedestal voltage, overshoot voltage and voltage droop are reduced.

Abstract: A multiplexed input/output (I/O) system detects leakage currents on a selected input channel. The system includes a leakage detection multiplexer connected to provide an output selected from one of a plurality of input channels. In addition, the leakage detection multiplexer provides as part of the output measured leakage currents associated with the selected input channel. Based on the detected leakage currents, a determination can made regarding whether the detected leakage currents have compromised the integrity of the multiplexer output. In addition, the detected leakage current can be used to compensate the output provided by the multiplexer to account for the presence of leakage currents on the selected channel.

Abstract: A first bias circuit outputs a first direct-current voltage to charge a first capacitor based on a clock signal. A second bias that outputs a second direct-current voltage to charge a second capacitor based on a clock signal. A first MOS transistor has a gate and a source. The first direct-current voltage is applied between the gate and the source of the first MOS transistor to bias the gate of the first MOS transistor. A second MOS transistor has a gate and a source, and a drain connected to the source of the first MOS transistor. The second direct-current voltage is applied between the gate and the source of the second MOS transistor to bias the gate of the second MOS transistor. A coupling capacitor has a first end connected to the source of the first MOS transistor, and a second end to which an alternating-current signal is input.

Abstract: An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generator for generating a trimming selection signal and a trimming enable signal by using an inputted address signal, and an internal power voltage level controller for controlling the levels of the internal power voltages by using the trimming selection signal that is outputted under control of the trimming enable signal.

Abstract: An apparatus for an event tolerant circuit including a latch. The event tolerant circuit may maintain correct data values even after the occurrence of an event such as a soft error. The event tolerant circuit may introduce a delay in a feedback loop, thereby passing the glitch value to an element in the feedback loop at different times, thus preventing the propagation of the glitch through the event tolerant circuit.

Abstract: According to one embodiment, a threshold adjusting apparatus for a clocked comparator, the clocked comparator comparing an input signal with a threshold in accordance with a clock, the threshold adjusting apparatus comprises an output detection module configured to detect an output from the clocked comparator with the threshold while changing the threshold and a setting module configured to set the threshold when the output detection module detects a change in the output from the clocked comparator as an adjusted threshold.

Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.

Abstract: A data receiver includes a plurality of amplifiers for receiving data in response to clock signals having a predetermined phase difference, and amplifying the received data by performing an equalization function based on feedback data, thereby outputting amplification signals, and a plurality of latches for latching output of the amplifiers, respectively. One amplifier receives the amplification signal, as feedback data, from another amplifier receiving a clock signal having a phase more advanced than a phase of a clock signal received in the one amplifier.

Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.

Abstract: A voltage generator includes a detector for outputting a driving signal according to comparison results of a reference voltage and a pumping voltage, an oscillator for generating an oscillation signal in response to the driving signal and varying a period of the oscillation signal according to a level of the pumping voltage, and a pump for pumping an external voltage in response to the oscillation signal to generate the pumping voltage. The voltage generator can quickly increase a pumping voltage up to the target level and improve the efficiency of the pumping voltage by minimizing the ripple components of the pumping voltage.

Abstract: A signal detecting device detects, as analog voltage signals, a current flowing through an exciting coil of an electric power generator, a source voltage and a temperature of a regulator that change as a current is fed to the exciting coil by an FET. These analog voltage signals are subjected to A/D conversion by a single A/D converter circuit. The detected current is subjected to A/D conversion in a period during which the FET is ON, while the detected source voltage and the detected temperature are subjected to A/D conversion in a period during which the FET is OFF.

Abstract: The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device, —and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device.

Abstract: Embodiments of the invention relate to a method and apparatus to drive non-resistive loads. The non-resistive load driver may include two or more drivers, such as a high-drive circuit and a low-drive circuit, to drive rail-to-rail output voltages and to stabilize the output voltages at a substantially constant level. The high-drive circuit may drive the output voltage of the non-resistive load driver to a threshold level, whereas the low-drive circuit may modify the output voltage of the non-resistive load driver to approximate an input voltage of the non-resistive load driver, and compensate any leakage associated with the non-resistive loads to provide a substantially constant output voltage. The low-drive circuit consumes less current than the high-drive circuit. The non-resistive load driver consumes less power and use less chip space.