Abstract: The object of the present disclosure is to suppress the conduction noise in a semiconductor device. A semiconductor device includes an inverter section being a full-bridge inverter, and a reflux section that short-circuits between output terminals U and V of the inverter section, in which impedances and are provided between each of freewheel diodes and of the upper arm and the output terminals U and V, and impedances and are provided between the freewheel diodes and of the lower arm and the input terminal N of in the inverter section, and the impedances to are greater than parasitic impedance of wiring assuming that IGBTs to and the output terminals U and V or the IGBTs and the input terminal N are connected only by the wiring.

Abstract: A system, method and apparatus for automatically adapting power grid usage by controlling internal and/or external power-related assets of one or more users in response to power regulation and/or frequency regulation functions in a manner beneficial to both the power grid itself and the users of the power grid.

Abstract: The power supply circuit which includes a first power circuit, a second power circuit, and a third power circuit is used for supplying power to loads. The first power circuit is connected between a control terminal of a control circuit and the load, and includes a switching unit including a first terminal, a second terminal, and a switching terminal controlling connection and disconnection between the first terminal and the second terminal The first terminal is connected to a power source, the second terminal is connected to the load, and the switching terminal is connected to the control terminal. The second power circuit and the third power circuit further includes a delay circuit relative to the first power circuit, the delay circuit is connected between the control terminal and the switching terminal, a delay time of the third power circuit is greater than the delay time of the second power circuit.

Abstract: A voltage sequence output circuit includes input terminals of a NOR gate connected to first and second input terminals. An output terminal of the NOR gate connected to a first terminal of a first electrical switch. A third terminal of the first electrical switch connected to a power source. A first terminal of a second electrical switch connected to the first input terminal and the power source through a first resistor. A second terminal of the second electrical switch connected to a second terminal of the first electrical switch. A third terminal of the second electrical switch connected to a first output terminal and a second terminal of a third electrical switch. A first terminal of the third electrical switch connected to a second input terminal and the power source through a second resistor. A third terminal of the third electrical switch connected to a second output terminal.

Abstract: A semiconductor device includes internal voltage generating circuits, a switching circuit, load circuits, a control circuit. Each of the plurality of load circuits is supplied with voltage through the switching circuit from any one of the plurality of internal voltage generating circuits. The control circuit defines connecting combinations by the switch circuit. The control circuit supplies a control signal to the switch circuit, based on the control signal corresponding to the definitions of the connecting combinations. The control circuit allows switching the connecting combinations when the semiconductor device tests in a test mode. The control circuit prohibits switching the connecting combinations in a non-test mode. The switch circuit connects between each of m of the internal voltage generating circuits and each of n of the load circuits through a connecting combination which is selected, based on the control signal, from mn of the connecting combinations.

Abstract: A drive circuit is provided for a semiconductor optical amplifier type gate switch includes a first transmission path and a second transmission path. The first transmission path includes a common first sub-path between a signal source and a first node; and an individual second sub-path for each of a plurality of operational amplifiers between the first node and a corresponding one of the operational amplifiers. The second transmission path includes an individual third sub-path between each of the operational amplifiers and a second node; and a common fourth sub-path between the second node and the semiconductor optical amplifier type gate switches. Transmission delay times of all the individual second sub-paths are equal, and transmission delay times of all the individual third sub-paths are equal.

Abstract: A multi-system module having a functional substrate includes a substrate comprising therein at least one control circuit units, and a plurality of main circuit units provided on one side surface of the substrate. The main circuit units are electrically connected to the control circuit unit, whereby the control circuit unit is used to manage the operation of the main circuit units. Via the above module structure, the substrate can improve the function of controlling multiple systems.

Abstract: A semiconductor circuit suitable for normally-on switching elements or switching elements low in threshold voltage. A negative power supply is charged by a high-voltage power supply. A high-voltage switch controls the advisability of applying a voltage to a high-voltage terminal. With deducing the power supply to power switching elements, the high-voltage switch is turned off, and even in the case where the voltage of the controlling circuits of the power switching elements is reduced, the power supply capacitors for the controlling circuits are charged by the high-voltage terminal thereby to operate the controlling circuits. Further, a negative power source voltage generating circuit utilizes the energy charged to the capacitors from output terminals. A voltage terminal is inserted between the high-voltage terminal and a reference voltage terminal. The negative power source voltage generating circuit is interposed between the voltage terminal and a plurality of the output terminals.

Abstract: A semiconductor device includes a plurality of circuits each independently conducting a predetermined process, and a circuit operation control part controlling operation start timings and operation suspend timings so as to mutually interfere with power voltage fluctuations caused by a state transition between an operation start and an operation suspend for each of the plurality of circuits.

Abstract: A semiconductor circuit suitable for normally-on switching elements or switching elements low in threshold voltage. A negative power supply is charged by a high-voltage power supply. A high-voltage switch controls the advisability of applying a voltage to a high-voltage terminal. With deducing the power supply to power switching elements, the high-voltage switch is turned off, and even in the case where the voltage of the controlling circuits of the power switching elements is reduced, the power supply capacitors for the controlling circuits are charged by the high-voltage terminal thereby to operate the controlling circuits. Further, a negative power source voltage generating circuit utilizes the energy charged to the capacitors from output terminals. A voltage terminal is inserted between the high-voltage terminal and a reference voltage terminal. The negative power source voltage generating circuit is interposed between the voltage terminal and a plurality of the output terminals.

Abstract: A system and method for generating multiple drive strengths for one or more output signals of a memory controller operable to control a memory subsystem. The system includes a state machine operable to generate an n-bit output representative of a drive strength operable to drive the one or more output signals; and a plurality of adders, each adder having a plurality of n-bit inputs, each input receiving a selective set of bits from the n-bit output of the state machine, the adders generating a plurality of n-bit outputs representative of drive strengths operable to drive the output signals. The method includes generating an n-bit output representative of a drive strength, and adding combinations of two or more selective sets of bits from the n-bit output to generate a plurality of n-bit outputs representative of a plurality of drive strengths that are operable to drive the output signal.

Abstract: A contactless data storage medium having a principal circuit component and a coupling element, with a controllable load provided for performing offloading modulation. A drawn-current controller is able to reduce the current drawn by the principal circuit component and simultaneously increase the size of the current through the load in order to provide an offloading potential for performing the offloading modulation.

Abstract: An architecture for distributing supply voltages to a plurality of memory modules supplied through a plurality of charge pump circuits may include a sorting block bi-directionally connected to the plurality of memory modules, from which it may receive a plurality of power requests. The sorting block may provide a sorting signal based upon a priority scale to drive the plurality of charge pump circuits and distribute supply voltages to the plurality of memory modules. The architecture may advantageously be software-configurable.

Abstract: A control arrangement and method is provided for electronic devices in which an electronic switch is maintained in a conducting state at all times other than when it is desired to render the electronic switch nonconducting. In a specific embodiment, a latched control signal is utilized which is changed by the receipt of a momentary signal to change the conducting state of the electronic switch. For example, according to one specific arrangement, the momentary signal is a secure, complex signal such that appropriate decoding and detection of the proper signal is required to change the conducting state of the electronic switch.

Abstract: A method for generating signals for input to a vital “AND” gate includes generating a plurality of independent signals for input to the “AND” gate and checking that each of the signals has a frequency and duty cycle within predetermined ranges. Upon a determination that one of the signals exhibits an inactive state or has a frequency or duty cycle outside the predetermined ranges, generation of another of the signals is stopped. This method eliminates a need for physical filters where the input signals are generated independently by computer subsystems.

Abstract: A ramp loading circuit for slowing current change in a circuit block. The circuit may include a plurality of load circuits placed in parallel with the circuit block and a control circuit. Each load circuit may provide a path for current flow when the load circuit is activated. Each load circuit may also be configured to allow a gradual decrease in current flow through the path when the load circuit is deactivated. The control circuit may be configured to deactivate each load circuit before the circuit block enters the sleep mode.

Abstract: A device for automatically varying resistance includes a comparator for comparing a control voltage to a reference voltage; a switch operatively coupled to the comparator; and a first resistor and second resistor operatively coupled in a series connection between a pull-up voltage and a signal line. The switch is operatively coupled in a parallel connection with the first resistor and, based on the comparison between the control voltage and the reference voltage, the switch selectively bypasses the first resistor. A method of automatically varying resistance includes comparing a control voltage and a reference voltage; pulling-up a signal line to a pull-up voltage through a first resistor and a second resistor operatively connected in series if the comparison has a first outcome; and pulling up the signal line to the pull-up voltage through only the second resistor if the comparison has a second outcome.

Abstract: An improved method and system for providing power to digital potentiometers is provided by applying the static electric field of an adjacent modified, non-volatile memory cell to the wiper mechanism. During periods of power removal to the circuitry as a whole, the potentiometer maintains the selected resistance via this static power supply.

Abstract: A computer circuit comprising a driver circuit and a variable loading circuit coupled to the driver circuit. The variable loading circuit is configured to provide a first capacitive load to the output driver while operating according to a first state, and a second capacitive load while operating according to a second state. According to one embodiment, the variable loading circuit includes a first programmable cell element. The variable loading circuit is configured to operate according to the first state in response to the first programmable cell element being programmed. The variable loading circuit is further configured to operate according to the second state in response to the first programmable cell element being erased and a voltage potential being supplied.

Abstract: A time domain multiplexer system with automatic determination of acceptable multiplexer output limits, error determination, or correction is comprised of a time domain multiplexer, a computer, a constant current source capable of at least three distinct current levels, and two series resistances employed for calibration and testing. A two point linear calibration curve defining acceptable multiplexer voltage limits may be defined by the computer by determining the voltage output of the multiplexer to very accurately known input signals developed from predetermined current levels across the series resistances. Drift in the multiplexer may be detected by the computer when the output voltage limits, expected during normal operation, are exceeded, or the relationship defined by the calibration curve is invalidated.

Abstract: Conventional integrable differential amplifiers have implanted resistors as load resistors, the limited size of which represents a barrier for the minimization of current consumption. In accordance with the present invention, the load resistors are replaced by load elements that represent non-linear two-terminal elements such as diodes, the potential at these load elements is held constant via a control loop by a controlling element such as a control transistor. This allows the current consumption of differential amplifier stages to be reduced to the order of magnitude of the residual current without increasing the area required for integration of the circuit.

Abstract: A multi-voltage circuit on a semiconductor chip including core circuitry driven by a power supply voltage equal to the voltage of a selected external device operating in connection with the semiconductor chip, and having input/output circuitry in selected regions for operating in connection with external devices having the same operating voltage and other external devices having a selected substantially lower operating voltage. Peripheral input/output circuit regions of at least first and second kinds are established for interfacing with the respective high and low voltage external devices. According to one version of the invention, the input/output circuitry directed toward interfacing with external devices operating at a particular voltage level is concentrated at a particular peripheral region in the periphery of the semiconductor chip. According to another version of the invention, multiple regions of input/output circuitry are established for external devices at the same voltage level.