Abstract: A voltage detector has a diode ladder with one or more diodes connected in series between a battery voltage input and an upper measuring node. A measuring diode is connected between the upper measuring node and a lower measuring node. A resistor and a power-down switch are connected in series between the lower measuring node and a ground. An analog input to an Analog-to-Digital Converter (ADC) is connected by a switch to the upper measuring node to generate an upper digital value. Then the switch connects the analog input to the lower measuring node to generate a lower digital value. The difference between the upper and lower digital values is the diode voltage drop across the measuring diode and is multiplied by a number of diodes in the diode ladder and added to the upper digital value to generate a battery voltage measurement.

Abstract: A method of performing coarse calibration of a voltage-mode (VM) driver having a plurality of driver slices connected in parallel includes setting a control code applied to activated driver slices of the plurality of driver slices to a maximum value to minimize an output resistance of the activated driver slices, activating one driver slice of the plurality of driver slices by applying the control code to the one driver slice, while disabling other driver slices of the plurality of driver slices, measuring an output resistance of the VM driver, determining whether the output resistance of the VM driver is greater than a desired resistance, and in response to determining that the output resistance of the VM driver is greater than a desired resistance activating one more driver slice of the plurality of driver slices.

Abstract: In a transfer type ink jet recording method, the temperature of an intermediate image in a heating step is not lower than the minimum coat forming temperature of a first resin and is not lower than the glass transition temperature of a second resin, and the temperature of the intermediate image in a transfer step is lower than the glass transition temperature of the first resin and is not lower than the glass transition temperature of the second resin.

Abstract: A dummy circuit and a driving circuit of a flat panel display device is provided in the present application, including: a plurality of dummy scanning lines extending in a row direction and separated from each other; a plurality of data lines extending in a column direction and separated from each other, the plurality of data lines including an outer dummy data line in the outermost side; the dummy scanning lines intersecting with the dummy data lines to form a plurality of dummy pixel regions, dummy pixel electrodes provided in the dummy pixel regions; a plurality of thin film transistors connecting the pixel electrode to the corresponding dummy scanning lines and the dummy data lines; and wherein the outer dummy data line corresponding to at least one end portion of the of the dummy scanning line outwardly avoidance disposed to make the projections of the both staggered.

Abstract: The present description relates to a semiconductor device including an array of two or more switching elements and a controller electrically connected to the array of switching elements. At least one switching element of the array of switching elements has a different electrical resistance than at least another switching element of the array of switching elements. The controller is configured to generate and transmit at least one coarse tuning signal and at least one fine tuning signal. The array of switching elements is configured to alter an electrical resistance of the array of switching elements in response to the at least one coarse tuning signal and the at least one fine tuning signal. The present description also includes a method of making a semiconductor device and a method of using a semiconductor device.

Abstract: A current source and an associated method for supplying current to a load such as an arrangement of LEDs. The intensity of the supplied current varies as a function of the temperature of the load. The intensity of the current is temperature-dependent and limited to a predefined maximum. The temperature dependence is achieved by the component parts that are used without the help of special temperature sensors. The current source is supplied with a reference voltage derived from an integrated circuit. The reference voltage is tapped from a port of the IC and therefore it is switchable. The reference voltage is used to produce a control current, which is fed through a driver stage to produce the current of the current source. Elements in the current source limit the current's intensity and change it as a function of temperature.

Abstract: A control circuit, which controls a transistor including a gate and a field plate, includes: a detecting circuit which detects a driving timing to drive the transistor; a timing controlling circuit which controls a first driving timing to drive the gate and a second driving timing to drive the field plate, in response to the driving timing; and a driving circuit which drives the gate in response to the first driving timing, and drives the field plate in response to the second driving timing.

Abstract: An apparatus and method for automatic control of current electrodes in a measuring system for an electrical resistivity survey. An exemplary apparatus includes: a circuit where one pair of metal oxide semiconductor field effect transistors (MOSFETs) are connected to upper and lower terminals of n current electrodes and the one pair of MOSFETs are connected in parallel with each other; and a controller which controls ON/OFF of each MOSFET. With this, the present invention provides a stable and semipermanent apparatus for automatic control of current electrodes, which is capable of bipolar high-speed switching, and a method thereof.

Abstract: Semiconductor relays switch power supplied from a power source to drive loads, and further detect current values of electric currents flowing through the loads. A control section intermittently turns ON the semiconductor relays via driving circuits, thereby limiting electric power consumption of the loads. Further, the control section calculates, based on the current values detected by the semiconductor relays, load electric power consumption of the loads, and estimated electric power consumption of the loads when the semiconductor relays are continuously ON, and allows a display section to display, as a value indicative of an energy-saving effect, an electric power amount difference i.e. a saved electric energy that is based on an electric power difference obtained by subtracting the load electric power consumption from the estimated electric power consumption.

Abstract: An apparatus is provided. The apparatus comprises a digital signal generator, an analog filter, an amplitude modulator, and an analog-to-digital converter (ADC). The digital signal generator has a demodulator and provides a digital excitation signal. The analog filter is coupled to the digital signal generator. The amplitude modulator has a variable capacitor and is coupled to the analog filter. The amplitude modulator also generates an amplitude modulated signal with an amplitude that is a function of the capacitance of the variable capacitor. The ADC is coupled to the amplitude modulator and the demodulator, and the digital signal generator and the demodulator operate synchronously.

Abstract: A current balancing device for parallel batteries is electrically connected with a load. The current balancing device includes a buck module, a normal module, a current comparing module and a control module. The buck module is electrically connected with a high voltage battery and outputs a first current to the load. The normal module is electrically connected with a low voltage battery and outputs a second current to the load. The current comparing module is electrically connected with the buck module and the normal module, and compares the first current with the second current to output a first comparing signal. The control module is electrically connected with the buck module and the current comparing module, and outputs a control signal to the buck module in accordance with the first comparing signal for adjusting the first current.

Abstract: A current-controlled resistor comprises a first input terminal configured to receive an input signal and a second input terminal configured to receive a current control signal. The resistor comprises a first stage configured to receive the current control signal; the first stage includes first and second PN diodes having first terminals of a first type and second terminals of a second type. The first terminals of the first and second PN diodes are coupled each other and a second terminal of the first PN diode is coupled to the first input terminal. The resistor comprises a second stage configured to receive the current control signal; the second stage includes a third PN diode having first and second terminals of the first and second types, the second terminal of the third PN diode being coupled to the second terminal of the second PN diode.

Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may comprise a first circuit, a second circuit, a transmission line coupled between the first circuit and the second circuit, and a Q-enhancement cell coupled to the transmission line.

Abstract: It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

Abstract: The invention provides a semiconductor device with high yield by reducing an effect of variations in characteristics of a semiconductor element. Further, by reducing an effect of variations in characteristics of a semiconductor element to improve productivity, an inexpensive semiconductor device can be provided. Further, an inexpensive semiconductor device can be provided by forming a semiconductor device in a large amount over a large substrate such as a glass substrate and a flexible substrate. A semiconductor device of the invention includes a demodulation signal generating circuit and an antenna or a wire for connecting the antenna. The demodulation signal generating circuit includes a demodulation circuit and a correction circuit. The correction circuit corrects a first demodulation signal generated from the demodulation circuit and generates a second demodulation signal.

Abstract: A system for efficiently boosting drive capability for high-voltage linear power amplification to supply transducers in a print head is provided. A linear power amplifier to drive the transducers in the print head includes a charge pump capacitor to boost the output voltage of the amplifier above the supply rail voltage. The amplifier can provide both positive and negative output pulses to drive the transducers. A distribution switch is used to distribute the output pulses among multiple transducers and a biasing circuit provides proper sequencing and timing signals to generate smooth output pulses. A method for driving a plurality of transducers in a print head using a charge pump capacitor is also provided.

Abstract: The present invention relates to verification of a transmission margin of various transmission lines transmitting a signal such as a high-speed digital signal and ensures improved verification accuracy. A transmission margin verification apparatus according to the present invention is configured with a measurement unit (e.g., LSI tester 4, network analyzer 6, pulse generator 8, oscilloscope 10) operable to measure a transmission loss and a leading edge waveform of pseudo transmission lines (e.g., transmission lines 56, 62, 66) corresponding to a target device 44 to be verified, and a calculation unit (tester controller 12) operable to reference the transmission line loss and the leading edge waveform measured by the measurement unit, calculate a transmission waveform of the target device, and associate the transmission waveform with a mask of the target device to calculate a transmission margin of the target device.

Abstract: A drive circuit is provided for a semiconductor optical amplifier type gate switch includes a first transmission path and a second transmission path. The first transmission path includes a common first sub-path between a signal source and a first node; and an individual second sub-path for each of a plurality of operational amplifiers between the first node and a corresponding one of the operational amplifiers. The second transmission path includes an individual third sub-path between each of the operational amplifiers and a second node; and a common fourth sub-path between the second node and the semiconductor optical amplifier type gate switches. Transmission delay times of all the individual second sub-paths are equal, and transmission delay times of all the individual third sub-paths are equal.

Abstract: To include two counter circuits that change impedances of two replica circuits, respectively, and an impedance adjustment control circuit that controls the counter circuits to update count values of the counter circuits. The impedance adjustment control circuit controls one of the counter circuits to finish updating the count value of the counter circuit in response to a change of the impedance of the corresponding replica circuit from a state of being lower than an impedance of an external resistor to a state of being higher than the impedance of the external resistor, and controls the other counter circuit to finish updating the count value of the other counter circuit in response to a change of the impedance of the other replica circuit from a state of being higher than the impedance of the former replica circuit to a state of being lower than the impedance of the former replica circuit. With this configuration, the adjust errors generated in the replica circuits are canceled.

Abstract: A sequence circuit includes a switch circuit (30) and a control circuit (50). The switch circuit has an input terminal connected with a node (11) and an output terminal connected to a super I/O chip (10). The control circuit includes a first transistor (Q4) and a second transistor (Q5), the first transistor has a gate connected to the node and a drain connected to a sleep control signal terminal (S3?), the second transistor has a base connected to the drain of the first transistor and a collector connected to the super I/O chip. When the computer is off or in one of the sleep states, the node is at low level and the output terminal of the switch circuit outputs a low level signal; when the computer is on, the node is at high level and the output terminal outputs a high level signal.

Abstract: In accordance with one aspect of the present invention to achieve the object, there is provided a switching mode power supply for reducing standby power including an EMI(Electro-Magnetic Interference) filter unit for removing a high frequency noise component by being connected to an input power source; a PFC(Power Factor Correction) unit connected to the EMI filter unit; a DC/DC unit connected to the PFC unit; a synchronous rectifier unit connected to the DC/DC unit; a PFC controller connected to the PFC unit and provided with an overvoltage protection stage; a DC/DC controller which is connected to the DC/DC unit and generates a burst mode operation signal; a synchronous rectifier controller for controlling the synchronous rectifier unit by being connected to the synchronous rectifier unit; an error signal generation unit for sensing an output voltage to generate an error signal and then transmitting the error signal to the DC/DC controller; a control unit for synchronizing the DC/DC unit and the PFC unit so

Abstract: In a multi-stage amplifier, a power supply circuit and a multiplier perform control so that, when there are manufacturing variations in, for example, inter-stage capacitance, a collector voltage of a stage immediately preceding a final stage is smaller than a collector voltage of the final stage, thereby suppressing variations in AM-PM characteristics.

Abstract: An electrical timer system is provided that has a unique voltage converter that automatically converts various supply voltage values to the required operating voltage for a timing device without jumpers or special configuration at installation.

Abstract: An apparatus is provided. The apparatus comprises a digital signal generator, an analog filter, an amplitude modulator, and an analog-to-digital converter (ADC). The digital signal generator has a demodulator and provides a digital excitation signal. The analog filter is coupled to the digital signal generator. The amplitude modulator has a variable capacitor and is coupled to the analog filter. The amplitude modulator also generates an amplitude modulated signal with an amplitude that is a function of the capacitance of the variable capacitor. The ADC is coupled to the amplitude modulator and the demodulator, and the digital signal generator and the demodulator operate synchronously.

Abstract: A control device contains a plurality of controllers, a common signal output, and a change-over unit. The controllers are coupled on an output side to the common signal output through the change-over unit. A plurality of differentiating elements are disposed upstream of the change-over unit and in each case connected with one of the controllers. An integrating element follows the change-over unit. An output of a controller is first differentiated, sent through the change-over unit, and then integrated.

Abstract: An input processing circuit implemented on a semiconductor integrated circuit includes an input terminal for receiving an input signal, a first diode coupled between the input terminal and a power line, a second diode coupled between the input terminal and a ground line, a first MOSFET having a gate and drain coupled together to the input terminal, and a source coupled to the ground line, a second MOSFET coupled to the first MOSFET to construct a current mirror circuit, a current-to-voltage conversion circuit coupled between the power line and the second MOSFET to convert an electric current flowing through the second MOSFET to a voltage, and a determination circuit configured to determine a state of the input signal based on a level of the output voltage of the current-to-voltage conversion circuit.

Abstract: A power integrated circuit includes, in part, a multitude of controllers, a multitude of pulse-width generators, a multitude of output stages and a configuration matrix. Each controller is adapted to be responsive to a feedback signal and a reference signal to generate a control signal carrying pulse width information. Each control signal causes a difference between an associated output voltage feedback signal and the reference signal to be less than a predefined value. Each pulse-width generator is associated with and responsive to a different one of the controllers to generate a pulse-width modulated signal in response. The configuration matrix selectively couples the plurality of pulse-width generators to the output stages.

Abstract: An integrated circuit device for delivering power to a load includes a P-MOS power transistor, an N-MOS bypass transistor and a gate driver circuit. The P-MOS power transistor is coupled between a supply voltage node and a power output node of the integrated circuit device, and the N-MOS bypass transistor is coupled between the power output node and a reference node of the integrated circuit device. The gate driver circuit responds to a pulse-width-modulated (PWM) control signal by outputting an active-low drive-enable signal to a gate terminal of the P-MOS power transistor and an active-high bypass-enable signal to a gate terminal of the N-MOS bypass transistor during respective, non-overlapping intervals.

Abstract: This invention provides an electronic control unit is capable of suppressing electromagnetic noise having a frequency band used in a portable wireless apparatus, and capable of exhibiting a noise resistance property against electromagnetic noise. The electronic control unit including a constant voltage power supply circuit portion, an analog signal inputting circuit portion, and a conversion processing circuit portion, an analog sensor and a driving power supply being connected to the outside, and the unit being connected to the analog sensor through a power supply line and a signal line, in which the analog signal inputting circuit portion includes a current limiting circuit portion, an integrating circuit portion, a current limiting resistor, a signal noise absorbing circuit, and a first bypass capacitor, and capacitance (C1) and parasitic inductance (L1) of the first bypass capacitor are set in a range of 7×106<1/[2??(L1×C1)]<35×106.

Abstract: A method for detecting a null current condition in a PWM driven inductor connected between a voltage source node and a second circuit node of a line for outputting current to a load includes generating a derivative signal by time differentiating a voltage on the second node. The method further includes monitoring an instant when the derivative signal becomes negative, and signaling verification of the null current condition each time the derivative signal becomes negative.

Abstract: A data processing apparatus and method of configuration of such an apparatus are provided, the apparatus comprising a plurality of logic elements for processing data, a plurality of storage elements for temporarily storing data, and a plurality of connections from which data is passed between the logic elements. Each connection comprises one or more path portions separated by the storage elements. A number of the storage elements are selectable storage elements having a bypass path associated therewith, and a controller is provided for controlling the selection of each selectable storage element or its associated bypass path based on setup information, in order to enable a change in the number of path portions within one or more of the connections.

Abstract: A driver (300) which meets wide common mode voltage requirements is provided. Output passgates (310) protect sensitive line driver circuitry (305) from extreme bus voltages; enabling/disabling circuits (315, 316) detect fault conditions to ensure the line driver is disabled when needed, and pull-ups (320) assist in line driver start up by preventing negative voltage conditions on the bus driven by the line driver.

Abstract: Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a bandgap circuit with a low power consumption, said second circuit block including a bandgap circuit with a short start up time, said control circuit suitable to control said two circuit blocks in a such way that said output voltage of said bandgap voltage reference circuit is supplied by said second circuit block at the starting of said first circuit block for a period of time and said output voltage is supplied by said first circuit block for the period of time subsequent to said period of time and that lasts until the turning off of the circuit, said second circuit block being turned off after said period of time.

Abstract: A control arrangement and method is provided for electronic devices in which an electronic switch is maintained in a conducting state at all times other than when it is desired to render the electronic switch nonconducting. In a specific embodiment, a latched control signal is utilized which is changed by the receipt of a momentary signal to change the conducting state of the electronic switch. For example, according to one specific arrangement, the momentary signal is a secure, complex signal such that appropriate decoding and detection of the proper signal is required to change the conducting state of the electronic switch.

Abstract: A method for designing a semiconductor integrated circuit while minimizing any increase in the area of its logic circuit under test. Circuit data about the semiconductor integrated circuit are received, and transition signal occurrence probabilities of all scanning function-equipped storage elements involved are computed by use of the circuit data. In keeping with the transition signal occurrence probabilities thus computed and based on predetermined parameters, the method permits selection of scanning function-equipped storage elements that may be replaced by delay test-ready scanning function-equipped storage elements.

Abstract: A system and method for maintaining desired circuit component attributes is shown. According to a preferred embodiment, a high frequency circuit component, such as a MMIC, is retained in a circuit using a degradeable material, such as silver filled epoxy, wherein a portion of the degradeable material remains exposed. A protective coating of resin is applied to the exposed portion of the degradeable material by preferably depositing a predetermined amount of protective material, such as an epoxy resin, a void near the exposed portion of the degradeable material. The protective material preferably migrates to fully cover the exposed portion of the degradeable material without covering the circuit component. Accordingly, the circuit component is protected from substantial changes in operation characteristics due to the protective material and likewise is protected from changes in operation characteristics due to degradation of the degradeable material resulting from exposure.

Abstract: A method for generating signals for input to a vital “AND” gate includes generating a plurality of independent signals for input to the “AND” gate and checking that each of the signals has a frequency and duty cycle within predetermined ranges. Upon a determination that one of the signals exhibits an inactive state or has a frequency or duty cycle outside the predetermined ranges, generation of another of the signals is stopped. This method eliminates a need for physical filters where the input signals are generated independently by computer subsystems.

Abstract: A gm-C filter system having low power consumption is provided. An adjusting circuit 2 is equipped with an oscillator 3 constructed of a gm amplifier 3a having the same arrangement as that of a gm amplifier 1a of a gm-C filter circuit 1. The adjusting circuit 2 generates a digital adjusting value “Dgm” based upon an oscillation signal OSC outputted from this oscillation 3, and this digital adjusting value “Dgm” is used to adjust a gm value of the gm amplifier 3a of the oscillator 3. This digital adjusting value “Dgm” is held in a register 10. The digital adjusting value “Dgm” held in this register 10 is converted into an analog adjusting value (bias current) by a D/A converter 8, and then, this analog adjusting value is supplied to the gm amplifier 1a of the gm-C filter circuit 1 so as to adjust the gm value. The adjusting circuit 2 is operated in an intermittent manner based upon, for example, a change contained in ambient temperatures of the gm-C filter system.

Abstract: A method for the control of an electronic circuit of the type includes at least one access pin to receive and/or deliver control signals, includes the generation, in a control unit, of control signals from data elements received serially through a data transfer input/output device. The method also includes the following steps: (1) extracting a control word included in the data received serially; and (2) decoding the control word extracted in the previous step in order to perform an operation, as a function of the value of the control word, thus modifying the logic state of at least one control signal.

Abstract: The present invention relates to an output buffer circuit for transmitting digital signals over a transmission line with pre-emphase. It comprises an output stage and a control circuit. The output stage includes a first impedance circuit connected between an upper power supply potential and an output node. It furthermore includes a second impedance circuit connected between the output node and a power supply node at a lower supply potential. Both impedance circuits receive impedance control signals from the control circuit such that an impedance ratio between the first impedance and the second impedance takes one of at least three different predetermined values in accordance with the present state and the history of a digital data input signal, and such that the sum of the conductance provided by the first impedance circuit and the conductance provided by the second impedance circuit is independent from the generated impedance ratios.

Abstract: The constitution includes a heater 2 used as current receiving element, a thyristor 3 placed in the current travelling route of the heater 2, a series connection circuit of a capacitor 4 and diode 5 for control power source connected parallel to the thyristor 3, a Zener diode 9 as a constant voltage element connected to the gate of the thyristor 3, and a control circuit 6 connected parallel to the capacitor 4, with its control terminal connected to the gate of the thyristor 3, whereby a specified control voltage determined by the Zener voltage of the Zener diode 9 is obtained at the first capacitor 4 by the control of the thyristor 3, so that the transformer for stepping down the supply voltage is not necessary.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determines the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programming voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: A compensation circuit adapted to receive an input signal for a circuit element to be compensated. The input signal is used as an address to a memory at which a compensated signal is stored. The stored compensated signal is output to the circuit element as the compensated signal therefor. In a specific implementation, the command input is received by a shift register. The shift register converts a serial input to a parallel output. The parallel output of the shift register is combined with the output of a temperature sensor to provide an address for the memory. The command input data includes an address to the particular circuit element to be compensated. The temperature data is used to select a particular page of memory and the remainder of the command input data is used to select data from that page for output as the compensated signal for the selected element. In the illustrative embodiment, the components compensated are automatic gain control amplifiers.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determines the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programming voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determine the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programing voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: In a range finder, a capacitor for light emission is charged by turning off first and second switching elements and turning on third and fourth switching elements before light is emitted from a light emitting diode. A sum of a charging voltage of the capacitor for light emission and the voltage of a direct current power source is applied to the light emitting diode by turning on the first and second switching elements and turning off the third and fourth switching elements when light is emitted from the light emitting diode. At this time, an operation of the second switching element is controlled with a constant electric current by a constant current control circuit constructed by a transistor, a resistor for current limitation, a diode, etc. so that an electric current flowing through the light emitting diode is constant and a light emitting amount of the light emitting diode becomes constant.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determine the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programming voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: Conventional integrable differential amplifiers have implanted resistors as load resistors, the limited size of which represents a barrier for the minimization of current consumption. In accordance with the present invention, the load resistors are replaced by load elements that represent non-linear two-terminal elements such as diodes, the potential at these load elements is held constant via a control loop by a controlling element such as a control transistor. This allows the current consumption of differential amplifier stages to be reduced to the order of magnitude of the residual current without increasing the area required for integration of the circuit.