Abstract: A clock frequency supply device includes: a frequency tuner configured to receive an input signal with a carrier frequency, and tune an oscillation frequency of an oscillator based on the carrier frequency; an injector configured to inject the input signal directly into the oscillator after the tuning of the oscillation frequency is completed; and an oscillator configured to generate a reference clock signal with a reference clock frequency based on the injected input signal.

Abstract: A wireless communication system is disclosed. The system performs data transmission from a first terminal including N antennas to a second terminal including M antennas using spatially multiplexed streams (N and M are integers larger than or equal to 2).

Abstract: The invention discloses a communication method using dual-level and binary digital baseband symbols which represents information by durations of a high level and a low level instead of by a high level and a low level in conventional digital baseband symbol design. In the invention, waveforms of a symbol 0 and a symbol 1 are determined according to durations of a high level and a low level, a transmitter generates a corresponding digital baseband signal in terms of a binary data to be transmitted according to the defined waveforms, and a receiver determines a symbol 0 or a symbol 1 according to waveform of a received digital baseband signal. The invention realizes bit synchronization of a receiver and a transmitter without extracting a bit synchronization clock from a received signal by the receiver, and a bit rate thereof is higher than that of Manchester under a same signal bandwidth.

Abstract: A transceiver 1 includes a frequency synthesizer 2 configured to generate an output signal 3 for use as a carrier signal for transmission and/or a signal with a channel frequency for reception, wherein the frequency synthesizer is a sub-sampling based frequency locked loop frequency synthesizer. The combination of a FLL and sub-sampling allows to obtain a sub-sample based locked loop with a closed loop response similar to a PLL but with improved settling time and improved suppression of high frequency components of the quantization noise due to the sampling process. The transceiver allows to obtain a frequency synthesizer with improved characteristics with respect to at least one of power consumption, locking characteristic, design optimization characteristics compared to non-sub-sampling PLL based frequency synthesizers.

Abstract: A passive electro-optical tracker uses a two-band IR intensity ratio to discriminate high-speed projectiles and obtain a speed estimate from their temperature, as well as determining the trajectory back to the source of fire. In an omnidirectional system a hemispheric imager with an MWIR spectrum splitter forms two CCD images of the environment. Three methods are given to determine the azimuth and range of a projectile, one for clear atmospheric conditions and two for nonhomogeneous atmospheric conditions. The first approach uses the relative intensity of the image of the projectile on the pixels of a CCD camera to determine the azimuthal angle of trajectory with respect to the ground, and its range. The second calculates this angle using a different algorithm. The third uses a least squares optimization over multiple frames based on a triangle representation of the smeared image to yield a real-time trajectory estimate.

Abstract: A binarization circuit includes a comparator that outputs a signal according to a differential voltage between the input and reference voltages. The first charging-discharging circuit generates a first voltage. The second charging-discharging circuit generates a second voltage. The control circuit compares the differential voltage with the threshold voltage, and switches between turn-on and turn-off of the second charging-discharging circuit based on a difference between the differential voltage and the threshold voltage. A sum of the reference and first voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned off. A sum of the reference and the first and second voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned on.

Abstract: An architecture for processing signal communications between a frequency translation module and an integrated receiver decoder. According to an exemplary embodiment, the signal processing apparatus comprises a demodulator for generating a first signal responsive to an FSK signal, said first signal comprising a varying amplitude and a clamping means for generating a second signal, wherein said second signal has a first value when the amplitude of the first signal is above a predetermined value, and wherein said second signal has a second value when the amplitude is below a second predetermined value.

Abstract: An architecture for processing signal communications between a frequency translation module and an integrated receiver decoder. According to an exemplary embodiment, the signal processing apparatus comprises a demodulator for generating a first signal responsive to an FSK signal, said first signal comprising a varying amplitude and a clamping means for generating a second signal, wherein said second signal has a first value when the amplitude of the first signal is above a predetermined value, and wherein said second signal has a second value when the amplitude is below a second predetermined value.

Abstract: Structures and techniques for implementing multiple-antenna configurations within a radio frequency receiver are provided. In one aspect, a modularized multi-antenna receiver is provided having multiple independent microelectronic dice mounted on a common module substrate. In another aspect, a multi-antenna receiver is provided that utilizes at least one single ended low noise amplifier and at least one differential low noise amplifier within a common receiver.

Abstract: A BFSK demodulator comprises a three-channel frequency-to-voltage converter, an information signal inputting the first-channel frequency-to-voltage converter, a converted information signal inputting the second-channel frequency-to-voltage converter, wherein outputs of first and second channel frequency-to-voltage converter are connected with a capacitor, a output voltage signal produced by the first and second frequency-to-voltage converters and the capacitor, inputting into a positive terminal of the comparator after high frequency noise filtering through a first low-pass filter, a carrier signal inputs into the third-channel frequency-to-voltage converter; and an output from the third-channel frequency-to-voltage converter connected to a capacitor; and a reference voltage signal is produced after high frequency noise filtering through a second low-pass filter, producing a demodulated signal after comparing the information voltage signal with the reference voltage.

Abstract: A FSK signal demodulating integration-discharge circuit has a simple circuit configuration and utilizes an AC waveform of the FSK signal as a. control signal for a transistor gate. FSK signals are converted into rectangular-wave signals by the use of a limiter, before adding the rectangular-wave signal to an integrating capacitor C1 through a resistor. The capacitor C1 connects to a first transistor in parallel thereto, which is turned ON/OFF due to the rectangular-wave signal. The signal causes the capacitor C1 to be charged by the voltage corresponding to time length of a half cycle of a portion of positive voltage of the rectangular-wave signal, while causing the above capacitor C1 to discharge in terms of electric charge of the capacitor C1 by the voltage corresponding to time length of a half cycle of a portion of negative voltage of the rectangular-wave signal. Charged voltage from the capacitor C1 also feeds into a holding capacitor C2 through a second transistor.

Abstract: A demodulator circuit (10) includes an oscillator (12) and an injection circuit (14). An Automatic Frequency Control (AFC) signal adjusts the tail current of a current source (28) provided in the oscillator (12) and the tail current of a current source (44) provided in the injection circuit (14). A phase detector (16) compares the phase of the signal generated by the oscillator (12) with the phase of the injected input signal. The phase detector (16) generates an output signal V0 having a value of zero when the input signal is in quadrature with the signal generated by the oscillator (12), but generates a non-zero signal that is used to adjust the AFC signal when the input signal and the signal generated by the oscillator (12) are not in quadrature.

Abstract: A FSK signal demodulating integration-discharge circuit is realized with simple circuit configuration in such a way as to utilize AC waveform itself of the FSK signal as a control signal of a transistor gate. Conversion is made to execute in terms of FSK signals into rectangular-wave signals by the use of a limiter LIM, before adding the rectangular-wave signal to an integrating capacitor C1 through a resistor. Since the capacitor C1 is connected to a first transistor in parallel thereto and being turned ON/OFF due to the rectangular-wave signal, it causes the above capacitor C1 to be charged by the voltage corresponding to time length of half cycle of a portion of positive voltage of the rectangular-wave signal, while it causes the above capacitor C1 to discharge in terms of charged electric charge of the capacitor C1 by the voltage corresponding to time length of half cycle of a portion of negative voltage of the rectangular-wave signal.

Abstract: A frequency demodulator of the present invention includes: an amplification section for receiving a frequency-modulated signal and amplifying the frequency-modulated signal based on a gain so as to produce a digital signal having a predetermined level and an inverted signal of the digital signal; a digital demodulation section for receiving the digital signal and frequency-demodulating the digital signal; an amplitude detection section for receiving the digital signal and the inverted signal of the digital signal, and detecting maximum amplitude values of the digital signal and the inverted signal for a predetermined period of time so as to produce an amplitude signal in proportion to the maximum values; and a gain controlling section for varying the gain based on the amplitude signal.

Abstract: A demodulation circuit providing for detection of multiple zero-crossings in an FSK signal. High data rate signals are demodulated by generating, for each pair of baseband signals I and Q, additional I and Q pairs which are phase shifted from the original I and Q pair. By generating zero crossing signals for the original baseband signals and for the phase shifted signals, additional zero crossings may be detected allowing demodulation of relatively high data rate modulated signals.

Abstract: A circuit is provided by which in the case of the transmission of a short packet signal through an FSK transmission channel having a frequency error for transmission and reception, directly from one shaped rectangular pulse of a frequency detected bit synchronization signal having a DC offset (this pulse including a bias distortion as it is) a clock signal can be generated indicating the points of time when the base-band signal passes through its center level and the point of time when it arrives its maximum or minimum value (data sampling points of time). This invention utilizes the fact that the bit synchronization signal is in the form of a sine wave because it has been band limited.

Abstract: An apparatus detects living bodies, in particular human living bodies, by ectromagnetic signals. The apparatus has a receiver device for electromagnetic signals that includes a device for obtaining frequency components that are characteristic in respect to living bodies, out of the magnetic signals. The receiver device includes a direct demodulator.

Abstract: A cancellation circuit is provided where one demodulator circuit provides a demodulated output having interference voltage owing to interference between carrier signals, between a carrier signal and noise, or a combination of both. Cancellation of interference is particularly directed to narrowband applications. Because the interference is within the band of the desired signal, it cannot be filtered without materially harming the quality of the message. A separation circuit is provided for removing the interference voltage component from the message signal. Outputs are provided to a second demodulator for creating a phase-shifted near replica signal of the dominant carrier signal without an interference voltage component. The separation circuit includes an isolation circuit. Further described are applications of the cancellation circuit, including demultiplexing a power-multiplexed signal, demodulation of two or more carrier signals, and removal of interference from modulated and unmodulated carrier signals.

Abstract: A demodulator for demodulating a binary frequency-modulated signal includes a demodulator with a quadrature tank circuit and a duty cycle monitor circuit. The quadrature tank circuit has a voltage-controllable resonant frequency for compensating for shifts in the carrier frequency of the incoming signal and shifts in the tank circuit component values so as to allow the use of a high-Q tank circuit and thereby maximize use of the incoming signal energy. The quadrature tank circuit is a reactive circuit (with both inductive and capacitive elements) which includes a varactor diode having a voltage-controllable capacitance. The duty cycle monitor circuit measures the duty cycle of the demodulated binary output from the demodulator, and provides a control voltage to the quadrature tank circuit for adjusting its center frequency of operation.

Abstract: An FSK demodulator is provided comprising means for receiving and digitizing an FSK signal (such as a signal comprising two frequencies f1 and f2 in which first and second logic states are represented by first and second periods of different durations). First, second, third and fourth consecutive transitions of the signal are identified and the times of said transitions are identified. A first period between the first and third transitions is calculated, as is a second period between the second and fourth transitions. A change of frequency in the signal is indicated when the first and second periods lie on opposite sides of a first threshold period (.tau.) and no change of frequency is indicated when the first and second periods lie on the same side of the threshold period (.tau.). In a further aspect of the invention, a transition is rejected as illegal when two consecutive transitions occur within a predetermined period of time.