Abstract: An example apparatus includes: an input adapted to receive a signal modulated with data, counter circuitry coupled to the input and operable to determine a first count value in response to a first period between a first rising edge of the signal and a second rising edge of the signal, the first rising edge indicative of a start bit of the data, and determine a second count value based on a second period between a first falling edge of the signal and a second falling edge of the signal, data capture clock circuitry coupled to the counter circuitry and operable to generate a data capture clock based on the first count value in response to the second count value satisfying a threshold, and demodulator circuitry coupled to the counter circuitry and the data capture clock circuitry, the demodulator circuitry operable to generate a demodulated signal based on the data capture clock.

Abstract: A demodulation system for demodulating an input signal is provided. The input signal includes a carrier wave modulated with data symbols selected from a plurality of candidate complex symbol values. The system includes a carrier recovery module, operative to compensate for a carrier frequency of the carrier wave and output a demodulated data signal. The carrier recovery module includes: a first complex-signal conversion module, operative to convert the input signal into a complex-valued input signal; a voltage-controlled oscillator; a mixer, for mixing the complex-valued input signal and a complex-valued output signal of the voltage-controlled oscillator, and generating a mixer output signal; a low-pass filter, coupled to the mixer, operative to filter the carrier frequency from the mixer output signal, and output a signal corresponding to the demodulated data signal; and a folding module, operative to apply a folding algorithm to the output signal of the low-pass filter.

Abstract: A multiuser communication system comprises multiple transmitters and a multiuser receiver that detects multiple transmissions via iterative soft interference cancellation. An initial acquisition module and single user decoder module are also described. The multiuser receiver acquires and subtracts known users in the residual signal before acquiring new users in the residual signal, which is performed iteratively until no new users are detected or a stopping criterion is met. To aid receiver acquisition, the transmitters insert discrete tones into the transmitted signals. These allow the multiuser receiver to obtain initial estimates of the frequency, time, gain, and/or phase offset for each user. To improve the quality of cancellation the receiver refines estimates of gain, time, frequency and phase offsets for each user after each iteration, and calculates time varying SINR estimates for each user. The multiuser receiver may be satellite based, may be a distributed receiver, or process users in parallel.

Abstract: The present invention provides a control method and apparatus for an electric tool, and further provides an electronic tool, which relates to the field of automatic control of electric tools. The method comprises: Obtaining parameters characterizing an output shaft load during a running process of an electric tool; calculating the average values of the parameters characterizing an output shaft load according to a composite average algorithm, wherein the composite average algorithm comprises a combination of at least two average algorithms; calculating slope values of the parameters characterizing the output shaft load according to the average values of the parameters characterizing the output shaft load; and interrupting torque output of the electric tool according to the slope values of the parameters characterizing the output shaft load.

Abstract: Exemplary aspects are directed to FM-radio receivers and methods to assess signals in a desired channel. In one example, a method includes demodulating a broadcast signal associated with a radio-frequency transmission using a desired-channel bandwidth setting and, in response, provide a first frequency-selective demodulated signal (e.g., MPX signal in an FM broadcast) and provide a magnitude indication, such as the raw signal level, of a second demodulated signal that is less frequency selective than the first frequency-selective demodulated signal. A level estimation circuit is used to assess a running representation (or effective average) of the magnitude indication over time. In this manner, a speed or rate at which the level estimator assesses the running representation is controlled based on a degree of deviation or offset as indicated by the first frequency-selective demodulated signal relative to a carrier frequency used for the broadcast signal.

Abstract: A system and a method of demodulating a frequency shift keying signal are provided. The method includes steps of: inputting the frequency shift keying signal; accumulating cycles of the frequency shift keying signal to a reference cycle number from a time point; finding an initial point of each of pulse waves of the frequency shift keying signal; accumulating the cycles to the reference cycle number multiple times from the initial point and extracting data of each accumulation; determining whether or not the number of times of extracting the data reaches a preset value, if not, returning to the previous step, if yes, performing the next step; determining whether or not a difference between the data is larger than a threshold, if not, outputting a first bit value, if yes, outputting a second bit value; and packing the first and second bit values into a demodulated signal.

Abstract: A method includes, at a frequency shift keying (FSK) demodulator, determining a likelihood of a symbol having a first symbol value or a second symbol value, using the likelihood of the symbol to select either the first symbol value or the second symbol value for the symbol, the first symbol value or the second symbol value that is selected being a selected symbol value, selecting a frequency error from a first frequency error or a second frequency error, and using a down-mixer and the frequency error to correct a frequency drift associated with a future selected symbol value.

Abstract: A distributed antenna and backhaul system provide network connectivity for a small cell deployment. Rather than building new structures, and installing additional fiber and cable, embodiments described herein disclose using high-bandwidth, millimeter-wave communications and existing power line infrastructure. Above ground backhaul connections via power lines and line-of-sight millimeter-wave band signals as well as underground backhaul connections via buried electrical conduits can provide connectivity to the distributed base stations. An overhead millimeter-wave system can also be used to provide backhaul connectivity. Modules can be placed onto existing infrastructure, such as streetlights and utility poles, and the modules can contain base stations and antennas to transmit the millimeter-waves to and from other modules.

Abstract: A device of one aspect of the present invention includes a receiver to receive a modulation signal that has been subjected to frequency shift keying division ratio. The receiver includes a first demodulator and a demodulation control signal generator. The demodulation control signal generator includes a first frequency divider, a frequency control signal generator, and an oscillator. The first frequency divider divides a frequency of one of the modulation signal and the demodulation control signal by a first or second reception division ratio. The frequency control signal generator generates a frequency control signal based on a frequency of the other of the modulation signal and the demodulation control signal, and a frequency of the one of the modulation signal and the demodulation control signal obtained by division by the first or second reception division ratio. The oscillator generates the demodulation control signal based on the frequency control signal.

Abstract: A phase rotator corrects the IQ imbalance in a wireless transceiver. The phase rotator is a part of a compensation system that detects and separates reception impairment images from transmission impairment images. The disclosed phase rotator introduces a phase shift between the transmission channel and the reception channel without perturbing the phase mismatch and the gain mismatch in the reception path. The phase rotator includes a first local oscillation (LO) circuit that generates a first LO signal at a first carrier frequency and a second LO circuit that generates a second LO signal at a second carrier frequency that deviates from the first carrier frequency for a phase rotation period. The phase rotation period is sufficiently long such that the frequency deviation can introduce a prescribed phase shift between the first LO signal and the second LO signal.

Abstract: An integrated multi-user satellite receiver includes: a single-chip, and the single-chip includes: a first synthesizer for generating a first oscillating signal having a first frequency; a first frequency multiplier for generating a second oscillating signal having a second frequency according to the first oscillating signal; a second synthesizer for generating a third oscillating signal having a third frequency; and a second frequency multiplier for generating a fourth oscillating signal having a fourth frequency according to the third oscillating signal; wherein the single-chip generates a first down-converted signal according to a first satellite signal and the second oscillating signal, generates a second down-converted signal according to the first satellite signal and the fourth oscillating signal, generates a third down-converted signal according to a second satellite signal and the second oscillating signal, and generates a fourth down-converted signal according to the second satellite signal and the

Abstract: Presented herein are techniques to reduce error probability and eliminate the lingering signal that causes problems during audio signal data transmission. An electroacoustic transducer of a first electronic device receives a data encoded audio signal that includes modulated digital data therein. The data encoded audio signal is demodulated to produce a present input signal that includes a target frequency and a lingering effect of a previously received data encoded audio signal. Lingering cancellation is performed on the present input signal to produce a present output signal from which the lingering effect of the previously received data encoded audio signal has been removed.

Abstract: A four-phase clock generator with timing sequence self-detection including a phase-locked loop (PLL), a frequency dividing module, and a detection and control module. The PLL generates a first to a fourth reference clock signal with the same frequency, respectively, wherein each consecutive two of the first to the fourth reference clock signals have a 90-degree phase difference. The frequency dividing module is coupled to the PLL and determines whether to perform frequency dividing on the first to the fourth reference clock signals to obtain a first through a fourth output clock signal according to a first control signal. The detection and control module is coupled to the frequency dividing module and detects a timing sequence of the first to the fourth output clock signals to output the first control signal accordingly.

Abstract: A method for determining arrival time of a UWB pulse at a receiver. When a pulse is modulated at an RF frequency, the receiver includes a quadrature demodulator, a first correlating stage for correlating the in-phase signal with the first and second signals of an orthogonal base on a time window and a second correlating stage for correlating the quadrature signal with the first and second signals of the orthogonal base on the same window, a phase estimator estimating the phase of the signal received in the orthogonal base from the correlation results of the first and/or second correlating stage(s), and a computing device determining the arrival time from the phase thus estimated.

Abstract: A clock-data recovery circuit includes a variable delay circuit that adjusts timing of a recovered clock by an amount to recover a received data stream at timing corresponding to a maximum opening of an eye pattern of the data stream. The delay timing is adjusted iteratively. The data stream in input to a 2-bit ADC, where the sampled data stream is compared with reference values representative of conditions of the eye pattern, and a result of the comparisons increases or decreases the clock delay according to a relative height of the eye pattern. A method of clock-data recovery uses the recovery circuit.

Abstract: A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

Abstract: A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

Abstract: A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

Abstract: Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

Abstract: A transmitter includes an encoding module, an adaptive hierarchical signal mapping module and a transceiver module. The encoding module receives an input signal and encodes the input signal. The input signal includes data to be transmitted. The adaptive hierarchical signal mapping module modulates the encoded signal according to one or more hierarchical level distance ratios to obtain modulated symbols. The hierarchical level distance ratio defines distances between the modulated symbols. The transceiver module generates a radio frequency signal according to the modulated symbols and transmits the radio frequency signal to an air interface.

Abstract: A receiver front end receives a local frequency reference signal and a Frequency Shift Keying modulated signal comprising a synchronisation sequence, and downconverts the Frequency Shift Keying modulated signal to provide baseband in-phase and quadrature signals. A pulse generator receives the in-phase and quadrature signals, generates an in-phase pulse signal ILEAD comprising pulses aligned with edges of the baseband in-phase and quadrature signals when the baseband in-phase signal leads the baseband quadrature signal, and generates a quadrature pulse signal QLEAD comprising pulses aligned with edges of the baseband quadrature and in-phase signals when the baseband quadrature signal leads the baseband in-phase signal. A frequency corrector receives the in-phase and quadrature pulse signals during receipt of the synchronisation sequence, compares the pulse signals to a target, and generates a control signal for controlling the local signal generator in dependence upon the result of the comparison.

Abstract: Apparatus and methods for demodulation are provided. In one embodiment, a method includes receiving an input signal having a frequency that varies in relation to a state of the signal, calculating a sine and cosine of a phase control signal, generating a first signal proportional to the sine of a product of a first quantity and the frequency of the input signal, generating a second signal proportional to the cosine of a product of the first quantity and the frequency of the input signal, and summing a product of the first signal and the cosine of the phase control signal with a product of the second signal and the sine of the phase control signal to generate a demodulator output for resolving the state of the input signal. In certain implementations, the phase control signal is controlled so as to reduce a frequency error of the input signal.

Abstract: The invention discloses a dual frequency multiplexer by which a first and second coaxial harmonic oscillator type band pass filters are disposed in a box. The box includes a base body, a cover plate and a cover body. The two coaxial harmonic oscillator type hand pass filters are located on the base body and spaced each other by a metal plate; the multiplexer port, first and second ports are positioned on lateral side of the base body. The blocking capacitors are contained in the coaxial chamber of the two coaxial harmonic oscillator type band pass filters. The cover plate is secured on the base body; the first and second direct current circuits are placed on the cover plate; the low pass filters of the first and second direct current circuits are fixed on an edge of a top surface of the coaxial chamber by means of a support member; the cover body and the base body are fastened with each other. The blocking capacitors each are of distributed parameter capacitor.

Abstract: A binarization circuit includes a comparator that outputs a signal according to a differential voltage between the input and reference voltages. The first charging-discharging circuit generates a first voltage. The second charging-discharging circuit generates a second voltage. The control circuit compares the differential voltage with the threshold voltage, and switches between turn-on and turn-off of the second charging-discharging circuit based on a difference between the differential voltage and the threshold voltage. A sum of the reference and first voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned off. A sum of the reference and the first and second voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned on.

Abstract: A carrier offset detection circuit is offered, which is provided to a demodulation circuit which demodulates a received signal subjected to FSK (Frequency Shift Keying) modulation, and which detects the offset of the carrier frequency between the transmitting side and the receiving side. A zero-crossing detection unit receives a digital base band signal indicating the level of the frequency shift (frequency deviation) of the received signal using the carrier frequency on the receiving side as a reference frequency, and detects a zero-crossing point of the base band signal and a base band signal obtained by delaying the former base band signal by one symbol, which occurs in a preamble period. A carrier offset detection circuit sets the offset value of the carrier frequency to the value of the base band signal at a timing of the zero-crossing point thus detected.

Abstract: A quadrature demodulation circuit includes: first to fourth mixers to receive a modulation signal; a phase shifter to supply to the first and third mixers a first local frequency signal, to supply to the second mixer a second local frequency signal having a designated phase difference relative to the first local frequency signal, and to supply to the fourth mixer a third local frequency signal that is an inverse in phase to the second local frequency signal; a first adder to add a signal output from the first mixer and a signal output from the second mixer and to output a first demodulation signal; and a second adder to add a signal output from the third mixer and a signal output from the fourth mixer and to output a second demodulation signal.

Abstract: A method of generating a phase value representative of a phase of a complex signal that includes an in-phase component and a quadrature-phase component includes determining a first sign for a first value and a second sign for a second value based on a quadrant occupied by the complex signal. The in-phase component is multiplied by the first value with the first sign, thereby generating a first multiplication result. The quadrature-phase component is multiplied by the second value with the second sign, thereby generating a second multiplication result. The first multiplication result, the second multiplication result, and a bias value are added, thereby generating the phase value for the complex signal.

Abstract: Frequency demodulation of a signal is disclosed. A first edge event and a second edge event are detected in a signal. The second edge event is an edge event subsequent in time to the first edge event. A data bit based at least in part on a timing interval between the first edge event and the second edge event is determined.

Abstract: A receiver has a first voltage control oscillator configured to generate a first oscillation signal, a second voltage control oscillator configured to generate a second oscillation signal having a first phase, a first phase comparator configured to detect a phase difference between the first and second oscillation signals, a demodulator configured to perform demodulation processing of the received signal and to generate timing information of a second phase included in the first oscillation signal, a second phase comparator configured to detect the phase difference between the first and second oscillation signals, and a first control voltage generator configured to generate a first control voltage for controlling a phase and a frequency of the second voltage control oscillator based on the phase difference detected by the second phase comparator.

Abstract: Aspects of a method and system for communicating via a spatial multilink repeater are provided. In this regard, a received signal may be frequency shifted to generate a plurality of repeated signals, wherein each repeated signal may be shifted by a different frequency with respect to the received signal. Each repeated signal may comprise one or more signal components and a phase and/or amplitude of each of the components may be controlled to control a directivity of the repeated signals. Each of the repeated signals may be generated by quadrature down-converting said received signal by mixing the received signal with a first LO signal pair, up-converting the down-converted signal by mixing it with a second LO signal pair, and adding or subtracting an in-phase portion and a quadrature-phase portion of the up-converted signal.

Abstract: The present invention is a quadrature multi-mode RF receiver that uses a single quadrature mixer for tuning to desired frequency bands. In a direct conversion mode of operation, the RF receiver down converts a received RF signal directly into a baseband signal. In a VLIF mode of operation, the RF receiver down converts a received RF signal into a VLIF signal. When receiving a wanted RF signal, the frequency of the resulting VLIF signal is called the wanted VLIF frequency, and is based on the signal strength of the received RF signal. In one embodiment of the present invention, the wanted VLIF frequency is selected to be one of two VLIF frequencies. The wanted VLIF frequency is inversely related to the signal strength of the received RF signal.

Abstract: Nanoantennas are formed on a substrate (e.g., silicon) and generate light via interactions with a charged particle beam, where the frequency of the generated light is based in large part on the periodicity of the “fingers” that make up the nanoantennas. Each finger has typical dimensions of less than 100 nm on the shorter side and typically less than 500 nm on the longer, but the size of the optimal longer side is determined by the electron velocity. The charged particle may be an electron beam or any other source of charged particles. By utilizing fine-line lithography on the surface of the substrate, the nanoantennas can be formed without the need for complicated silicon devices.

Abstract: A receiver to process a RF input signal having a plurality of channels includes a direct down conversion circuit, a demodulation circuit, and a local oscillator circuit. The direct down conversion circuit provides a downconverted signal based on the RF input signal and a local oscillator signal. The demodulation circuit receives the downconverted signal and provides a demodulated signal. The local oscillator circuit sets a frequency of the local oscillator signal based on a selected channel of the plurality of channels.

Abstract: A frequency shift keying demodulator robust for frequency offset is provided. The demodulator is used to enable the signal to be received correctly when the frequency offset occurs. A microprocessor of demodulator controls a frequency mixer and a phase difference generator according to the duty cycle of the preamble when receiving the preamble of the demodulated signal. Therefore, the duty cycle of the preamble of the demodulated signal can be close to 50%, and the data from a transmitter is received correctly.

Abstract: Apparatuses and methods for testing the integrity of high speed optical fiber transmission networks are presented. Data from an optical network, for example, NRZ formatted data at forty gigabits per second and higher may be reliably recovered using embodiments of the invention. The invention employs hybrid microwave and high speed processing technology to reliably measure the phase shift of the data transmitted over a high speed optical transmission network by comparing the incoming data to a super-stable clock/frequency reference. The clock/frequency reference is intentionally offset by fractional frequency resulting in a beat frequency when compared to the incoming data. The beat frequency provides the ability for automatic calibration of the phase measurements because the period of the full 360 degrees phase is known. Also, the invention provides reliable means for measuring jitter and for generating Eye-pattern diagrams by eliminating issues associated with oscilloscope loop bandwidth limitations.

Abstract: Structures and techniques for implementing multiple-antenna configurations within a radio frequency receiver are provided. In one aspect, a modularized multi-antenna receiver is provided having multiple independent microelectronic dice mounted on a common module substrate. In another aspect, a multi-antenna receiver is provided that utilizes at least one single ended low noise amplifier and at least one differential low noise amplifier within a common receiver.

Abstract: An apparatus for a direct down-conversion of modulated RF signals, the device including: a first power detector connected between an input port for the modulated RF signal and ground, which outputs a first DC signal, a second power detector connected between an input port for a local oscillator signal and ground, which outputs a second DC signal, the local oscillator signal having the same center frequency as the modulated RF signal, and a third power detector connected between the input port for the modulated RF signal and the input port for the local oscillator signal, which outputs a third DC signal.

Abstract: An analogue output signal of a sensor which comprises a carrier signal with a carrier frequency ?C which is modulated by a measurement size is sampled with a sampling frequency ?A to receive a sampled sensor output signal. The frequency ?A of the sampling signal is set so that it is an integer divisor n of the carrier frequency ?C, wherein the phase of the sampling signal is set so that the sampling signal is synchronous to the sensor output signal. The sampled sensor output signal is filtered now to remove periodically repeated signal components from the sampled sensor output signal. Then a filtered useful signal is received, wherein its amplitude is proportional to the measurand detected by the sensor.

Abstract: A demodulation arrangement for a radio signal is disclosed wherein an I/Q mixer converts the radio signal to a real and an imaginary component and supplies the components to a limiting circuit. The limiting circuit limits the amplitude of the signals applied to its inputs. A demodulator circuit receives the output of the limiting circuit and converts the signal components to a demodulated signal including a sequence of pulses. A pulse shaper circuit converts the pulses having pulse amplitudes that are greater than a first threshold value to output pulses having a predetermined first amplitude. This reduces fluctuations in the pulse amplitudes, thus leading to a reduction in low-frequency interference and jitter in the data signal.

Abstract: A frequency discriminators (FD) and frequency modulation (FM) demodulators, utilizing single sideband (SSB) complex conversion directly to zero IF, suitable for direct demodulation at high frequencies of analog FM or digital FSK modulated signals, as well as for high speed frequency discrimination (or frequency comparison) in applications such as frequency acquisition in frequency synthesizers. The complex SSB down-converter consists of a quad of mixers and quadrature splitters in both the signal path and local oscillator (LO) path. Each mixer receives both the signal and the LO, each either in-phase or quadrature. The outputs of mixers are combined in pairs, to produce the SSB in-phase (I) baseband signal and the SSB quadrature (Q) baseband signal. Both I and Q signals are then delayed, each multiplied by un-delayed version of the other one. The multiplication products are summed together, to produce an FD error signal, or an FM demodulated signal at the output.

Abstract: A circuit for detecting and correcting a center level is constituted for when the length of a code of “1” or “0” in an FSK signal is extremely long and superimposed with a frequency fluctuation of a transmitter/receiver. This circuit has sample value holding circuits exclusive to “1” and “0” of an input demodulation data signal. After a difference voltage between both sample values is once converted to a digital code in an ADA converter, the converted code is re-converted to an analog value, thereby holding the value digitally. When “1” s repeat, the hold voltage to “1” is updated to new values and simultaneously a voltage obtained by subtracting the difference voltage from the above-described voltage is applied to the holding circuit for “0” to update the value in the holding circuit. Also, when “0”s repeat, the processing proceeds in reverse and the holding circuit for “1” is updated with a voltage obtained by adding the difference voltage to the hold voltage.

Abstract: A frequency discriminators (FD) and frequency modulation (FM) demodulators, utilizing single sideband (SSB) complex conversion directly to zero IF, suitable for direct demodulation at high frequencies of analog FM or digital FSK modulated signals, as well as for high speed frequency discrimination (or frequency comparison) in applications such as frequency acquisition in frequency synthesizers. The complex SSB down-converter consists of a quad of mixers and quadrature splitters in both the signal path and local oscillator (LO) path. Each mixer receives both the signal and the LO, each either in-phase or quadrature. The outputs of mixers are combined in pairs, to produce the SSB in-phase (I) baseband signal and the SSB quadrature (Q) baseband signal. Both I and Q signals are then delayed, each multiplied by un-delayed version of the other one. The multiplication products are summed together, to produce an FD error signal, or an FM demodulated signal at the output.

Abstract: A method of, and terminal for, detecting the presence of a 2-FSK signal, the method comprising receiving (10) a 2-FSK signal, quadrature frequency down-converting (34,35,36) the received signal to produce quadrature related outputs, oversampling (42,43) the quadrature related outputs to produce digital samples, differentially decoding (44) the digital samples to produce real and imaginary components, integrating (56,58) the imaginary components and comparing (26) the integrated value with a fixed threshold value (24) and determining a signal to be present if the threshold is exceeded.

Abstract: A method and apparatus for frequency shift-keying (FSK) demodulation includes processing that begins by generating a charge signal, a data acquisition signal, and a reset signal from an I component and a Q component of an FSK modulated signal. The processing continues by generating a delta frequency signal based on the charge signal, the data acquisition signal, and the reset signal. The delta frequency signal is representative of the frequency difference used within the FSK modulation to indicate a logic 1 and a logic 0. The processing then continues by demodulating the delta frequency signal to recapture a stream of data.

Abstract: In a method for demodulating an analog FSK signal (FSKin), a current sample (Id(k);Idi) of the downconverted and digital inphase component is multiplied with a previous sample (Qd(k−1);Qdi−1) of the downconverted an digital orthogonal phase component. The product thereof is subtracted from the product obtained by multiplying a current sample of said orthogonal phase component (Qd(k); Qdi) with a previous sample (Id(k−1); Idi−1) of said inphase component. Said current and said previous samples of said inphase and said orthogonal phase components are spaced apart by the digital baseband signal period. In a variant method said current sample and said previous sample of said inphase and orthogonal phase component are spaced apart by an integer fraction (n) of said digital baseband signal period,whereby the steps of said method are repeated, thereby further adding consecutive values of the result Ri).

Abstract: A method and apparatus for frequency shift-keying (FSK) demodulation includes processing that begins by generating a charge signal, a data acquisition signal, and a reset signal from an I component and a Q component of an FSK modulated signal. The processing continues by generating a delta frequency signal based on the charge signal, the data acquisition signal, and the reset signal. The delta frequency signal is representative of the frequency difference used within the FSK modulation to indicate a logic 1 and a logic 0. The processing then continues by demodulating the delta frequency signal to recapture a stream of data.

Abstract: A method for estimating an interference phase shift when receiving a multicarrier signal formed of a time series of symbols modulating a plurality of carrier frequencies, at least some of the carrier frequencies of at least some of the symbols bearing reference elements, whereof the value at transmission level is known by the receiver carrying out the reception. The phase variation &dgr;n between at least two symbols bearing reference elements is estimated by analysing the reference elements. Each of the reference elements in the estimation is weighted by information representing the noise affecting the carrier frequency bearing the reference element.

Abstract: An FM demodulator in accordance with the present invention receives a composite signal from an antenna and corresponding processing circuitry. The composite signal includes a carrier signal having a voice/data signal modulated thereon. The composite signal is processed to separate the voice/data signal from the carrier signal. The voice/data signal is separated into an in-phase (I) signal and a quadrature (Q) signal. The Q signal is differentiated and then divided by the I signal to obtain the voice/data signal. Alternatively, I signal is differentiated and then divided by the Q signal to obtain the voice/data signal.

Abstract: In a receiver for FSK modulated signals, an input signal is applied to a converter (20) which mixes the input signal with a local oscillator frequency. The frequency of the local oscillator is unrelated to the frequencies of the FSK signal, resulting in a larger degree of freedom for choosing the local oscillator frequency. This oscillator frequency can e.g. be chosen to be one fourth of the sample frequency the input signal is sampled with.

Abstract: A demodulator circuit (10) includes an oscillator (12) and an injection circuit (14). An Automatic Frequency Control (AFC) signal adjusts the tail current of a current source (28) provided in the oscillator (12) and the tail current of a current source (44) provided in the injection circuit (14). A phase detector (16) compares the phase of the signal generated by the oscillator (12) with the phase of the injected input signal. The phase detector (16) generates an output signal V0 having a value of zero when the input signal is in quadrature with the signal generated by the oscillator (12), but generates a non-zero signal that is used to adjust the AFC signal when the input signal and the signal generated by the oscillator (12) are not in quadrature.