Abstract: An occurrence of a first set of n periods of a frequency-shift-keying (FSK)-modulated waveform is counted, where n is an integer number. The n periods of the FSK-modulated waveform in the first set have a first time duration. An occurrence of a second set of n periods of the waveform is counted. The n periods of the waveform in the second set have a second time duration. The first time duration is determined based on the counting of the first set of n periods. The second time duration is determined based on the counting of the second set of n periods. A difference between the first time duration and the second time duration is compared to a threshold. Changes in frequency of the waveform are detected based on the comparing of the difference between the first time duration and the second time duration to the threshold.

Abstract: A frequency-shift keying (FSK) demodulator includes a digital phase-locked loop (DPLL) based frequency estimator to convert a phase signal to a frequency signal, a frequency offset estimator to estimate and track direct current (DC) component of the frequency signal, and an average filter communicatively coupled to the frequency offset estimator to perform an accumulate-and-dump operation to improve a symbol-level signal to noise ratio (SNR) of the frequency signal.

Abstract: The present application relates to a self-adaptive receiving method, device, and system for a wireless signal, where the receiving method is characterized by: detecting an electric signal, and recording and storing a duration of each level of the electric signal; determining a decision time interval according to the duration of each level, where the decision time interval is used to determine a location of the spacing level between the electric signal groups of the electric signal; comparing the duration of each level with the decision time interval to recognize each electric signal group; when the duration of the level is less than the decision time interval, determining the level as the intragroup time interval and recording the data of the electric signal groups; and when the duration of the level is greater than or equal to the decision time interval, determining the level as the intergroup time interval and confirming an end of the electric signal groups.

Abstract: A comparator includes a first comparison unit configured to compare an input signal with a first signal and a second comparison unit configured to compare the input signal with a second signal having a voltage value lower than a voltage value of the first signal in a case where a voltage value of the input signal is lower than the voltage value of the first signal and compare the input signal with a third signal having a voltage value higher than a voltage value of the first signal in a case where a voltage value of the input signal is higher than the voltage value of the first signal.

Abstract: A detecting apparatus includes a threshold detection circuit that detects by a switchable time constant, a threshold of a level of an input optical burst signal; an input detection circuit that detects input of the optical burst signal; a level detection circuit that detects a level of the optical burst signal; a switching circuit that switches the time constant when a period that corresponds to the level detected by the level detection circuit has elapsed after the input is detected by the input detection circuit; and an output circuit that outputs the threshold detected by the threshold detection circuit.

Abstract: A circuit to detect states of a signal is provided. The circuit comprises an input node to receive an input signal. A state detection circuit detects a state of the input signal and generates a detection signal. The state corresponds to at least one of three states. Furthermore, the detection signal generated by the state detection circuit has a level based on the detected state of the input signal. A logic discriminator circuit generates first and second state signals based at least partly on the level of the detection signal. A clock detection circuit generates a clock signal based at least partly on a sequence of logic transitions of the first and second state signals.

Abstract: This application discusses among other things, apparatus and method for transmitting data with an analog signal without significantly distorting the analog signal. In an example, an apparatus can include an audio channel, a capacitor coupled to a first conductor of the audio channel, the capacitor configured to couple an analog representation of a digital data signal with an analog audio signal on the audio channel, and a frequency modulator configured to receive the digital data signal and to modulate a frequency of an output signal of the frequency modulator based on a logic level of the digital data signal, wherein the analog representation of the digital data signal includes the frequency of the output signal of the frequency modulator.

Abstract: An FSK demodulator and a method for detecting an inflection point extract a greater amount of effective inflection points of a frequency detection signal while reducing erroneous detection of the inflection points. The inflection point detector includes an inflection point extraction part to extract the inflection point corresponding to variation of a sample value of an amplitude value of the frequency detection signal, an amplitude determination part to determine if a size between peak values of sample values in front and rear of the inflection point exists in a first predetermined range, a preamble determination part to determine if a difference between initial and final sample values of at least one of a symbol having the extracted inflection point and a right before symbol exists in a second predetermined range, and an AND operation part to determine a normal inflection point.

Abstract: A binarization circuit includes a comparator that outputs a signal according to a differential voltage between the input and reference voltages. The first charging-discharging circuit generates a first voltage. The second charging-discharging circuit generates a second voltage. The control circuit compares the differential voltage with the threshold voltage, and switches between turn-on and turn-off of the second charging-discharging circuit based on a difference between the differential voltage and the threshold voltage. A sum of the reference and first voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned off. A sum of the reference and the first and second voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned on.

Abstract: An FSK demodulator and a method for detecting an inflection point extract a greater amount of effective inflection points of a frequency detection signal while reducing erroneous detection of the inflection points. The inflection point detector includes an inflection point extraction part to extract the inflection point corresponding to variation of a sample value of an amplitude value of the frequency detection signal, an amplitude determination part to determine if a size between peak values of sample values in front and rear of the inflection point exists in a first predetermined range, a preamble determination part to determine if a difference between initial and final sample values of at least one of a symbol having the extracted inflection point and a right before symbol exists in a second predetermined range, and an AND operation part to determine a normal inflection point.

Abstract: A carrier offset detection circuit is offered, which is provided to a demodulation circuit which demodulates a received signal subjected to FSK (Frequency Shift Keying) modulation, and which detects the offset of the carrier frequency between the transmitting side and the receiving side. A zero-crossing detection unit receives a digital base band signal indicating the level of the frequency shift (frequency deviation) of the received signal using the carrier frequency on the receiving side as a reference frequency, and detects a zero-crossing point of the base band signal and a base band signal obtained by delaying the former base band signal by one symbol, which occurs in a preamble period. A carrier offset detection circuit sets the offset value of the carrier frequency to the value of the base band signal at a timing of the zero-crossing point thus detected.

Abstract: A method and system for a frequency shift key demodulation is provided. The system includes a counting block for counting a reference clock within a window defined by a modulated signal, a detector for comparing a count value output from the counting block with digital multi-level thresholds and outputting baseband data based on the comparison, and a configurations block for configuring at least one of the counting block and the detector. The method includes counting a reference clock within a window defined by the FSK modulated signal and outputting a count value as a result of the counting, and comparing the count value with multi-level thresholds to output baseband data based on the comparison.

Abstract: A DSP tuner, which is equipped with an A/D converter and a digital signal processing part, is provided to the receiving parts of an in-vehicle equipment and a portable equipment that constitute an in-vehicle equipment remote control system. The A/D converter quantizes analog input signals received by receiving antennas and converts them into digital values. The digital signal processing part always appears, and removes as a noise a frequency band of which spectrum hardly change within a predetermined time period. Moreover, the digital signal processing part sets a frequency band with a comparatively large spectrum change as an FSK modulation signal corresponding to code contents, and outputs binary data corresponding to the frequency band as a code signal.

Abstract: A demodulator circuit for demodulating a signal modulated by frequency shift keying discriminates the frequency of the signal to produce demodulated data. When the demodulated data match a known synchronization pattern, or are complementary to the known synchronization pattern, the demodulator circuit latches a value indicating whether the demodulated data match or are complementary to the synchronization pattern. If the latched signal indicates matching data, subsequent demodulated data are output as is. If the latched signal indicates complementary data, subsequent demodulated data are inverted and the inverted data are output. The output data are therefore correct even if the demodulated data are inverted.

Abstract: An FSK demodulator which outputs an enable signal in response to the detection of a data change point in a detected signal of an amplitude associated with the received frequency of an input FSK signal, outputs an average signal of the detected signal for each predetermined time period, acquires the average signal in response to the enable signal to output as an offset signal an average value of M average signals, and subtracts the offset signal from the detected signal to output the resulting signal.

Abstract: Channel selection of a received signal is first of all carried out, in the process, by way of an analog channel selection filter. The signal is then converted to a digital discrete-time and discrete-value signal. Finally, the continuous-time and continuous-value signal profile is determined on the basis of a mathematical reconstruction using the zero crossings {ti} and the phase values {?(ti)=ki·?/2, ki?N0}, with a mathematical reconstruction algorithm using a function system {?(t?k)}.

Abstract: A non-coherent frequency shift key demodulator comprising an oversampling device, a chain of registers, and a threshold device is disclosed. The oversampling device receives an input digital non-coherent frequency shift signal, and examines for transitions therein, and thereby generating data bit signals in the form of logic high level ‘1’ or logic low level ‘0’ accordingly. The chain of registers receives, counts and stores the number of 1's data bit signals. Following, the threshold device compares the stored number of 1's in the chain of registers with a predetermined threshold value to extract the digital signal of the input digital non-coherent frequency shift signal. The non-coherent frequency shift key demodulator, by the use of a simple circuit and implementation, combats miscellaneous system impairments, such as frequency offset, and further support multi-rate transmission.

Abstract: A frequency discriminator for detecting phase shifts between sequential pulses in a frequency-shift keyed (FSK) signal having a nominal frequency, f. The frequency discriminator comprises: 1) a first current controlled delay line for receiving the FSK signal and delaying the FSK signal by a desired time delay to thereby produce a time-delayed FSK signal; 2) a multiplier for receiving and multiplying the FSK signal and the time-delayed FSK signal to thereby produce an output product signal proportional to a phase shift between said FSK signal and said time-delayed FSK signal; and 3) a delay locked loop comprising a second current controlled delay line substantially similar to the first current controlled delay line.

Abstract: All-digital FSK demodulation can be accomplished by producing in response to a received IF signal digital information (22) indicative of a frequency of the IF signal. A symbol represented by the IF signal can then be determined (28, 44) in response to the digital information.

Abstract: There is provided a signal demodulating method of a two-phase frequency shift keying (FSK) digital demodulator. The method utilizes at least a detect circuit respectively detecting and collecting a positive edge signal and a negative edge signal of an intermediate frequency signal. Then, two n-bit ripple counters are utilized to refer to a threshold value and then receiving the positive and negative edge signal as a switch signal to reset the threshold value as an initial value of counters so as to start to count and compare to output a positive edge data bit and a negative edge data bit. Last, a hard decision logic circuit is used to perform a frequency-descending decision in accordance with the positive and negative edge data bit so as to send a base frequency signal. The method can decrease the logic gate counts, shorten the signal delay time, and increase the resolution of the demodulation.

Abstract: A FSK demodulation system of the present invention has a means for comparing two preset values across 0, a positive side level shift amount and a negative side level shift amount, with an inputted amplitude level; and a demodulation means for performing demodulation based on the comparison result.

Abstract: In a method for demodulating an analog FSK signal (FSKin), a current sample (Id(k);Idi) of the downconverted and digital inphase component is multiplied with a previous sample (Qd(k−1);Qdi−1) of the downconverted an digital orthogonal phase component. The product thereof is subtracted from the product obtained by multiplying a current sample of said orthogonal phase component (Qd(k); Qdi) with a previous sample (Id(k−1); Idi−1) of said inphase component. Said current and said previous samples of said inphase and said orthogonal phase components are spaced apart by the digital baseband signal period. In a variant method said current sample and said previous sample of said inphase and orthogonal phase component are spaced apart by an integer fraction (n) of said digital baseband signal period,whereby the steps of said method are repeated, thereby further adding consecutive values of the result Ri).

Abstract: An FM demodulator for reproducing data by performing FM demodulation of a received RF signal in a Bluetooth transmission system is provided. The FM demodulator includes a frequency discrimination unit and a level determination unit. The FM demodulator frequency-discriminates the RF signal, performs digital conversion of the discriminated RF signal, and outputs converted data. The level determination unit performs level comparison of current input-data, supplied from the frequency discrimination unit in the latest clock period, with last input-data, supplied from the frequency discrimination unit in the immediately preceding clock period, determines a logic state of the current input-data based on the result of the level comparison, and reproduces data in accordance with the determined logic state.

Abstract: A variable delay line detector (34, 48, 66)includes a power splitter (36, 50, 68), a mixer (44, 62, 72) and a variable delay line (42,52, 70). Various devices are suitable for the variable delay line (42, 52, 70), such as a non-linear transmission line (NLTL). By providing a variable delay line, the variable delay line detector (34, 48, 66) is adapted to be programmed in real time thus making it suitable in applications where the phase and or frequency of the input signal varies. As such, the variable delay line detector (34, 48, 66) may be used in applications heretofore unknown, such &a an inexpensive demodulator in a frequency hopped spread spectrum system.

Abstract: A cost-effective continuous phase logic-based modulator and demodulator are provided to allow communications using binary frequency shift keying (BFSK) as well as M-ary FSK techniques. The modulator of the 1-bit precision modem architecture is based on a 1-bit precision numerically controlled oscillator (NCO), which provides complete programmability with respect to a frequency of the 1-bit precision logic-based modulator and/or demodulator. The output of the 1-bit precision NCO is upconverted to an intermediate frequency using a simple logic function, i.e., XNOR logic. The undesirable portion of the upconverted signal may be suppressed using I/Q image rejection, and/or an appropriate bandpass filter may be used. A band limited, hard limited signal at the high IF is presented to the 1-bit precision demodulator as a receive IF signal, which is treated as a 1-bit quantization of the signal. The receive IF signal is digitally down-converted to a low IF signal to produce an alias signal at the low IF frequency.

Abstract: A FSK demodulator which uses the combination of a digital phase comparator and a digital controlled oscillator (DCO) in the form of a state machine to demodulate an FSK signal. The phase comparator compares the phase of the FSK signal with the output of the DCO to provide a signal to the DCO having a level dependent on the phase relationship between the two signals at the input to the comparator. The demodulator also includes a filter to obtain the data from the signal at the output of the comparator.

Abstract: A frequency demodulator of the present invention includes: an amplification section for receiving a frequency-modulated signal and amplifying the frequency-modulated signal based on a gain so as to produce a digital signal having a predetermined level and an inverted signal of the digital signal; a digital demodulation section for receiving the digital signal and frequency-demodulating the digital signal; an amplitude detection section for receiving the digital signal and the inverted signal of the digital signal, and detecting maximum amplitude values of the digital signal and the inverted signal for a predetermined period of time so as to produce an amplitude signal in proportion to the maximum values; and a gain controlling section for varying the gain based on the amplitude signal.

Abstract: In a demodulating device which comprises an orthogonal transforming circuit, an up-converting circuit, a pulse signal producing circuit, and a low-pass filter, the orthogonal transforming circuit orthogonally transforms a received frequency shift keying signal to produce a first base band signal and a second base band signal. A phase converting circuit converts a clock signal from a clock signal producing circuit to produce a first clock signal having a first phase and a second clock signal having a second phase. A first EXOR circuit receives the first base band signal and the first clock signal to produce a first EXOR output signal. A second EXOR circuit receives the second base band signal and the second clock signal to produce a second EXOR output signal. A mixing circuit mixes the first EXOR output signal and the second EXOR output signal to produce and supply an up-converted signal to the pulse signal producing circuit.

Abstract: A circuit is provided by which in the case of the transmission of a short packet signal through an FSK transmission channel having a frequency error for transmission and reception, directly from one shaped rectangular pulse of a frequency detected bit synchronization signal having a DC offset (this pulse including a bias distortion as it is) a clock signal can be generated indicating the points of time when the base-band signal passes through its center level and the point of time when it arrives its maximum or minimum value (data sampling points of time). This invention utilizes the fact that the bit synchronization signal is in the form of a sine wave because it has been band limited.

Abstract: A method and apparatus for noise burst detection in a signal processor is provided. The method and apparatus is based on the zero-crossing rate (ZCR) of the received signal, which is defined as the number of times the magnitude of the received signal becomes zero during a specific counting period, to determine whether the received signal is a noise or a normal signal. The received signal is sampled at a specified sampling rate. Whether the signal waveform undergoes a zero-crossing is determined by comparing the polarity of the current sampled magnitude with that of the previous one. If the polarities are different, it indicates that the signal waveform has undergone a zero-crossing during the current sampling period; otherwise, it indicates that the signal waveform has not undergone a zero-crossing. The count of zero-crossing during each counting period is compared with a preset threshold value.

Abstract: A multivalued FSK demodulation window comparator includes an MSB comparator, an LSB comparator, a reception electric field strength detector, and a reference voltage generating circuit. The MSB comparator determines at least the polarity of a frequency shift of a radio frequency. The LSB comparator determines the absolute value of the frequency shift of the radio frequency. The reception electric field strength detector detects the strength of a radio signal and outputs a signal corresponding to the detected strength. The reference voltage generating circuit changes the reference voltages of the LSB comparator in accordance with an output voltage from the reception electric field strength detector. When the output voltage from the reception electric field strength detector is not higher than a predetermined level, a reference voltage from the reference voltage generating circuit changes.

Abstract: A signal detection circuit employs a delay line with edge detection logic for capturing and buffering timing information about an input signal. A plurality of comparators for comparing the input signal to different reference potentials capture amplitude information in the input signal launching bits into respective delay lines. Preferably, each delay line includes a counter for counting detected bit edges.

Abstract: A bit synchronization circuit receives polarity-judged output signal and a level-judged output signal that are produced through demodulation of a 2-value FSK or 4-value FSK transmission signal. Flip-flop circuits and an exclusive-OR circuit generate a second sampling output by sampling and delaying the polarity-judged output signal. Flip-flop circuits and an exclusive-NOR circuit generate a third sampling signal having a given temporal relationship with the second sampling output by sampling and delaying the level-judged output signal. AND circuits supply a correction signal to a counter circuit when levels of the second and third sampling outputs and a phase signal indicating a correction period of the counter circuit satisfy a given relationship. In response to the correction signal, the counter circuit corrects its count so as to produce a clock signal having a rate that is equal to a transmission rate of the transmission signal.

Abstract: A demodulator for demodulating an MSK signal constituted by a sequence of MSK modulated symbols is disclosed. An exclusive OR signal obtained by delay detection is delayed by delay times shorter than one symbol time. The delayed signals thus obtained are logically processed in parallel. Each symbol thus can be recovered by demodulation in one symbol time.

Abstract: A frequency discriminator circuit that includes a signal shaping and power splitting circuit (20) responsive to a sinusoidal RF input signal for providing first and second substantially identical squarewave outputs having the same frequency as the sinusoidal RF signal, a digital delay line (19) responsive to the first squarewave output for providing a delayed replica of the first squarewave output, an exclusive OR gate (21) responsive to the second squarewave output and the delayed replica of the first squarewave output, low pass filters (23, 25) for averaging each of the inverted and non-inverted outputs of the exclusive OR gate, and a differential amplifier (27) for subtracting the outputs of the low pass filters from each other and providing an output indicative of the frequency of the RF input signal.

Abstract: Known is a receiver having a demodulator for intermediate frequency modulated frequency shift keyed signals. The known demodulator applies absolute period time measurements expressing the period of a divided IF-signal into clock pulses of a relatively high frequency reference clock to detect data from a received signal. Such a demodulator is sensitive to frequency drift of the reference clock and has a relatively large power consumption. A receiver is proposed having a demodulator that is arranged to transform the intermediate frequency modulated frequency shift keyed signal into a lower frequency modulated frequency shift keyed signal so that the relative frequency deviation representing the data becomes substantially larger.

Abstract: A digital frequency demodulator includes a first counter and a second counter measuring the instantaneous and mean values of the period of a frequency modulated signal. A comparator compares the values measured and creates a binary signal of the same frequency as the modulation signal. The measurement of the instantaneous value of the frequency modulated signal is effected by counting the number of reference clock pulses during a period of the modulated signal, and the measurement of the mean value is effected by counting the number of pulses of a clock signal of frequency N times lower than the reference clock during N periods of the modulated signal.

Abstract: A digital phase detector which generates low jitter when the phase-locked-loop is in lock. A delay line, combined with an UP/DOWN phase detector causes substantial overlap in the UP and DOWN signals from the detector. When the PLL is in lock, the overlapping signals substantially cancel each other out, minimizing the variations in the output frequency. Two approaches are disclosed: one delaying the UP signal sufficiently to overlap the DOWN signal, the other using a delay and an exclusive OR gate to generate the DOWN signal.

Abstract: In a quadrature receiver for phase and/or frequency modulated signals an intermediate phase signal is quantized to produce a quantized phase signal. The receiver includes a demodulator in which pulses are generated from the quantized phase signal and it is determined whether two successive pulses have different polarities, and if so, a reconstructed baseband signal transition is produced at a predetermined reconstruction instant between the two successive pulses. The reconstruction instant is chosen in the middle between two successive pulses for FSK modulation, and it is chosen at different positions between the two pulses for other types of modulation, such as GMSK or multi-level FSK.

Abstract: A signal FSK-modulated with a binary data signal has first signal portions representing first logical level data contained in the binary data signal and second signal portions representing second logical level data contained in the binary data signal. Each of the first signal portions has a first frequency and lasts for a first time period and each of the second signal portions has a second frequency and lasts for a second time period. These first and second time periods are determined such that a number of cycles of the FSK-modulated signal appearing in each of the first time periods is equal to a number of cycles of the FSK-modulated signal appearing in each of the second time periods.

Abstract: A miniaturized FSK demodulation circuit for accurately demodulating a signal having a small modulation index comprises a multiplier for multiplying a FSK modulated input signal by 4, an oscillator for generating a first signal having the same frequency and phase as the input signal, a phase shifter for producing a second signal by phase shifting the first signal by 90.degree.

Abstract: A digital filtering system for filtering a first and a second digital signals inputted from a FSK (frequency-shift-keying) demodulator to generate a first and a second filtered digital signals. The FSK demodulator is used for demodulating a four level FSK signal into the first and second digital signals.

Abstract: A receiver (100) is utilized for demodulating a multi-level frequency shift keyed (FSK) signal. The receiver (100) includes a mixer (102) for mixing the multi-level FSK signal to generate an in-phase signal and a quadrature signal, and a demodulator circuit (110) coupled to the mixer (102). The demodulator circuit (110) is adapted to count a sequence of state transitions of the in-phase signal and the quadrature signal and to determine a frequency deviation of the multi-level FSK signal based on the sequence of state transitions counted.

Abstract: A pulse-width modulating device comprises: a counter for generating a plurality of counter signals of n-bit, where n is an integer of 2 or more; a fundamental waveform generator for outputting a signal for the least significant bit of the count signal as the most significant bit of a fundamental waveform signal, obtaining a first product of inverted signals of all of the count signals for higher order bits than LSB, obtaining a second product of the first product and the count signal for a certain bit, carrying out this for every bit, and outputting n-bit fundamental waveform signals extending from the upper order bits to the lower order bits; and a pulse-width modulator for obtaining a product sum total for each bit of the n-bit data signal and each of the n-bit of fundamental waveform signals corresponding to the each bits of n-bit data and generating a pulse-width modulated signal, configured in such a manner that a pulse-width modulating signal having a pulse-width corresponding to the data signal and hav

Abstract: An apparatus and method for demodulating a frequency-shift keyed (FSK) signal to provide a data signal. An input FSK signal is processed in a waveform reshaper to generate a first pulse signal which includes a pulse for each cycle of the FSK signal. The first pulse signal is processed in a cycle counter to generate second and third pulse signals. The second pulse signal includes a pulse for each time a low clock pulse count is reached between pulses of the first pulse signal, and the third pulse signal includes a pulse for each time a high clock pulse count is reached between pulses of the first pulse signal. The low and high pulse counts are generally indicative of cycles of first and second FSK carrier frequencies, respectively, in the input FSK signal. The second pulse signal is processed in a data recognizer to generate a logic level indicator signal.

Abstract: A direct conversion Binary FSK radio receiver has an AFC loop comprising an Exclusive-Or phase detector 104 responsive to the I.sub.3 and Q.sub.3 signals. I and Q filters 100, 101 are not identical but have different frequency-phase characteristics such that their phase shifts are identical when the local oscillator 102 is correctly tuned and differ when the local oscillator is off-tune. Detector 104 detects the change of phase and applies a control signal to local oscillator 102 such as to return the local oscillator frequency to the correct value. Alternatively, identical filters may be used in the I and Q channels, circuits having different phase shifts being coupled between the I.sub.3 and Q.sub.3 signals and the inputs of the phase detector 104.

Abstract: A frequency-shift keying (FSK) demodulator demodulates a binary signal encoded in an FSK signal. The present invention employs a bandpass filter to filter out noise and pass the frequencies used in the modulation. A comparitor converts the received signal into a square wave. A divider reduces the frequency of the square wave signal by a dividing factor. A counter counts the number of square wave transitions in a predetermined time period. A decision device receives the dividing factor from the divider, and uses this factor to adjust the count measured. The adjusted count is compared to counts pertaining to modulated frequencies to select a frequency. A bit value associated with the selected frequency is output for the time period being demodulated.

Abstract: A signal modulated by frequency-shift keying is input to a detector consisting of an instantaneous phase detection circuit that detects the instantaneous phase of the input signal, a differentiating circuit that differentiates the instantaneous phase to obtain the instantaneous frequency, and a baseband processing circuit that recovers clock and data signals from the instantaneous frequency. To detect the instantaneous phase, the instantaneous phase detection circuit compares the logic levels of the input signal and a clock signal, and filters the resulting bit stream with a digital low-pass filter. The detector consists entirely of digital circuits that are well suited for large-scale integration.

Abstract: A decision feedback multiple symbol differential demodulator for Gaussian filtered Minimum Shift Keying (GMSK) has a performance very close to theoretical limit even under a fading channel. The demodulator implements a non-coherent, maximum likelihood (ML) search over multiple bit-time intervals. The past bit decisions are fed back to the ML decision logic. The improved performance of the demodulator is achieved by using old decisions in the ML decision logic.

Abstract: A demodulator for demodulating a binary frequency-modulated signal includes a demodulator with a quadrature tank circuit and a duty cycle monitor circuit. The quadrature tank circuit has a voltage-controllable resonant frequency for compensating for shifts in the carrier frequency of the incoming signal and shifts in the tank circuit component values so as to allow the use of a high-Q tank circuit and thereby maximize use of the incoming signal energy. The quadrature tank circuit is a reactive circuit (with both inductive and capacitive elements) which includes a varactor diode having a voltage-controllable capacitance. The duty cycle monitor circuit measures the duty cycle of the demodulated binary output from the demodulator, and provides a control voltage to the quadrature tank circuit for adjusting its center frequency of operation.