Including Logic Element (e.g., Logic Gate Or Flip-flop) Patents (Class 329/310)
  • Patent number: 10605942
    Abstract: A technique facilitates accumulation of information via arrays of seismic tools to enable improved assessment of subterranean reservoirs. A plurality of seismic tool arrays may be combined to increase the quantity of downhole seismic tools, e.g. sensors. The seismic tool arrays are synchronized, via downhole clock synchronization technology, in a manner which enhances seismic data collection via the combined seismic tool arrays. In drilling applications, the seismic tool arrays may be combined with a bottom hole assembly. For example, multiple seismic tool arrays may be combined in a logging-while-drilling platform.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: March 31, 2020
    Inventors: Adrien Hendra Soepriatna, Hideki Tanaka, Takashi Aoki
  • Patent number: 10419256
    Abstract: An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit; a data demodulation unit; and a data clock restoration unit.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: September 17, 2019
    Inventor: Benjamin P. Wilkerson
  • Patent number: 10061740
    Abstract: A receiver includes first, second, and third signal processors and a controller. The first signal processor provides a first signal in response to detecting a first attribute of a received signal. The second signal processor provides a second signal in response to detecting a second attribute of the received signal. The third signal processor provides a third signal in response to detecting a third attribute of the received signal and provides packet data. The controller enables the first signal processor in response to a receive enable signal, controls the third signal processor to provide the packet data in response to receiving the first signal and the third signal, and initializes the first signal processor and the third signal processor in response to receiving the first signal and the second signal.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: August 28, 2018
    Inventors: Hendricus de Ruijter, Wentao Li
  • Patent number: 9942062
    Abstract: An unlock detector includes a checker, an accumulator, and a comparator. The accumulator is electrically connected to the checker, and the comparator is electrically connected to the accumulator. The checker includes several checking units. The checker is configured to receive a sampled data signal and a sampled edge signal, and to check the sampled data signal and the sampled edge signal via the checking units to generate several checking results. The accumulator is configured to generate a counting value in a manner of counting according to the checking results. The comparator is configured to compare the counting value with a threshold to generate an unlock-detecting result.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 10, 2018
    Inventors: Yu-Chu Chen, Wen-Juh Kang, Cheng-Hung Wu
  • Patent number: 9923749
    Abstract: A method and wireless communication device for tracking frequencies of transmitted burst signals. The method includes receiving a burst signal, determining a quality of the burst signal and a carrier frequency of the burst signal, demodulating the burst signal based upon the determined carrier frequency, determining a frequency offset of the burst signal based on the determined carrier frequency, and when the quality of the burst signal exceeds a threshold, calculating a drift window based on the determined frequency offset.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: March 20, 2018
    Assignee: SR Technologies, Inc.
    Inventors: John C. Sinibaldi, Adam Ruan, Conrad C. Smith
  • Patent number: 9835662
    Abstract: Determination of electrical network topology and connectivity are described herein. A zero-crossing is indicated at a time when the line voltage of a conducting wire in an electrical grid is zero. Such zero-crossings may be used to measure time within a smart grid, and to determine the connectivity of, and the electrical phase used by, particular network elements. A first meter may receive a phase angle determination (PAD) message, including zero-crossing information, sent from a second meter, hereafter called a reference meter. The first meter may compare the received zero-crossing information to its own zero-crossing information. A phase difference may be determined between the first meter and the reference meter from which the PAD message originated. The first meter may pass the PAD message to additional meters, which propagate the message through the network. Accordingly, an electrical phase used by meters within the network may be determined.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: December 5, 2017
    Assignee: Itron, Inc.
    Inventors: Timothy James Driscoll, Hartman Van Wyk, Robert C Sonderegger, Christopher M Higgins
  • Patent number: 9813069
    Abstract: A clock and data recovery circuit includes a phase detector, an adder, and an oscillator circuit. The phase detector includes a sampling circuit, a comparison circuit, and a resampling circuit. The sampling circuit includes first through fourth flip-flops for receiving a data signal and first through fourth clock signals, and generating first through fourth sampling signals. The comparison circuit includes first through fourth logic gates for receiving the first through fourth sampling signals and generating first through fourth comparison signals, respectively. The resampling circuit includes fifth through eighth flip-flops for receiving the first through fourth comparison signals and the first through fourth clock signals, and generating first through fourth control signals, respectively. The adder receives the first through fourth control signals, and generates a frequency control signal. The oscillator circuit receives the frequency control signal, generates the first through fourth clock signals.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: November 7, 2017
    Assignee: SILAB TECH PVT. LTD.
    Inventors: Biman Chattopadhyay, Ravi Mehta
  • Patent number: 9673964
    Abstract: An example method for active load modulation includes determining a modulated portion and an unmodulated portion of a bit. Further, the example method includes during the modulated portion of the bit, holding a phase of a received carrier signal. In addition, the example method includes, during the unmodulated portion of the bit, synchronizing to the received carrier signal.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: June 6, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Mohammad Mahdi Ghahramani, Mazhareddin Taghivand, Niranjan Anand Talwalkar
  • Patent number: 9602094
    Abstract: A decoding circuit may include a section information generation unit suitable for generating section information corresponding to a section in which an input signal has a first value, a period information generation unit suitable for generating period information corresponding to a period of the input signal, a reference information generation unit suitable for generating reference information by dividing a value of the period information by a given value, and a comparison unit suitable for determining a logic value of the input signal by comparing the section information with the reference information.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 21, 2017
    Assignee: SK Hynix Inc.
    Inventor: Dong-Wook Jang
  • Patent number: 9532324
    Abstract: A communication device and a communication scheme judgment method that enable reception of frames of different communication schemes without setting a common synchronization signal in the frames for each communication scheme. A signal including synchronization information corresponding to a communication scheme is receivable via a frequency band within which a frequency band of a channel corresponding to a first communication scheme overlaps with at least a portion of a frequency band of a channel corresponding to a second communication scheme.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: December 27, 2016
    Inventors: Yosuke Ukita, Hiroshi Hayashino
  • Patent number: 9496755
    Abstract: This disclosure provides systems, methods, and apparatus for filtering of a rectifier in a wireless power receiver. In one aspect a wireless power receiver is provided. The wireless power receiver includes a rectifier circuit configured to provide direct-current (DC) based at least in part on a time-varying voltage generated via a wireless field provided from a wireless power transmitter. The wireless power receiver further includes a band-stop filter circuit configured to filter an output of the rectifier circuit and electrically isolate a capacitor from the rectifier circuit at an operating frequency.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: November 15, 2016
    Inventors: Zhen Ning Low, Sreenivas Kasturi, Xuanning Gao
  • Patent number: 9413432
    Abstract: Provided is a near field wireless communication apparatus that uses magnetic coupling and a method for operation of the apparatus, in which the magnetic coupling is used to transmit data or clock information with low power and high efficiency. A pulse generator of the near field wireless communication apparatus generates a pulse signal corresponding to transmission digital data to be transmitted. When the transmission digital data is “1,” the near field wireless communication apparatus modulates the data into the pulse signal and transmits the pulse signal. When the data is “0,” the near field wireless communication apparatus does not output the pulse.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: August 9, 2016
    Assignees: Samsung Electronics Co., Ltd, Korea Advanced Institute of Science and Technology
    Inventors: Jae-Young Huh, Hoi-Jun Yoo, Dong-Churl Kim, Kyu-Sub Kwak, Jea-Hyuck Lee, Hyun-Woo Cho, Tae-Hwan Roh, Un-Soo Ha
  • Patent number: 9379679
    Abstract: A self-oscillation frequency varying element for varying the self-oscillation frequency of a self-oscillation loop of a self-oscillating class-D amplifier is placed in the self-oscillation loop. Frequency comparison, cycle comparison, or phase comparison is performed between a self-oscillation signal of the self-oscillating class-D amplifier or a signal corresponding to the self-oscillation signal and a reference frequency signal having a prescribed reference frequency. Alternatively, information corresponding to a frequency or a cycle of a self-oscillation signal of the self-oscillating class-D amplifier or a signal corresponding to the self-oscillation signal is compared with information corresponding to a prescribed reference frequency or reference cycle.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: June 28, 2016
    Assignee: Yamaha Corporation
    Inventor: Masao Noro
  • Patent number: 9312816
    Abstract: A frequency and phase conversion circuit and wireless communication unit for supporting a plurality of different duty cycles is described. The frequency and phase conversion circuit comprises: a local oscillator module comprising a plurality of frequency conversion modules arranged to receive at least one input clock signal wherein a plurality of phases of the at least one input clock signal are selectable to support a plurality of different duty cycle clock signals; and at least one frequency conversion module comprising a plurality of mixer arrangements configured to receive at least one baseband input signal and the selected plurality of phases of the at least one input clock signal and output a frequency and phase converted representation of the at least one baseband input signal, wherein at least one of the plurality of mixer arrangements is re-used in a plurality of the selectable supportable duty cycles.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: April 12, 2016
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Neric Fong, Siu-Chuang Ivan Lu
  • Patent number: 8665014
    Abstract: An I/Q demodulation apparatus and method with phase scanning are provided. The demodulation apparatus includes a ring oscillator, a first latch unit, a decoding unit, a counter unit, a second latch unit, a first arithmetical unit and a second arithmetical unit. The first latch unit samples phase signals outputted from the ring oscillator. The decoding unit decodes the output of the first latch unit to correspondingly generate fine code of a first, a second, a third and a fourth codes. The counter unit counts the phase signals. The second latch unit samples the output of the counter unit to correspondingly generate coarse code of the first, the second, the third and the fourth codes. The first arithmetical unit performs an addition/subtraction operation by using the first code and the second code. The second arithmetical unit performs the addition/subtraction operation by using the third code and the fourth code.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: March 4, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Huan-Ke Chiu, Jia-Hung Peng
  • Patent number: 8324963
    Abstract: In one embodiment, a circuit provides two quadrature components, I and Q, from a received modulated signal, from three mutually phase-shifted components of the received signal. The circuit can demodulate three mutually phase-shifted components of a baseband signal, in order to provide two quadrature demodulation components. The circuit includes three circuit inputs, each designed to received said three components, respectively. The circuit further includes a first and second adder circuit. The circuit also includes a bank of weighting circuits linked, at input, to the three circuit inputs and linked, at output, to the inputs of the first and second adder circuits so as to transmit to each adder input, with a determined weighting, a particular one of said three components, the weightings being chosen so that the first and second adder circuits provide said two quadrature demodulation components.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: December 4, 2012
    Assignee: Groupe des Ecoles des Telecommunications—Ecole Nationale Superieure des Telecommunications
    Inventors: Bernard Huyart, Kaïs Mabrouk
  • Patent number: 8269569
    Abstract: A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: September 18, 2012
    Assignee: Advantest Corporation
    Inventors: Daisuke Watanabe, Toshiyuki Okayasu
  • Patent number: 8237494
    Abstract: The determination of the signal modulation format for a channel is an important aspect of the operation of a signal receiver. A method (700) is described including the steps of receiving (710) a signal, comparing (720) a sample of the received signal to a first threshold value and a second threshold value, creating (720) a signal profile based on the comparison, and selecting (750) a modulation format for the received signal based on the signal profile. An apparatus (500) is also described including a ring counter (510) that receives a sample of an input signal, compares the sample to a first threshold value and a second threshold value, and creates a signal profile for the input signal, a signal profiler (550) that compares the signal profile for the input signal to at least two reference profiles, and a detector (560) that determines a modulation format for the input signal based on the comparison in the signal profiler (550).
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: August 7, 2012
    Assignee: Thomson Licensing
    Inventors: Aaron Reel Bouillet, Mark Francis Rumreich
  • Patent number: 8170149
    Abstract: An OFDM receiver apparatus receives an OFDM signal including a plurality of DBPSK signals transmitting identical information. An extraction unit extracts the plurality of DBPSK signals from the OFDM signal. A phase difference calculation unit calculates a phase difference between symbols of each of the plurality of extracted DBPSK signals. An accumulation unit accumulates the plurality of phase differences. A decision unit decides data transmitted by the DBPSK signals on the basis of an accumulation result.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: May 1, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoto Adachi
  • Patent number: 8159288
    Abstract: A low power BPSK demodulator having a simple architecture, compact design and reliable is provided. The BPSK demodulator includes a first branch (210) having a first mixer (212) and a first low pass filter (214), a second branch (220) coupled to the first branch at the output of the first low pass filter (214) and input of the first mixer (212) and having a second mixer (222), and a third branch (230) coupled to the second branch at the input and output of the second mixer (222) and having a third mixer (232) a second low pass filter (234) and a voltage control oscillator (236), wherein the third branch and the second branch form a charge pumped based phase lock loop that locks onto a carrier frequency of the BPSK demodulator.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: April 17, 2012
    Assignee: Tufts University
    Inventors: Zhenying Luo, Sameer Sonkusale
  • Patent number: 7994851
    Abstract: A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: August 9, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Jin Byun, Jae Hoon Shim, Hyun Kyu Yu
  • Patent number: 7911266
    Abstract: A low complexity and low power phase shift keying demodulator structure includes a digitizer, a phase-transition-independent carrier clock extractor, a binary correlater, a delay element, and a sampler. The digitizer digitizes a BPSK signal for an output waveform. The phase-transition-independent carrier clock extractor detects the phase transition on the output of the digitizer and produces a carrier clock signal. The binary correlater has correlated processes to the output signal of the digitizer and carrier clock signal obtained from the phase-transition-independent carrier clock extractor. The sampler samples the signal from the binary correlater according to the signal from the delay element in order to finish the demodulation with only a small capacitance.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: March 22, 2011
    Assignee: National Central University
    Inventors: Cihun-Siyong Gong, Muh-Tian Shiue, Kai-Wen Yao
  • Patent number: 7697637
    Abstract: A demodulation circuit can perform a capturing operation although a frequency error is large. A phase comparator out puts a predetermined value other than 0 as a determination result of a phase error when a phase error of a carrier wave is large and a signal point is located at a predetermined position. A loop filter outputs a negative minimum value to an integrator when an integrated value of a determination result reaches a positive maximum value of a limiter. Thus, when a phase error is large, a value changing from a negative minimum value to a positive maximum value is output from the loop filter, thereby realizing a broad synchronous capture range.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: April 13, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tatsuaki Kitta, Takanori Iwamatsu
  • Patent number: 7671670
    Abstract: The invention relates to a device for demodulating an input signal containing information being conveyed by phase modulation of a carrier wave. A transmitter generates a signal controlling a phase variation in the carrier wave, for each symbol having N cycles, N being an integer strictly greater than 1. The phase variation stretches on the receiver side over n cycles, n being an integer greater than 1 and less than N. The device generates a single pulse for each symbol received suited to generate the leading edge of the pulse corresponding to the symbol considered after a constant duration from the moment the symbol considered starts; and generates the trailing edge of the pulse considered at a moment the phase shift corresponding to the symbol considered has to be measured. Conversion means generate an output signal with a voltage varying as a function of the duration of the pulse produced.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: March 2, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Gilles Masson, Jacques Reverdy
  • Publication number: 20090256629
    Abstract: A phase detector, including a sampling device, a comparing device, and an output device, is provided. The sampling device samples a data signal according to a plurality of clock signals, so as to provide a plurality of corresponding sampling values. The clock signals have the same frequency and different phases. The comparing device is coupled to the sampling device, and provides a plurality of corresponding comparison values according to comparison results of each of the sampling values comparing with the next sampling value. The output device is coupled to the comparing device, and outputs two of the comparison values in response to edges of the clock signals. The two outputted comparison values serve as a first instruction signal and a second instruction signal respectively. The first and the second instruction signals are referred to in controlling the frequency and the phase of the foregoing clock signals.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 15, 2009
    Inventors: Yu-Hsin Tseng, Wen-Ching Hsiung
  • Patent number: 7564934
    Abstract: The DSP MSP invention provides an implementation of programmable algorithms for analyzing a very wide range of low and high frequency wave-forms. The DSP MSP comprises a synchronous sequential processor (SSP) for real time capturing and processing of in-coming wave-form including a programmable computing unit (PCU) for controlling SSP operations and supporting adaptive signal analysis algorithms. The DSP MSP further comprises a Sequential Data Recovery from Multi Sampled Phase (SDR MSP) for a receiver of an optical wave-form.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: July 21, 2009
    Inventor: John W. Bogdan
  • Patent number: 7514993
    Abstract: A method and apparatus for the demodulation, filtering, decimation and optional voltage multiplication of modulated signals to produce in-phase and quadrature outputs using a discrete time architecture.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: April 7, 2009
    Inventor: Alon Konchitsky
  • Patent number: 7508889
    Abstract: A system for implementing the soft decision of a 3-chip differential binary phase shift keying (DBPSK) optical signal using digital components. Pair-wise comparisons of three differentially detected signals are performed and analyzed by digital logic which determines the most likely sequence of data. In a first variant, pairs of adjacent data bits are detected simultaneously, whereas in a second variant, data bits are detected individually. The digital logic can be implemented using conventional logic gates.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: March 24, 2009
    Assignee: Alcatel-Lucent USA Inc.
    Inventor: Xiang Liu
  • Publication number: 20080088367
    Abstract: The invention provides a semiconductor device that generates a clock signal with a fixed pulse width from a carrier. The invention also provides a semiconductor device where data can be obtained accurately from a carrier using a clock signal with a fixed pulse width. Further, the invention provides a semiconductor device that has a simpler circuit configuration and a smaller scale, and consumes less power as compared to the PLL circuit. According to the invention, a signal obtained by dividing a carrier including 100% modulation is not used as a clock signal, and a correction circuit is used to generate a clock signal using a demodulated signal and a signal obtained by dividing the carrier including 100% modulation. According to the invention having such a configuration, a clock signal with a fixed pulse width can be generated.
    Type: Application
    Filed: October 5, 2005
    Publication date: April 17, 2008
    Inventor: Tomoaki Atsumi
  • Patent number: 7148743
    Abstract: A demodulation device is provided that includes first and second power control circuits and demodulation circuits. The first power control circuit keeps the amplitude of a modulated input signal constant, and the demodulation circuits applying a demodulation processing to the input signal. The second input signal power control circuit generates a control signal having a signal present state representing detection of the presence of the input signal and a signal disappeared state representing detection of disappearance of the input signal. The demodulation device further includes means for deactivating the demodulation circuits when the control signal changes from the signal present state to the signal disappeared state, and for activating the demodulation circuits when the control signal changes from the signal disappeared state to the signal present state so as to enable a fast restart of the demodulation processing.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: December 12, 2006
    Assignee: STMicroelectronics SA
    Inventors: Bruno Paille, Mariano Bona
  • Patent number: 6879646
    Abstract: A QAM demodulator comprises a timing synchronizer whose output is supplied via an adaptive equalizer to a carrier synchronizer, all of which are controlled by a controller. The timing synchronizer resamples the incoming signal in the digital domain with a sampling period which, during an acquisition mode, sweeps between limit values at different rates. The controller begins an acquisition cycle at the highest rate and monotonically lowers the sweep rate until timing lock is achieved. The sampling rate is then fixed at the correct value. Similarly, the controller sweeps the local oscillator of a phase locked loop in the carrier synchronizer initially at a highest rate and at progressively lower rates until the carrier synchronizer locks to the phase of the incoming signal.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: April 12, 2005
    Assignee: Zarlink Semiconductor Limited
    Inventor: Bernard Arambepola
  • Patent number: 6839389
    Abstract: One embodiment of the present invention includes a gating circuit, a demultiplexer, and an integrator. The gating circuit gates an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock. The demultiplexer demultiplexes the gated input sample to generate in-phase and quadrature samples. The integrator integrates the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively. Each of the in-phase and quadrature decimated samples having K bits.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: January 4, 2005
    Assignee: PRI Research & Development Corp.
    Inventors: Alireza Mehrnia, Kaveh Shakeri
  • Patent number: 6459743
    Abstract: A radio frequency signal is received by using a sigma-delta analog-to-digital converter to sample the radio frequency signal at a sampling rate and to generate therefrom 1-bit digital samples representing a digital intermediate frequency signal. The intermediate frequency signal is demodulated to generate in-phase and quadrature samples. Demodulation may be performed by generating a first mixed signal by combining the 1-bit digital samples representing the intermediate frequency signal with a first sequence representing a cosine mixing signal; generating a second mixed signal by combining the 1-bit digital samples representing the intermediate frequency signal with a second sequence representing a sine mixing signal; and decimating the first and second mixed signals to generate the in-phase and quadrature samples.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: October 1, 2002
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Dietmar Lipka
  • Patent number: 6246281
    Abstract: An absolute phasing circuit having a simplified phase rotating means constituting a remapper. The phase rotation angle of a receiving phase for the signal point arrangement on the transmitting side is detected, and a phase rotation signal RT (3) based on the detected phase rotation angle is outputted from a frame synchronization circuit (2). Phases of baseband demodulated signals I and Q through a demodulator circuit (1) are rotated by 45° through a ROM (3) constituting the remapper. A logic conversion circuit (4), receiving the baseband demodulated signals I and Q through the demodulator circuit (1) and phase rotated baseband demodulated signals i and q from the ROM (3), performs inversion of code and exchange of the baseband demodulated signals selectively and delivers a baseband demodulated signal matched with the signal point arrangement on the transmitting side.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: June 12, 2001
    Assignee: Kabushiki Kaisha Kenwood
    Inventors: Akihiro Horii, Kenichi Shiraishi
  • Patent number: 6236263
    Abstract: A demodulator with a cross polarization interference canceling function for canceling interference of cross polarization in the main polarization includes a demodulating unit for demodulating a baseband signal of the main polarization, a phase control unit which controls the phase of an interference signal, which is a baseband signal of cross polarization, based upon an error in the demodulated signal, and an interference cancellation unit which cancels an interference signal component from the demodulated signal of the main polarization.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: May 22, 2001
    Assignee: Fujitsu Limited
    Inventor: Takanori Iwamatsu
  • Patent number: 6163208
    Abstract: A phase shift keyed carrier recovery and demodulator circuit which includes a phase detector and subsequent feedback control loop circuitry which maintains an initial phase relationship. By comparing an incoming phase modulated carrier with the multiple phase outputs of a local oscillator, the circuit is able to generate a correcting signal which allows coherent phase tracking of the incoming phase modulated carrier. The phase detector produces a correction signal which allows the circuit to phase lock any two sequential phases of the locally generated phase outputs to phase positions on either side of the phase of the incoming phase modulated carrier. Once the circuit has obtained carrier phase lock, the multiple phases produced by the local oscillator will remain fixed (without phase change) relative to the initial detected phase of the incoming phase modulated carrier.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: December 19, 2000
    Assignee: Ga-Tek Inc.
    Inventors: Craig L. Christensen, Kenneth L. Reinhard, Andrei Rudolfovich Petrov
  • Patent number: 6140869
    Abstract: A device for demodulating a binary signal having a predetermined carrier frequency and phase-modulated by encoded pulses. The device includes a phase-locked loop circuit having a phase comparator followed by a low-pass filter and a voltage-controlled oscillator, which is voltage-controlled by the output of the filter. The voltage-controlled oscillator outputs a binary signal that is synchronous with the modulated signal and at a frequency N times the carrier frequency. The phase-locked loop circuit also includes a divider that divides by N the output signal of the oscillator and supplies the divided signal to one input of the phase comparator. Thus, a binary signal synchronous with the modulated signal and having a frequency equal to the carrier frequency is supplied to one input of the phase comparator. The other input of the phase comparator receives the modulated signal.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: October 31, 2000
    Assignee: STMicroelectronics S.A.
    Inventor: Cyril Troise
  • Patent number: 6133785
    Abstract: A receiver includes a demodulator and a false carrier lock detector circuit for a quadrature amplitude modulated (QAM) signal. The demodulator includes a controllable oscillator and an offset frequency generator for generating an offset frequency for the controllable oscillator to lock to a carrier of the QAM signal. The demodulator is susceptible to false carrier locking responsive to the offset frequency being substantially equal to the symbol rate divided by four or an integer multiple thereof. The receiver further includes the false carrier lock detector circuit including a first detector for detecting consecutive symbols spaced apart, and a second detector for determining whether an intervening sample between the consecutive symbols is outside a predetermined distance from the origin. The first and second detectors cooperate to determine false carrier locking based upon the intervening sample being outside a predetermined distance from the origin.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: October 17, 2000
    Assignee: Harris Corporation
    Inventor: Richard Bourdeau
  • Patent number: 6130577
    Abstract: In a digital demodulator for phase modulated signals, logical values of a waveform-shaped phase-modulated signal are sampled based on a clock signal having a period that stands in integer ratio relationship to a carrier period of the modulated signal and thereafter subjected to serial/parallel conversion for each predetermined interval, whereby a logical pattern of a digital code train subjected to the serial/parallel conversion is analyzed. As a result, phase information required to demodulate digital data can be logically detected.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: October 10, 2000
    Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Yuko Tamba, Taiji Kondou, Katsuhiro Furukawa, Yukihito Ishihara
  • Patent number: 6075827
    Abstract: A DQPSK mapping circuit is disclosed which comprises: a parallel decoding circuit having inputs for decoding first to 2Nth bits of input data and one symbol period prior I and Q data which are prior by one symbol period from the present decoding cycle thereof through the inputs and outputting serial first to Nth I and Q data of the present decoding period in parallel, N is a natural number; and a FF circuit for supplying the Nth I and Q data to the inputs as the one symbol period prior I and Q data in the succeeding decoding cycle of the parallel decoding circuit. The parallel decoding circuit may comprise first to Nth decoders, an Mth decoder out of the first to Nth decoders decoding 2Mth bit and (2M-1)th bits of the input data and outputs of (M-1)th decoder, M being a natural number and M.ltoreq.N, wherein the first decoder decodes the one symbol period prior I and Q data and the first and second bits of the input data.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: June 13, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuo Shida, Katsuhiko Hiramatsu
  • Patent number: 6075408
    Abstract: A method and an apparatus for generating an error estimate as input for an error recovery loop of a demodulator which receives an offset quadrature phase shift keyed (OQPSK) signal having a symbol interval. The method comprises the following operations: (a) receiving at least four consecutive complex samples z.sub.-1/2, z.sub.0, z.sub.1/2 and z.sub.1 obtained by sampling the OQPSK signal at half the symbol interval; and (b) computing the error estimate based on the complex samples z.sub.-.sub.1/2, z.sub.0, z.sub.1/2 and z.sub.1.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: June 13, 2000
    Assignee: International Business Machines Corp.
    Inventors: Johan Kullstam, Rahul Deshpande
  • Patent number: 6028475
    Abstract: Disclosed is a demodulating apparatus for preventing a reduction in reliability of demodulated data even if a signal point of a multi-level QAM signal is detected, because of influence from fading or noises, in a position where such a signal is not normally existent. To this end, a modulated signal modulated by a multi-level QAM modulation system is orthogonally detected, and analog signals of I and Q channels placed in an orthogonal relationship with each other are outputted. By an identification device, the analog demodulated signals are digitized and then outputted as digital demodulated signals of I and Q channels. If a signal point outside a normal signal point arrangement is detected among the outputs, a digital demodulated signal within a normal signal point arrangement is substituted for the detected signal and then original code data is reproduced.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: February 22, 2000
    Assignee: NEC Corporation
    Inventor: Masahiro Kikuchi
  • Patent number: 5977821
    Abstract: In a digital radio communication apparatus which receives PSK modulated signal, a plurality of items of quantized data are sampled at a plurality of points including a central point, which corresponds to one of each rising edge or each decaying edge of a reproduction clock signal, points before the central point and points after the central point. The sampled plurality of items of quantized data are combined so that combined phase data is obtained for each symbol.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: November 2, 1999
    Assignee: Fujitsu Limited
    Inventor: Manabu Shibata
  • Patent number: 5977820
    Abstract: The presence or absence of a clock component is detected for an input signal. If the input signal does not comprise a clock component, the operation of a computing circuit is halted, thereby further improving the accuracy of phase estimation. A signal generating circuit produces a twiddle factor for DFT. A DFT circuit performs discrete Fourier transform on an input signal for a predetermined number of symbols based on the twiddle factor for DFT. A pattern detecting circuit examines the input signal for its pattern based on the output from the DFT circuit. An averaging filter turns on or off the operation of the subsequent averaging filter according to the detected pattern, and averages the outputs from the DFT circuit to remove a noise component.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: November 2, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasushi Sogabe, Fumio Ishizu, Keishi Murakami
  • Patent number: 5945875
    Abstract: A .pi./n shift PSK demodulator of this invention is formed with a digital logical means through the following method. XOR4 calculates the ex-OR operation between the present sample through .pi./4 shift QPSK output from SH2 and the previous one output from SH1. Accumulating 1 among the outputs from XOR4 in the first operation means 5 and multiplying it by .pi./8 obtains the absolute phase difference between the present and the previous symbols. The former or latter four bits from SH1 are subtracted from the corresponding former or latter four bits from SH2, and the result of each bit is summed and its sign is added to the absolute phase data in sign addition means 10. After the phase offset is subtracted from the outputs from 10, it is demodulated into the original one in judgment circuit 13.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: August 31, 1999
    Assignee: Yozan Inc.
    Inventors: Xuping Zhou, Guoliang Shou, Changming Zhou
  • Patent number: 5942937
    Abstract: A signal detection circuit employs a delay line with edge detection logic for capturing and buffering timing information about an input signal. A plurality of comparators for comparing the input signal to different reference potentials capture amplitude information in the input signal launching bits into respective delay lines. Preferably, each delay line includes a counter for counting detected bit edges.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: August 24, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Russell Bell
  • Patent number: 5933053
    Abstract: A burst demodulator prevents transmission efficiency from being lowered, and a dynamic range of an input strength from being narrowed, by providing a stable frame signal even if the reaction is rapid against the input and the input strength is low. A logarithm amplifier outputs an electric power strength of a modulated input signal as a logarithm value, and an integrator smooths the output of the logarithm amplifier and outputs the smoothed output as an RSSI. The comparator compares the RSSI with the appropriate reference value REF while including some margin within the noise level, and outputs the frame signal of an `LO` state when the RSSI is lower than the REF, that is, during the non-signal zone, of an `HI` state when the RSSI is higher than the REF, that is, during the signal zone. The period of the comparator output continuously remaining in the `LO` state cannot exceed one clock period even if the comparator output flutters within one time slot.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: August 3, 1999
    Assignee: NEC Corporation
    Inventor: Takaya Iemura
  • Patent number: 5892797
    Abstract: A data and clock recovery circuit includes a front end circuit for receiving a data signal encoded with a Manchester or other bi-phase level code having a sequence of bit frames, and for outputting a recovered data signal and a recovered clock signal in accordance with transitions in the data signal that overlap with a window signal. A window generation circuit generates the window signal in accordance with a delay control signal, and includes circuitry that delays and transforms the recovered clock signal into the window signal. A delay control circuit generates and adjusts the delay control signal. A phase comparison circuit compares the recovered clock signal with leading and lagging portions of the window signal, and generates signals that adjust the delay control signal when the recovered clock signal overlaps with either of the leading and lagging portions of the signal.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: April 6, 1999
    Assignee: Jay Deng
    Inventor: Jay Jie Deng
  • Patent number: 5808509
    Abstract: In a quadrature receiver for phase and/or frequency modulated signals an intermediate phase signal is quantized to produce a quantized phase signal. The receiver includes a demodulator in which pulses are generated from the quantized phase signal and it is determined whether two successive pulses have different polarities, and if so, a reconstructed baseband signal transition is produced at a predetermined reconstruction instant between the two successive pulses. The reconstruction instant is chosen in the middle between two successive pulses for FSK modulation, and it is chosen at different positions between the two pulses for other types of modulation, such as GMSK or multi-level FSK.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: September 15, 1998
    Assignee: U.S. Philips Corporation
    Inventors: Petrus G. M. Baltus, Augustus J. E. M. Janssen
  • Patent number: 5805018
    Abstract: A high-speed demodulating method of burst data capable of performing demodulation process at high speed in a single hardware structure. An input signal digitally modulated is taken in into an input unit to be sampled and latched therein by a sampling clock from a controller, and a modulation signal from the input unit is taken in into either a first demodulator or a second demodulator for each one burst data depending on the timing of a first control signal or a second control signal output by the controller, respectively, and demodulated, and a first demodulation signal produced from the first demodulator or a second demodulation signal produced from the second demodulator is taken in into an output unit by a third control signal output by the controller, and in the output unit, the first demodulation signal or the second demodulation signal is latched by a latch signal of the controller and supplied as an output signal.
    Type: Grant
    Filed: May 14, 1997
    Date of Patent: September 8, 1998
    Assignee: Ando Electric Co., Ltd.
    Inventor: Yousuke Harima