Abstract: A method of detecting normality of a PWM signal, wherein an error in a pulse-width modulation (PWM) signal is detected using four different self-test logics, and information obtained by categorizing results of detection into failure modes is transmitted to a vehicle component controller, so that the consistency of the PWM signal is determined, a signal safety means is secured, and further, safety standard requirements of the automobile field are satisfied.

Abstract: A signal generation device includes a first timer to output an interrupt signal at a predetermined cycle, a second timer to output a first pulse signal and a second pulse signal, a third timer to count a number of edges of the first pulse signal and the second pulse signal, and a processor configured or programmed to perform interrupt processing to control an output mode of the second timer every time the interrupt signal occurs. When the interrupt frequency is equal to an initial value at the start of the interrupt processing, the processor is configured or programmed to perform predetermined short-period processing after performing predetermined long-period processing. When the interrupt frequency is not equal to the initial value, the processor is configured or programmed to perform the short-period processing without performing the long-period processing. The processor execute is configured or programmed to angle acquisition processing and function calculation processing as the long-period processing.

Abstract: A precharge control apparatus starts precharge of a capacitor. The precharge is determined to be completed when a set time has elapsed since a voltage difference between a battery voltage and a capacitor voltage detected by a voltage sensor becomes equal to or less than a set voltage. The set voltage is based on a maximum error obtained by adding maximum values of detection errors of the battery voltage and capacitor voltage by the voltage sensor. The set time is based on a time from when the voltage difference becomes twice the maximum error to when the voltage difference becomes equal to or less than a withstand voltage of a main contactor, under states where the precharge causes the capacitor voltage to increase with a time constant when a resistance value of a resistor and a capacitance of the capacitor each are largest within an allowable error.

Abstract: A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.

Abstract: A simple, fast, easily designed circuit for demodulating a PWM signal produces an output signal indicating a duty cycle of a received PWM signal. The circuit may include a low pass filter circuit to receive a Pulse Width Modulated (PWM) signal and produce a triangular signal, a track-and-hold circuit to receive the PWM signal and the triangular signal and produce a minimum and maximum signals corresponding to minimum and maximum values of the triangular signal during each cycle of the PWM signal, and an averaging circuit to receive the minimum signal and the maximum signal and produce, by averaging the values of the minimum signal and the maximum signal, the output signal.

Abstract: The present disclosure provides a device for controlling a position based on a programmable logic controller (PLC), the device comprising: a motor driving module; an input module; and a control module, wherein the control module includes: a profile creation unit configured for creating the position profile based on the position command when a first position calculation interrupt is generated in a first position control period; a pulse calculation unit configured for calculating a number of outputs of the driving pulse to be output in a second position control period following the first position control period based on the position profile; and a driving controller configured for outputting the driving pulse having the number of outputs calculated by the pulse calculation unit to the motor driving module when a second position calculation interrupt notifying a start time-point of the second position control period is generated.

Abstract: Described embodiments provide circuits, systems and methods for digitally demodulating a pulse-width modulated (PWM) signal in a motor control system. An electronic circuit of the motor control system includes an input to receive a speed demand signal that is a PWM signal having a duty cycle associated with a requested speed of a motor. A PWM demodulator demodulates the PWM signal and generates an N-bit digital speed value representative of the requested speed of the motor, where N is a positive integer. A motor driver generates, based at least in part upon the N-bit digital speed value, one or more control signals to operate the motor.

Abstract: A system and method for streaming media and, more particularly, to a system and method for active transcoding of content in a distributed system. The method includes receiving a file having predetermined parameters and sizing the file up to an optimal packet size according to a logarithmic scheme. The optimal packet size is a largest packet size. In further aspects, the method also includes providing a computer infrastructure operable to perform the steps herein. The system includes a media service, rules engine, log based job creator and a stream constructor. A computer infrastructure having computer readable medium to perform the processes described herein is also provided.

Abstract: An energy-efficient system for measurement of analog signals including one or more measuring units. Each measuring unit has a measuring probe which signal is processed by a modulator. All measuring units have identical modulators selected from the Time Encoding Machine family: Asynchronous Sigma Delta Modulator, Integrate And Fire Modulator and Integral Pulse Frequency Modulator. A signal from the modulator is processed by a delay circuit from which is optionally fed back to the modulator. Signals from the delay circuit and modulator are used to trigger a UWB pulse generator, which is optionally amplified and transmitted via transmission line or antenna. The delay circuit uniquely characterizes the measuring unit and enables the receiving unit to separate received signals from plurality of measuring units signals sent in an unsynchronized manner. The invention is useful for long term acquisition of analog signals, especially time varying signals such as biological signals.

Abstract: A pulse width modulation (PWM) data recovery device includes a differential-to-single (DTS) circuit configured to generate a PWM bit using a differential data signal including a differential positive data signal and a differential negative data signal, and an alignment buffer configured to activate a bit lock signal by detecting a synch pattern, recover symbol data by receiving the PWM bit in synchronization with one of the differential positive data signal and the differential negative data signal, and transmit the symbol data in synchronization with a reference clock.

Abstract: A circuit for use with PWM signal having first pulse and a second pulse, wherein the first pulse has a period and a first duty cycle, and the second pulse has the period and a second duty cycle. The period has clock information therein, the first duty cycle has first data information therein, and the second duty cycle has second data information therein. The circuit includes a first integrating component and a second integrating component. The first integrating component can generate a first voltage corresponding to the first duty cycle and a second voltage corresponding to the first duty cycle. The second integrating component can generate a third voltage corresponding to the second duty cycle and a fourth voltage corresponding to the second duty cycle.

Abstract: A device for detecting a PWM wave, comprising: a PWM wave generating module, configured to generate the PWM wave; a detecting module coupled to the PWM wave generating module, configured to receive the PWM wave and to determine an electric level of the PWM wave; a timer coupled to the detecting module, configured to start a counting when the detecting module receives the PWM wave, and to interrupt the counting when the counting reaches a predetermined value, the detecting module determining whether the electric level of the PWM wave is a high electric level or a low electric level when the counting is interrupted; and a calculating module coupled to the detecting module, configured to calculate a duty ratio of the PWM wave based on a number of high electric level and a number of low electric level of the PWM wave determined within one period of the PWM wave.

Abstract: A PWM receiver circuit receives and demodulates pulse width modulated (PWM) data signals without requiring synchronization such that no synchronization preamble need be provided with the PWM data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a PLL, counter or other circuitry to the PWM data signal. Furthermore, the PWM receiver circuit operates in view of or is “tolerant” to jitter in the frequency of the PWM signal and also to a relatively wide range of intentional variation in the frequency. Interleaved operation of parallel PWM receiver circuits are utilized in some embodiments. In one embodiment currents are integrated during low and high portions of the duty cycle of the PWM data signal and the difference in the respective voltages generated through such integration used to demodulate the PWM data signal.

Abstract: A pulse signal receiving apparatus may include a reception unit that receives a pulse signal modulated by a double-edge modulation scheme, a measurement unit that measures an edge interval of the pulse signal, which has been received by the reception unit, a detection unit that detects a deviation of the edge interval, which has been measured by the measurement unit, for a pulse-width reference value indicating a reference value of a width of the pulse signal, a correction unit that corrects the edge interval, which is to be measured next by the measurement unit, by using the deviation, which has been detected by the detection unit, and a decoding unit that decodes the pulse signal, of which the edge interval has been corrected by the correction unit, so as to output a digital signal.

Abstract: A modulator, a demodulator and a modulator-demodulator are provided. A modulator includes a first intermediate signal processing path adapted to route a first intermediate signal; a second intermediate signal processing path adapted to route a second intermediate signal; a first amplifier coupled into the first intermediate signal processing path; a second amplifier coupled into the second intermediate signal processing path; and a chopper circuit coupled into the first intermediate signal processing path; wherein the chopper circuit is adapted to process the first intermediate signal in dependence on first baseband data; wherein the first amplifier is adapted to amplify the first intermediate signal processed by the chopper circuit in dependence on second baseband data; and wherein the second amplifier is adapted to amplify the second intermediate signal in dependence on the second baseband data.

Abstract: A digital demodulation circuit amplifies a received signal of an intermediate frequency with a variable gain control amplifier so as to convert it into a baseband signal, which is separated into a common-mode component and an orthogonal component. A first gain control voltage is generated based on the common-mode component and the orthogonal component. Additionally, a temperature correction value is generated by smoothing a pulse-width modulation signal, having a pulse width corresponding to ambient temperature, and by adding a predetermined gain and an offset thereto. A second gain control voltage is generated by adding the temperature correction value to the first gain control voltage. The variable gain control amplifier amplifies a received signal with the second gain control voltage. Thus, it is possible to achieve a temperature compensation function and an automatic gain control function in the digital demodulation circuit with a simple circuit configuration.

Abstract: A pulse width modulated (PWM) signal is received and, over a time interval of the PWM signal, a first count is incremented when the PWM signal is at a first level, and a second count is incremented when the PWM signal is at a second level. At the end of time interval the first count is compared to the second count and, based on the comparison, a decoded bit is generated. Optionally, incrementing the first count is by enabling a first oscillator that increments a first counter, and incrementing the second count is by enabling a second oscillator that increments a second counter.

Abstract: An object is to provide a demodulation circuit having a sufficient demodulation ability. Another object is to provide an RFID tag which uses a demodulation circuit having a sufficient demodulation ability. A material which enables a reverse current to be small enough, for example, an oxide semiconductor material, which is a wide bandgap semiconductor, is used in part of a transistor included in a demodulation circuit. By using the semiconductor material which enables a reverse current of a transistor to be small enough, a sufficient demodulation ability can be secured even when an electromagnetic wave having a high amplitude is received.

Abstract: Apparatus and methods are described that enable concurrent transmission of multiple data signals including clock, synchronization, and power over a single-wire bus between a master device and one or more slave devices. A first transmission channel from the master device to the slave device may modulate the width of periodic pulses between a first voltage level and a second voltage level with respect to a reference potential. A second transmission channel may modulate the amplitude of at least one of the first and second voltage levels to at least one third voltage level. Concurrent communications between a master device and one or more slave devices over a single-wire bus can be achieved.

Abstract: A pulse width modulated (PWM) signal is received and, over a time interval of the PWM signal, a first count is incremented when the PWM signal is at a first level, and a second count is incremented when the PWM signal is at a second level. At the end of time interval the first count is compared to the second count and, based on the comparison, a decoded bit is generated. Optionally, incrementing the first count is by enabling a first oscillator that increments a first counter, and incrementing the second count is by enabling a second oscillator that increments a second counter.

Abstract: A modulator using a polynomial interpolator is described herein. In a simple circuit implementation of the modulator, coefficients of a representative polynomial are generated with interpolation filters in the polynomial interpolator. Crossing points may be identified for each sampling period by incorporating a virtual carrier waveform with the representative polynomial to generate a switching output control. Among other applications, the described modulator may be used in a Class-D amplifier. The described implementations may further confer benefits such as micro-power low voltage operation, low sampling rate, and low harmonic distortion.

Abstract: Systems and methods for the demodulation of pulse edge modulated signals for communications systems which are useful in body implanted electronics. A pulse edge modulated signal is generated by retarding or advancing each pulse edge of a carrier to be modulated relative to its original position in time, depending on the state of the digital bit to be modulated on that edge. Each modulated edge of a pulse edge modulated signal is demodulated by determining the position in time of the modulated edge relative to the original respective position of the modulated edge prior to modulation.

Abstract: An object is to provide a demodulation circuit having a sufficient demodulation ability. Another object is to provide an RFID tag which uses a demodulation circuit having a sufficient demodulation ability. A material which enables a reverse current to be small enough, for example, an oxide semiconductor material, which is a wide bandgap semiconductor, is used in part of a transistor included in a demodulation circuit. By using the semiconductor material which enables a reverse current of a transistor to be small enough, a sufficient demodulation ability can be secured even when an electromagnetic wave having a high amplitude is received.

Abstract: A variable delay circuit delays a carrier signal having a predetermined frequency, and outputs a modulated signal. A delay setting unit sets a delay period for the variable delay circuit according to a data signal to be modulated. The delay setting unit assigns each symbol in the data signal to any one of positive edges and negative edges in the carrier signal, and sets a delay period for the variable delay circuit at the timing at which a positive edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the positive edge. Furthermore, the delay setting unit sets a delay period for the variable delay circuit at the timing at which a negative edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the negative edge.

Abstract: The invention relates to a method for adjusting a pulse detection threshold consisting in detecting a pulse when the edge of said pulse envelop crosses the threshold, in allocating (A) a staring value (TH0) to the threshold and in adjusting (B1) the threshold (TH) in such a way that the number of pulses detected on at least one observation window (OWj) satisfies a predetermined criterion in a determined time.

Abstract: A method and apparatus is described for a time modulated signal. A cosine function is used as the basis for the signal with time intervals at the maximum and minimum values of the cosine function defining the encoded data. The received waveform is twice differentiated to provide a cosine function from which zero crossings are detected and the time intervals determined.

Abstract: A transmitter portion 14 includes a control circuit 32, a driver circuit 33, and a wave detector circuit 35. The control circuit 32 generates control signals Vp, Vn based on a pulsed transmission signal So. The driver circuit 33, which is supplied with a battery voltage Vb, generates an output signal Sa to be sent to an antenna 13 based on the control signals Vp, Vn. The wave detector circuit 35 outputs a detection signal Sk having a voltage proportional to the level of the output signal Sa (transmission power level). The control circuit 32 changes the pulse widths of the control signals Vp, Vn based on the voltage level of the detection signal Sk. As a result, electric power consumption is reduced and enlargement of an apparatus is suppressed while maintaining the transmission power level constant.

Abstract: Methods and systems for modulating a signal are described. A phase-modulated signal that includes a sequence of contiguous one-cycle sinusoidal waveforms having a frequency above 50 MHz is generated. The phases of the one-cycle sinusoidal waveforms correspond to symbols of a message signal. A bandwidth of the phase-modulated signal is reduced using a bandpass filter centered at the frequency of the contiguous one-cycle sinusoidal waveforms. The phase-modulated signal is wirelessly transmitted.

Abstract: A system for controlling the delay applied to one branch of a pulse width modulation amplifier. The delay typically incorporated whether input signal level is low and diminished when the input signal level increases. The system may be implemented using a switch, a level detector and a timer, which in conjunction determine whether the delay unit is included in the branch or bypassed. The system may also use a programmable delay that can adjust the period of delay applied or be programmed to operate as a pass-through where delay is no longer beneficial for providing high signal quality.

Abstract: The invention provides a semiconductor device that generates a clock signal with a fixed pulse width from a carrier. The invention also provides a semiconductor device where data can be obtained accurately from a carrier using a clock signal with a fixed pulse width. Further, the invention provides a semiconductor device that has a simpler circuit configuration and a smaller scale, and consumes less power as compared to the PLL circuit. According to the invention, a signal obtained by dividing a carrier including 100% modulation is not used as a clock signal, and a correction circuit is used to generate a clock signal using a demodulated signal and a signal obtained by dividing the carrier including 100% modulation. According to the invention having such a configuration, a clock signal with a fixed pulse width can be generated.

Abstract: In one embodiment, a method for a control interface includes: receiving a signal conveying bits of information over a single line; and for each bit of information, comparing the proportion of time that the signal on the single line is low versus the proportion of time that the signal on the single line is high for a respective bit period defined from one operative edge of the signal to the next operative edge of the signal in order to determine a logic value for that bit of information.

Abstract: A method and accompanying circuitry for asynchronous data demodulation uses sorted pulsewidth measurement based on an asynchronous clock. Lock-on of the data stream by such a system is accomplished by measured pulsewidth, rather than inferred frequency. The method broadly comprises the steps of measuring a temporal aspect of the asynchronous clock, and locking onto the data stream in accordance with the measured periods. In the preferred embodiment, the temporal aspect is a ratio of measured periods. Conveniently, a ratio of 2:1 may be used.

Abstract: A pulse width modulator for use in a digital amplifier, includes a pop noise reducer for reducing pop noise by controlling a width and a phase of a pulse of a PWM signal output from the pulse width modulator, wherein the pop noise reducer contains: a PWM pulse register for storing a width and a phase values of a pulse of the PWM signal; and a pulse generator for outputting the PWM signal according to the values stored in the PWM pulse register. The pulse width modulator reduces pop noise generated when power supply to a digital amplifier is started and interrupted.

Abstract: A demodulator for processing a PWM (pulse width modulation) signal includes a variable capacitor, a charging unit, a discharging unit, and a tuner. The charging and discharging units charge or discharge the variable capacitor depending on the PWM signal. The tuner determines a capacitance of the variable capacitor and a discharge current of the discharging unit for proper operation of the demodulator in various RF environments.

Abstract: In one embodiment, a method for a control interface includes: receiving a signal conveying bits of information over a single line; and for each bit of information, comparing the proportion of time that the signal on the single line is low versus the proportion of time that the signal on the single line is high for a respective bit period defined from one operative edge of the signal to the next operative edge of the signal in order to determine a logic value for that bit of information.

Abstract: The invention allows the detection and processing in a radio signal received by a receiver, of any signal of “pulsed” type present in radio signals applied to the input of a radiofrequency receiver, the receiver having an analogue/digital converter for performing the coding into digital on N bits of P successive samples of the analogue signal applied to the input of the receiver and a computer for processing the said digital signals, characterized in that on the basis of a histogram of the rate of occupancy of the digitized samples, graded in ranges Fx of amplitude-increasing sample levels, is determined, from among the ranges Fx, a range Fn onwards of which the total number of digitized samples Nnor contained in the ranges Fn and those below Fn is greater than or equal to a normality threshold Nn, Nn being a number predetermined as a function of the sensitivity of the detection of pulsed signals that one wishes to achieve.

Abstract: Systems and methods for evaluating a signal containing pulses received from a wireless computer peripheral device are provided. A received signal is analyzed to measure the strength of the received signal and determine whether sources of interference exist. Correction action is recommended based on the analysis of the received signal.

Abstract: Provided is a method to process a pulse width coded signal. the method includes digitizing a received pulse width coded signal and transforming the digitized signal to at least one of power domain and absolute value domain. The converting produces a converted signal. The method also includes estimating a signal power of the converted signal in a wide band filter to produce data representative of a first signal having first type signal shape properties and estimating a signal power of the converted signal in a narrow band filter to produce data representative of a second signal having second type signal shape properties. Finally, the first and second type data are compared to produce information representative of pulse width characteristics of the received signal.

Abstract: A dual phase pulse modulation (DPPM) decoder circuit processes a DPPM signal, which is in the form of a series of high and low pulses whose pulse widths represent successive groups of M data bits, so as to recover data carried by the signal. Each of the 2M possible data values of an M-bit group corresponds to one of 2M distinct pulse widths. Circuit blocks determine the width of each pulse by piping the DPPM signal through a short delay chain and inputting the delayed outputs and the non-delayed signal into AND logic gates, whose outputs are used to clock flip-flop registers. The registers are reset to a known state at the start of each signal pulse and toggled to an opposite state if clocked. The registered outputs are interpreted by logic to obtain the corresponding M-bit groups.

Abstract: A system and method for determining a minimum pulse width for a digital data stream is described herein. The minimum pulse width is used to infer the data rate for the digital data stream. A measuring cell is used to measure the pulse widths by utilizing RC time constants. The measuring cell comprises a capacitor whose voltage is related to the pulse width. This voltage is then transferred by the measuring cell to a measurement node which determines the minimum pulse width of all the transferred voltages for the plurality of pulses.

Abstract: A standard interface for interfacing a wireless modem assembly with a host device comprises a primary serial interface, a secondary serial interface, and a differential serial interface for supporting communication between the wireless modem assembly and the host device. The standard interface can be implemented in a standardized connector, such as a 70-pin connector having unused pins for future feature expansion. The standard interface also provides for other interfaces including, for example, power, modem status, audio, voice, general purpose input/output, and subscriber identification.

Abstract: A pulse width measuring device is disclosed that calculates the pulse width of a signal to be measured, based on a count value and a count clock signal. In the pulse width measuring device, the counter circuit has a plurality of bits that are divided into an exponent and a significand. The control unit of the pulse width measuring device includes: an exponent storing unit that stores an exponent setting value that represents the number of bits of the exponent of the counter circuit; and a decoder unit that generates a count value setting signal for rewriting the count value of the counter circuit, based on the exponent setting value stored in the exponent storing unit, when the count value overflows in the counter circuit, the decoder unit then outputting the count value setting signal to the counter circuit.

Abstract: An apparatus and method for safely handling asynchronous shutdown of pulsewidth modulated output. A shutdown circuit controls asynchronous shutdown of a pulsewidth modulated stage to ensure that pulsewidth modulated signals of less duration than a minimum period does not occur at transition edges of the pulsewidth modulated signal, in which such short pulses may affect the proper operation of output circuitry.

Abstract: At least one exemplary embodiment comprises a system comprising an arithmetic logic unit; a memory comprising a pre-computed table of target pulse widths, changes in pulse width, and pulse counts distributed according to a constrained semi-logarithmic distribution, the memory connected to the arithmetic logic unit via a pipeline mechanism; and a state machine adapted to load each of the target pulse widths and changes in pulse width from the memory into the arithmetic logic unit at pre-determined intervals of pulse count while maintaining control of a pulse width generated by the arithmetic logic unit.

Abstract: A variable aperture coding/decoding system suitable for use in a spread spectrum system provides multiple phase coding of an input NRZ bitstream. Each bit of a coded output signal is coded to encompass a predetermined different number of clock periods depending on the logic level of the input signal. A coded bit exhibits a predetermined reference number of clock periods, eg., 9, when the input signal does not exhibit a logic level transition. When the input signal exhibits a phase change from a 0 to a 1 logic level, the bit width of an associated coded bit is increased by 1 clock period, to 10 clock periods. When the input signal exhibits a phase change from a 1 to a 0 logic level, the bit width of an associated coded bit is decreased by 1 clock period, to 8 clocks periods. Thus the coded output signal may contain three types of information represented by a bit width change proportional to predetermined factor N.

Abstract: A method and accompanying circuitry for asynchronous data demodulation uses sorted pulsewidth measurement based on an asynchronous clock. Lock-on of the data stream by such a system is accomplished by measured pulsewidth, rather than inferred frequency. The method broadly comprises the steps of measuring a temporal aspect of the asynchronous clock, and locking onto the data stream in accordance with the measured periods. In the preferred embodiment, the temporal aspect is a ratio of measured periods. Conveniently, a ratio of 2:1 may be used.

Abstract: In a data receiver, pulse edges are sequentially detected from the pulse string. If a pulse which has a width equal to two cycles of the reference clock signals is detected, bit data ‘1’ is restored. If two consecutive pulses each of which has a width equal to one cycle are detected, bit data ‘0’ is restored. If a pulse width between two consecutive pulse edges is not equal to one cycle or two cycles, it is presumed that a pulse edge of an erroneous pulse is detected. If the pulse width between the pulse edge, which is presumed to correspond to the erroneous pulse, and the next pulse edge is equal to or shorter than a predetermined threshold Th, the pulse edge and the next pulse edge is invalidated.

Abstract: A digital data modulator includes a source of a plurality of digital data signals having a common data bit period. A plurality of encoders each encode a corresponding one of the plurality of digital data signals using a variable pulse width code having edges occurring in respective non-overlapping intervals within the data bit period. A plurality of pulse signal generators each generate respective pulses representing the edges of the corresponding one of the encoded plurality of digital data signals. A carrier signal generator generates a carrier signal having carrier pulses corresponding to the respective pulses.

Abstract: One aspect of the invention provides a method of processing an PPM encoded input signal transmission of data pulses to a data processing apparatus by processing the pulses by lengthening or shortening the pulses to a length within the predetermined acceptance pulse duration range of the data processing apparatus comprising: detecting when the input pulses of the input signal fall below the duration required and lengthening the pulses by a sufficient amount to bring them within the predetermined duration; detecting when the input pulses of the input signal exceed the duration required and reducing the duration of the pulses by a sufficient amount to bring them within the predetermined duration.

Abstract: In a method for decoding digital PWM signal and a bus system, a peripheral unit, and a device therefor, the digital signal is decoded by integrating the pulse width of each bit and then comparing the integration result with a reference signal. The bus system includes dual wires, a device, and at least one peripheral unit. In an embodiment of the present invention, the bus system issued as an air bag system where diagnostic and deployment commands are sent via the bus wires to one or more peripheral units which control individual air bags.