Abstract: Disclosed herein is a demodulator, including: a splitting/matching section for carrying out a matching process of making the amplitude and phase of a first modulated signal match respectively the amplitude and phase of a second modulated signal; and a demodulation section for generating a demodulated signal on the basis of the first modulated signal and the second modulated signal, which have been subjected to the matching process carried out by the splitting/matching section, wherein the splitting/matching section has a splitting section, a first matching section, and a second matching section, the first circuit-element constants determining the first input impedance of the first matching section and the second circuit-element constants determining the second input impedance of the second matching section are set at values determined in advance in order to make the first input impedance equal to the second input impedance.

Abstract: A demodulation circuit for an Amplitude Shift Keyed (ASK) modulated signal includes an envelope detector, an alternating voltage amplifier, a differentiator circuit, and a comparator having a hysteresis connected in series. The envelope detector produces an envelope signal from the received ASK signal. The amplifier blocks the DC component of the envelope signal and amplifies AC components of the envelope signal to obtain a steeper slope of the rising and falling edges. The differentiator circuit then processes the transition edges to provide a differentiated signal having positive and negative electrical pulses. The comparator converts the pulses into a binary data stream which corresponds to the transmitted data stream. The combination of the differentiated signal and comparator having a hysteresis enables better stability and sensitivity of the ASK demodulation circuit.

Abstract: A receiver estimates I/Q imbalance in I and Q input signals using circuitry to separate different frequency components of the I and Q input signals, and estimation circuitry arranged to estimate I/Q imbalance at the different frequency bands. The separating of the bands may be carried out in the frequency domain, and may involve combining corresponding values representing corresponding negative and positive frequency bands, and converting the separated frequency domain representations to a time domain representation before the estimation. The estimated imbalance may be used to correct the I and Q signals at the different frequency bands.

Abstract: A receiver for recovering timing and data information from a signal, comprising an envelope detector for demodulating the signal; to produce a demodulated signal; a filter for filtering the demodulated signal to remove or attenuate amplitude variations due to the timing information so as to produce a data signal; and a timing recovery circuit for forming a difference between time aligned versions of the demodulated signal and the data signal so as to recover the timing information.

Abstract: A demodulator circuit (DMOD) for amplitude-modulated signals is defined which comprises a threshold switch module (SWS), wherein a signal output (SA) of the threshold switch module (SWS) is connected to the output (DA) of the demodulator circuit (DMOD) and a signal input (SE) of the threshold switch module (SWS) is connected via a first capacitor (C1) to the input (E) of the demodulator circuit (DMOD). In addition, the signal input (SE) can be connected via a coupling element (KO) to a first or alternatively a second.

Abstract: A shunt regulator performs a control so as to stabilize a voltage obtained by rectifying the radio frequency signal output from an antenna unit at a prescribed voltage value. A signal extraction unit extracts the information signal from a bypass current sent by the shunt regulator for the control when the voltage fluctuates.

Abstract: A delayed peak detector detects a peak level of an input signal IN at timing lagged behind a peak detector, and a peak difference detector detects a peak difference PLD between a delayed peak level DPL and a peak level PL. A reset portion outputs a reset signal BRS for a bottom detector when a level difference between the peak level PL and a bottom level BL exceeds a predetermined value comparable with the amplitude of the input signal IN and the peak difference PLD exceeds an allowable peak difference PLM. It is thus possible to replace the bottom level BL outputted from the bottom detector with a bottom level based on a latest input signal IN.

Abstract: A receiver (202) has a down-conversion receiver (304) for transforming a signal (201) from a first operating frequency to a second operating frequency that is lower than the first operating frequency, and a receiver filter (308) with chopper stabilization for filtering unwanted portions of the signal (306) at the second operating frequency and for generating a final filtered signal (203) at the second operating frequency.

Abstract: An AM detecting apparatus includes a voltage comparator And an AND circuit. The voltage comparator compares a detection signal a low-pass filter outputs with a no-signal potential. The AND circuit outputs, when the amplitude of an AM signal is higher than the reference value, one of a first control signal and second control signal in response to a comparison result of the voltage comparator 5, and outputs, when the amplitude of the AM signal is lower than the reference value, the first control signal. The phase of the VCO signal is controlled such that the phase difference between the AM signal and VCO signal agrees with the control signal the AND circuit outputs. The AM detecting apparatus can carry out the coherent detection of the desired signal in the AM signal even during overmodulation.

Abstract: Two capacitors are provided for demodulating an amplitude-modulated signal and can be supplied with a signal that is rectified by a diode and that is at a voltage. The half-cycles of this signal are used for alternately charging the first or second capacitor using a switch. The capacitors are discharged using switches. Comparing the amplitude values, which are stored in the capacitors, of successive half-cycles in an evaluation unit allows simple and precise demodulation, which can be achieved with few components and can be carried out at very high frequencies.

Abstract: A computerized tomography (CT) system having an apparatus and method for receiving high data rate communication is disclosed herein. The apparatus includes a controlled variable attenuator for attenuating an encoded digital data signal having a wide range of power levels, a digital envelope detector for de-encoding the encoded digital data signal, a noise filtering circuit for filtering out the residual undesirable encoded signal components, and a feedback loop for maintaining a desired signal level such that the encoded digital data signal is converted to its pre-encoded state suitable for processing to generate a CT image.

Abstract: A computerized tomography (CT) system having an apparatus and method for receiving high data rate communication is disclosed herein. The apparatus includes a controlled variable attenuator for attenuating an encoded digital data signal having a wide range of power levels, a digital envelope detector for de-encoding the encoded digital data signal, a noise filtering circuit for filtering out the residual undesirable encoded signal components, and a feedback loop for maintaining a desired signal level such that the encoded digital data signal is converted to its pre-encoded state suitable for processing to generate a CT image.

Abstract: A demodulator circuit for demodulating a signal ASK-modulated with modulation pulses equal in duration, and having a small depth of modulation and large dynamic range comprises an amplitude limiter (10) through which an amplitude-dependent current flows when the amplitude of the signal to be demodulated exceeds its limiting threshold value. Furthermore comprised is an envelope detector (12) to the input of which the signal to be demodulated is applied, as well as a differentiating network (14) configured so that it differentiates the output signal of the envelope detector (12) and outputs a signal pulse only when the change in amplitude of this output signal is in one direction. A bandpass filter (18) in the demodulator circuit passes, from a signal derived from an amplitude-dependent current from the amplitude limiter (10), the frequency component attributed to the duration of the modulation pulses.

Abstract: A method and apparatus is shown for controlling the input gain of a receiver wherein the input gain is controlled by sampling an amplified data signal during a time interval when a positive-going feedback transient from an output terminal of the receiver to an input terminal of the receiver is not present in the amplified data signal. An embodiment of a receiver circuit according to the present invention includes an input amplifier having variable gain determined by a gain control signal, a comparator which compares the amplified data signal from the input amplifier to a detection threshold voltage to produce a demodulated data signal and an analog delay circuit which delays the amplified data signal by a predetermined time interval to produce a delayed data signal. A switch is driven by the demodulated data signal to sample the delayed data signal for input to an automatic gain control circuit.

Abstract: In a circuit arrangement for demodulating an intermediate-frequency video signal generated while using a Nyquist edge, having a phase-locked loop (1) including a phase detector (3), a loop filter (4) and a voltage-controlled oscillator (5), and a video demodulator (2), the intermediate-frequency video signal being applied to the phase detector (3) and the output signal of the phase-locked loop (1) being applied to the video demodulator (2), which converts the intermediate-frequency video signal into a baseband video signal, phase fluctuations contained in the carrier of the intermediate-frequency video signal due to its generation while using a Nyquist edge are compensated in that the phase comparator (3) operates, by approximation, independently of modulation in the control range of the intermediate-frequency video signal, in that the baseband video signal is present in an inverted form with respect to the intermediate-frequency video signal, and in that a correction signal is derived from the baseband video

Abstract: A DC offset measurement and compensation circuit includes a switch arrangement for establishing a zero carrier condition in the circuit. The circuit output is integrated to develop any DC offsets, which are converted to analog form and subtracted from the signal output. A reference may also be subtracted to establish a base digital level for the output.

Abstract: An automatic offset control circuit comprises a differential output preamplifier having an offset adjustment function, further comprising an average detector, a peak detector, and a differential input amplifier. The average detector generates a reference voltage representing an average value of a positive output and a negative output of the preamplifier. The peak detector outputs a peak voltage representing a peak of the negative output of the preamplifier. The differential input amplifier compares the peak voltage with the reference voltage to output an offset adjustment signal to the preamplifier. The offset adjustment signal is obtained based on a difference between the reference voltage and the peak voltage. A bottom detector may be used instead of the peak detector, provided a bottom value is detected using the positive output of the preamplifier.

Abstract: A digital AM transmitter according to the invention converts a audio signal to a digital audio signal of a plurality of bits by an A/D converter, outputs a logical code signal of "1" from each of those output terminals of a code unit, whose number corresponds to the digital value of the digital audio signal, selectively generates driving signals from those output terminals of a code shifter which are equal in number to the logical code signals of "1" from the code unit, while changing the driving-signal-generating output terminals of the code shifter from one to another (or some to others) with the lapse of time, selectively guiding, with the use of carrier wave switches, those portions of a carrier wave signal which have been divided by a carrier wave divider, to power amplifiers in accordance with driving signals generated from the code shifter, amplifies the guided portions of the carrier wave signal by power amplifiers, combined the amplified portions of the carrier wave signal by a combiner, and passes t

Abstract: A data slicer follows abrupt variations in level of the detection signal. The data slicer for converting a detection signal into a digital signal in a data transmission system includes a maximum value detecting section, a minimum value detecting section, a voltage shift-down section, a voltage shift-up section, and a binary encoding circuit. The maximum value detecting section detects the maximum value of the detecting signal, while the minimum value detecting section detects the minimum value of the detecting signal. The voltage shift-down section sets a minimum value which the minimum value detecting section should take according to the output voltage of the maximum value detecting section, while the voltage shift-up section sets a maximum value which the maximum value detecting section should take according to the output voltage of the minimum value detecting section.

Abstract: There is described an electronic circuit which operates an Amplitude Locked Loop. The circuit comprises a voltage controlled amplifier, a modulus detector and an integrator combined in a feedback loop. An FM signal decoder is also described as are a number of applications of Amplitude Locked Loop.

Abstract: In a digital mobile system, to avoid distortions and fadings due to multiple propagation and the doppler shift, adaptive gain of the amplifier of a demodulator must be controlled with information derived from the signal at a high frequency. This is accomplished without the use of intermediate frequency selection filters by first demodulating the signal to base band, filtering out the desired signal and remodulating the desired signal to a higher frequency. From this remodulated signal the adjustable gain is controlled.

Abstract: The invention is an automatic gain control (AGC) sampling structure in which a conventional closed loop AGC circuit detects a received level and generates a direct current voltage for controlling an amplification stage. This direct current voltage is sampled and the optimum control voltage is selected from the samples based on the technique of ordered statistics. The conventional AGC control loop is interrupted and the selected control voltage is provided to the amplification stage.

Abstract: A digital demodulator or receiver (22) having an interface (24) for receiving an input signal modulated with digital data, a multiplier (36) for multiplying the input signal with a local oscillator signal (LO) to generate a product signal, and an integrator (38) for periodically integrating the product signal to generate a sequence of integrated signals, each having an amplitude indicative of a respective portion of the digital data, additionally includes a circuit (30, 32) for directly generating a plurality of logic signals and a summer (34) for summing the logic signals to directly synthesize the local oscillator signal (LO). The local oscillator signal (LO) thereby produced has a fundamental component and third and fourth harmonic components and is shaped to ensure that each of the third and fourth harmonic components has an amplitude substantially less than that of the fundamental component.

Abstract: A regenerating device for regenerating a signal from a composite input signal, provided with a phase-locked loop comprising a first phase comparison circuit 1, a first low-pass filter 2 connected to the output thereof and a controlled oscillator 3. The control input of said oscillator 3 is connected to the output of the low-pass filter 2 while its quadrature output 3a is connected to one input of the phase comparison circuit 1. The input of the phase comparison circuit 1 forms the input of the regenerating device and the in-phase output of the oscillator 3 the output. Furthermore a second phase comparison circuit 4 and a second low-pass filter 5 connected thereto are provided, which correspond to the first phase comparison circuit and the first low-pass filter respectively. The input of the phase-locked loop and the in-phase output 3b of the controlled oscillator 3 are connected to the inputs of the phase comparison circuit 4.