Abstract: Systems and methods are described for enhancing the audio quality of an FM receiver. In embodiments described herein, a stop band noise signal is extracted from an L+R or L?R signal produced by an FM stereo decoder. A channel quality measure is calculated based on the stop band noise signal and is used to control whether a pop suppression technique is applied to the L+R signal. The channel quality measure and the stop band noise signal are also leveraged to perform single-channel noise suppression in the frequency domain on the L?R signal and on the L+R signal. The channel quality measure is also used to control the application of a fast fading compensation process that replaces noisy segments of the L?R and L+R signal with replacement waveforms generated via waveform extrapolation.

Abstract: Systems and methods are described for enhancing the audio quality of an FM receiver. In embodiments described herein, quadrature L?R demodulation is applied to a composite baseband signal output by an FM demodulator to obtain an L?R noise signal. A channel quality measure is calculated based on the L?R noise signal and is used to control whether a pop suppression technique is applied to an L+R signal obtained from the composite baseband signal to detect and remove noise pulses therefrom. The channel quality measure and the L?R noise signal are also leveraged to perform single-channel noise suppression in the frequency domain on an L?R signal obtained from the composite baseband signal and on the L+R signal. The channel quality measure is also used to control the application of a fast fading compensation process that replaces noisy segments of the L?R and L+R signal with replacement waveforms generated via waveform extrapolation.

Abstract: A channel stacking system includes first and second downconverting stages, first and second analog to digital converters, and a digital switching and signal processor. The first downconverting stage includes a first downconverter circuit having an input for receiving a first RF input signal which includes a multitude of first channels. The first downconverter circuit frequency downconverts the first RF input signal to a first IF signal which includes the multitude of first channels. The first analog-to-digital converter converts the first IF signal to a first digital IF signal. The second downconverter stage includes a second downconverter circuit having an input for receiving a second RF input signal which includes a multitude of second channels. The second downconverter circuit frequency downconverts the second RF input signal to a second IF signal including said multitude of second channels.

Abstract: A demodulator includes a sampler and a trigger unit. The sampler is configured to sample a carrier signal based on a trigger signal to obtain a demodulated signal. The trigger unit is configured to detect a zero crossing of the carrier signal or an extreme value of an amplitude of the carrier signal. Further, the trigger unit is configured to provide the trigger signal based on the detected zero crossing or the detected extreme value, so that the carrier signal is sampled by the sampler with a predefined phase shift to the detected zero crossing or the detected extreme value. The predefined phase shift is larger than 30° plus an integer multiple of 90° and lower than 60° plus the same integer multiple of 90° in reference to the carrier signal.

Abstract: A demodulator for use in a receiver converts a digital baseband signal into inbound digital symbols with reduced hardware complexity and reduced power consumption. The demodulator includes a lowpass filter operably coupled to filter the digital baseband signal to produce a filtered digital baseband signal, and an equalizer operating at a first sampling rate to equalize the frequency response of the digital baseband signal such that the receiver overall in-band frequency response approximates the frequency response of a square root raised cosine filter to produce an adjusted digital baseband signal. An interpolator receives the adjusted digital baseband signal at the first sampling rate and interpolates the adjusted digital baseband signal to produce an interpolated digital baseband signal at a second sampling rate, from which the inbound digital symbols can be generated.

Abstract: A circuit arrangement for matching a demodulator to operating conditions comprises a demodulator designed to demodulate an analog input signal to a demodulated signal. The demodulator is also designed to be driven by a control signal. The circuit arrangement further comprises a sensor which is designed to provide a sensor status signal, and a control unit to whose input side the sensor status signal is applied and which is designed to provide the control signal for the demodulator during operation.

Abstract: An efficient configurable signal filter. The filter includes a first mechanism for receiving a first signal of a first type and a second signal of a second type. A second mechanism selectively filters the first signal during a first mode of operation, and filters the second signal during a second mode of operation. A third mechanism generates control signals. A fourth mechanism automatically configures the second mechanism to operate in the first mode of operation or the second mode of operation based on the control signals. In a specific embodiment, the first type of signal is characterized by a first rate, and the second type of signal is characterized by a second rate. The first signal and the second signal are digital ADC outputs. The second mechanism includes plural filter blocks, each having one or more Multiply-Accumulate (MAC) pipes. Each of the one or more MAC pipes include one or more MAC blocks that are each associated with a coefficient memory data structure of a coefficient memory.

Abstract: A demodulator system and method is disclosed. In an embodiment, the demodulator system can include a Coordinate Rotation Digital Computer (CORDIC) mixer to mix a first signal substantially to baseband using a first input frequency and to mix a second signal substantially to baseband using a second input frequency. In another embodiment, the demodulator system can include a phase detector to receive a pilot signal and to generate a control signal to adjust a decimation rate based on the pilot signal. In another embodiment, the demodulator system can include a symbol decoder to determine a symbol from a phase signal.

Abstract: A signal received by a receiving antenna is input to an UDMV through a detector, and compensation for distortion caused by multipath fading and an error correction using Viterbi decoding are simultaneously performed, obtaining demodulation data. The UDMV comprises a demodulator in which an MLSE and a Viterbi decoder are combined. Thereby, equalization for removing a line distortion and reduction in an error rate can be simultaneously performed, improving a receiving quality.

Abstract: A digital signal processing architecture for an audio system combines multiple functions in programmable and reconfigurable blocks to achieve an efficient use of hardware and chip area. AM, FM, and audio functions can be performed using the same reconfigurable hardware while taking into account the different sample rates and processing functions required for each.

Abstract: A universal modem has a software-configurable modulator/demodulator which accommodates different modulation formats such as those associated with terrestrial, cable, phone line, satellite and wireless communications to be transmitted and received through a single device in which the modem has reconfigurable logic to accommodate the format of the signals being received or transmitted. In one embodiment, the system tracks channel noise and changes modulation format at both the transmit and receive sides of the system through the use of a controller that controls both sides.

Abstract: A data demodulation logic unit (200) and method used therein, adaptable to multiple data protocols, including an arithmetic logic unit (205) that is architecturally optimized to demodulate multiple data protocols under the control of a hardware based state machine (209) that operates in a selectable mode that corresponds to one of multiple data protocols.