Bootstrap Coupling Patents (Class 330/156)
  • Patent number: 9924118
    Abstract: In an image sensor, the effective capacitance of the storage node NS of the pixel, which stores the charges (the electrons) collected by the photosensitive element of the pixel, is modified with the aid of a feedback loop 100 which influences the supply VREFP of the follower transistor T3 connected to the storage node, in such a way that the apparent capacitance of the storage node depends on the gain GL of the loop. By modifying the gain, the capacitance of the storage node and therefore the charge/voltage conversion factor, which is inversely proportional to this capacitance, is modified.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 20, 2018
    Inventor: St├ęphane Gesset
  • Patent number: 9100017
    Abstract: An impedance circuit coupled to a first power supply includes: an output node; a transistor coupled between the output node and the first power supply, wherein the transistor comprises a gate electrode; and a voltage source electrically coupled to the gate electrode of the transistor and configured to apply a gate voltage to the gate electrode of the transistor, wherein the voltage source includes: a plurality of impedance components electrically coupled in series between a circuit node and the first power supply, and a current source electrically coupled between the circuit node and a second power supply.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: August 4, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Nasrin Jaffari
  • Patent number: 8630598
    Abstract: A wireless communications device, e.g., a mobile node supporting direct peer to peer communications, performs a self-calibration of one or more of: receiver IQ imbalance, transmitter IQ imbalance, receiver DC offset, and transmitter DC offset. The wireless communications device, operating in calibration mode, intentionally sets the oscillator frequency used for downconversion in its receiver module to a different frequency than the oscillator frequency used for upconversion in its transmitter module. A first baseband signal, e.g., a single tone test signal, is input to the transmitter module and an upconverted transmit signal is generated. The transmit signal is routed via a feedback loop to the receiver, which performs a downconversion operation. Power and/or phase measurements of the signals output from the downcoversion are used to determine IQ imbalance compensation information and DC offset compensation information.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: January 14, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Rajiv Laroia, Juergen Cezanne, Aleksandar Jovicic
  • Patent number: 7852154
    Abstract: A high performance follower device coupled with a slew enhancement circuit includes an amplifier circuit containing a follower device connected to a three-terminal device, whereupon current drawn through the three-terminal device is amplified through a current amplifier and sent to the source terminal of the follower device to stabilize the output voltage when the input signal is changed rapidly or if the output voltage is disturbed by a changing output load. The presence of a cascode device also allows for the bootstrapping of the follower device.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: December 14, 2010
    Assignee: Analog Devices, Inc.
    Inventor: Padraig Cooney
  • Patent number: 7795977
    Abstract: A bootstrapped class AB CMOS output circuit and method for generating a class AB output are disclosed. The bootstrapped class AB CMOS output circuit has a voltage offset circuit coupled to an NMOS transistor and a PMOS transistor. The voltage offset circuit has a capacitor bootstrapped between the NMOS transistor and the PMOS transistor to establish a voltage offset between the NMOS transistor and the PMOS transistor to effect a class AB output. The method for generating a class AB output in a semiconductor device having a capacitor coupled to the NMOS transistor and the PMOS transistor includes providing a voltage offset across the capacitor to effect a class AB output.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: September 14, 2010
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventor: Mihail Milkov
  • Patent number: 7468622
    Abstract: An integrated circuit having a bootstrap charger for using in a switching mode power supply is disclosed. In one embodiment, a capacitor is connected between a floating terminal and a bootstrap supply terminal with a voltage drop over the capacitor, a comparing device with a first input terminal receiving a fraction of the voltage drop, a second input terminal receiving a reference, and an output terminal providing a control signal, and a charge circuit configured to charge the capacitor dependent on the control signal.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: December 23, 2008
    Assignee: Infineon Technologies AG
    Inventors: Emanuele Bodano, Christian Garbossa, Marco Flaibani
  • Patent number: 6879215
    Abstract: Synthetic circuit elements and amplifier applications for synthetic circuit elements are provided. The synthetic circuit elements disclosed herein may be configured to compensate for some or all of the parasitic capacitance normally associated with circuit elements disposed on a substrate providing a selectable impedance characteristic. Amplifier circuit constructed using such synthetic circuit elements exhibit improved performance characteristics such as improved recovery time, frequency response, and time domain response.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: April 12, 2005
    Assignee: Linear Technology Corporation
    Inventor: Steven D. Roach
  • Patent number: 5945877
    Abstract: An amplifier output stage having an output transistor connected to a high supply voltage and a bootstrap terminal coupled to a control terminal of the output transistor through control circuitry. The output stage includes a capacitor arranged between the bootstrap terminal and the output terminal of the output stage for elevating the voltage at the bootstrap terminal above the high supply voltage, and circuitry for limiting the voltage at the bootstrap terminal to a predetermined threshold. The circuitry for limiting the voltage at the bootstrap terminal directly acts on the control terminal of the output transistor to reduce the conductivity of the output transistor when the voltage at the bootstrap terminal exceeds the predetermined threshold.
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: August 31, 1999
    Assignee: SGS-Thomas Microelectronics Pte. Ltd.
    Inventors: PakriSwami Elango, Gee-Heng Loh
  • Patent number: 5892398
    Abstract: This invention is for an improvement in amplifiers resulting in ultra low distortion.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: April 6, 1999
    Assignee: BHC Consulting Pty Ltd
    Inventor: Bruce Halcro Candy
  • Patent number: 5861775
    Abstract: A cost-effective conditioning circuit for extracting a weak, floating, wide-band signal with a low common-mode voltage from noisy environments is proposed that includes a high gain single ended operational amplifier to increase the amplitude of the signal. A simple, cost-effective approximately unity gain differential amplifier stage is used to level-shift the signal down to the desired reference potential. A typical application is a motor drive system, where the signals to be measured are bi-directional motor currents.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: January 19, 1999
    Assignee: Ford Global Technologies, Inc.
    Inventors: Chingchi Chen, Venkateswara Anand Sankaran
  • Patent number: 5638026
    Abstract: A high input impedance circuit includes an amplifier such as an operational amplifier comprising transistors of a first polarity which serve as a differential pair and input of the amplifier, base of one transistor being caused to serve as a positive input terminal, base of the other transistor being caused to serve as a negative input terminal. The high input impedance circuit further includes a transistor having base connected to the positive input terminal, and a second polarity opposite to the first polarity, wherein collector of the transistor of the second polarity is connected through d.c. path to a first power supply, e.g., ground, and emitter of the transistor of the second polarity is connected through d.c. path to a second power supply, e.g., power supply voltage terminal through a resistor to apply a signal in phase with an input signal delivered to the positive input terminal to the emitter of the transistor of second polarity to thereby allow input impedance to be higher.
    Type: Grant
    Filed: July 28, 1995
    Date of Patent: June 10, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaru Hashimoto
  • Patent number: 5592123
    Abstract: A floating current mirror circuit is disclosed which achieves high open loop gain without additional voltage gain stages leading to frequency compensation and increased power dissipation. The output of the circuit has only a first pole and is designed to be coupled to a second current source, a base coupled to the first terminal of the diode, and an emitter coupled to the floating node. A second bipolar transistor has a base coupled to the collector of the first transistor, and emitter coupled to the floating node.
    Type: Grant
    Filed: March 7, 1995
    Date of Patent: January 7, 1997
    Assignee: Linfinity Microelectronics, Inc.
    Inventor: Stephen F. Ulbrich
  • Patent number: 5521555
    Abstract: An amplifier topology for receiving signals output from a fiber optic rotation sensor and producing voltages that may be processed to determine the rotation rate includes a photodiode for receiving an optical signal and producing a corresponding electrical photodiode output signal. An ultra low noise and ultra low capacitance differential input stage is connected to receive the photodiode output signal. An operational amplifier having low noise and ultra-wide bandwidth is connected to the ultra low capacitance differential input stage to receive the output signal therefrom as a driving signal and to produce a low noise output signal. The differential input stage comprises a first amplifier circuit that includes a first transistor connected to the photodetector to act as a first buffer having low noise, low capacitance and unity gain.
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: May 28, 1996
    Assignee: Litton Systems, Inc.
    Inventors: Daniel A. Tazartes, John E. Higbee, Jacque A. Tazartes, Juergen K. P. Flamm, John G. Mark
  • Patent number: 5416442
    Abstract: An improved Class A amplifier has an enhanced slew rate response at high frequencies. A positive feedback path is connected from the output of the amplifier to a point on the gain path. The feedback path includes a capacitor, a resistor and a transistor, the resistor being connected between the base and emitter of the transistor. At relatively high frequencies, the voltage drop across the resistor causes the transistor to turn on, forming a buffered positive feedback path through an additional resistor. The amount of feedback is controlled by the second resistor in the feedback path. In the preferred embodiment, dual feedback paths are connected between the output terminal and different points in the gain path.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: May 16, 1995
    Assignee: National Semiconductor Corporation
    Inventor: Stephen W. Hobrecht
  • Patent number: 5392001
    Abstract: A capacitively-coupled amplifier circuit includes an amplifier for receiving an input signal via a coupling capacitance and for amplifying the input signal to produce an output signal. A resistor provides a bias voltage to the amplifier. The resistor is bootstrapped using positive feedback with a loop gain of slightly less than one. The bootstrapping causes an increase in the value of the resistor to lower the cut-in (pole) frequency of the amplifier. The bootstrapping or feedback circuit includes a roll-off (pole) at a frequency below the roll-off (pole) frequency of the amplifier. This prevents phase shift in the feedback loop from adversely effecting the high frequency response of the amplifier. The resulting amplifier circuit exhibits a wide passband and excellent low frequency response despite having a capacitively coupled input signal.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: February 21, 1995
    Assignee: Hewlett-Packard Company
    Inventors: Thomas F. Uhling, John M. Heumann, Ronald J. Peiffer
  • Patent number: 5337011
    Abstract: A tiny pre-amplifier for a small, low voltage, high impedance signal source, usually an electret microphone, exhibiting near unity gain, has an input cascode stage connected to the microphone and a matched balancing cascode stage; both cascode stages are energized from the same power supply circuit. The two cascode stages supply intermediate signals to the inputs of a differential amplifier to generate an output signal having a greatly reduced noise content, independent of power supply variations. The pre-amplifier is wholly integratable, has low power drain, and fits into the microphone housing.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: August 9, 1994
    Assignee: Knowles Electronics, Inc.
    Inventors: John S. French, Richard W. Peters
  • Patent number: 5315263
    Abstract: An audio power amplifier includes a stacked pair of complementary transistors having the emitters commonly coupled to a load. A driver stage couples the bases of the stacked pair to a source of audio frequency signal. A bootstrap capacitor is coupled between the commonly coupled output node and the supply voltage. An isolation diode is interposed between the bootstrap capacitor and the operating supply to prevent discharge of the bootstrap capacitor into the operating supply during positive signal swings.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: May 24, 1994
    Assignee: Zenith Electronics Corp.
    Inventors: Robert E. Mudra, Mark A. Scholten
  • Patent number: 5192920
    Abstract: A high-gain, low-noise transistor amplifier comprises an input, an output, and first and second field effect transistors each having a gate, a drain, and a source and being formed in a common semiconductor substrate. The second transistor is a depletion mode transistor if it is of the same conductivity type as the first but is an enhancement mode transistor if it is of opposite conductivity type with respect to the first. In an amplifier configuration, the input is coupled to the gate of the first transistor, the source of the first transistor is coupled to the gate of the second transistor, the source of the second transistor is coupled to the output, and there is a direct-coupled feedback path from the source of the second transistor to the drain of the first transistor. At least the first transistor is formed in an isolated well of conductivity opposite to that of the substrate in the semiconductor substrate and its source is coupled directly to that well.
    Type: Grant
    Filed: March 18, 1992
    Date of Patent: March 9, 1993
    Assignee: Eastman Kodak Company
    Inventors: Edward T. Nelson, Eric G. Stevens, David M. Boisvert
  • Patent number: 5140279
    Abstract: A high speed feedback amplifier is frequency compensated utilizing circuitry that does not cause distortion in the amplifier nor does it limit the slew rate of the amplifier. In one embodiment compensation circuitry drives one side of the compensation capacitor forcing the signal voltage across the compensation capacitor to zero while still providing bandwidth compensation. Since no current gets driven into the capacitor, no distortion or slew limitations are created by the compensation. In a second embodiment the voltage across the compensation capacitor is allowed to change, however the signal current for the compensation capacitor is supplied by a linear charging circuit which removes this charging requirement from the amplifier. Therefore, as in the first embodiment, no distortion or slew limitation is created by the addition of the frequency compensation.
    Type: Grant
    Filed: December 3, 1990
    Date of Patent: August 18, 1992
    Assignee: Crystal Semiconductor Corporation
    Inventor: Baker P. L. Scott, III
  • Patent number: 5111084
    Abstract: A drain pulsing circuit for intermittently applying electric power to the drain of a solid state amplifier uses a N-channel MOSFET as the drain switch, but does not require an external bias voltage to drive the drain switch gate. The pulsing circuit generally comprises a control input circuit for generating a control pulse, and a charge pumping circuit having a capacitor that is connected to the output of the control input circuit, and first and second complementary MOSFET switches. The capacitor in the pumping circuit stores a charge during an off cycle when the control input circuit does not generate a control pulse. However, when a control pulse is generated, the first and second complementary MOSFET switches of the pumping circuit connect the gate of the N-channel drain switch MOSFET to the voltages associated with both the capacitor charge and the control pulse (which "pumps" the capacitor to a higher charge) in order to temporarily bias the N-channel drain switch MOSFET to an "on" state.
    Type: Grant
    Filed: May 31, 1990
    Date of Patent: May 5, 1992
    Assignee: Westinghouse Electric Corp.
    Inventor: Scott K. Suko
  • Patent number: 4791313
    Abstract: A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.
    Type: Grant
    Filed: November 13, 1986
    Date of Patent: December 13, 1988
    Assignee: Fairchild Semiconductor Corp.
    Inventors: James R. Kuo, Brian R. Carey, Timothy G. Moran
  • Patent number: 4791383
    Abstract: A high speed buffer circuit is composed of complementary symmetry emitter follower driver and output stages. The input of driver stage includes active load devices cross-coupled to the output stage inputs so that the output stage is bootstrap driven from emitter followers. The circuit is biased by level shifting means to operate as a class AB current amplifier. It displays a wide bandwidth along with a high slew rate and can source or sink a large pulsed current.
    Type: Grant
    Filed: September 4, 1987
    Date of Patent: December 13, 1988
    Assignee: National Semiconductor Corporation
    Inventors: Dennis M. Monticelli, John W. Wright
  • Patent number: 4786879
    Abstract: When impedance elements such as FETs are used in attenuators, the elements have linear responses only when the signals attenuated are below certain signal levels. When signal conditions causing the element to operate non-linearly are detected, bootstrapping is applied to reduce the voltage across the element so that the element will operate linearly. The control signal at the gate of the element is then modified to compensate for the increase in effective impedance of the element caused by bootstrapping. The improved attentuators are especially useful in signal compressors and expanders.
    Type: Grant
    Filed: February 25, 1987
    Date of Patent: November 22, 1988
    Inventor: Ray M. Dolby
  • Patent number: 4764732
    Abstract: There is disclosed an amplifier device for use with a photodetector for amplifying wave energy signals received by the photodetector and converted into electrical signals. The amplifier device includes a first amplifier having its input connected to a junction between the photodetector and first and second photodetector load impedances. A negative feedback amplifier is connected to the output of the first amplifier. The negative feedback amplifier provides a feedback voltage to the first load impedance when in its first mode of operation and effectively reduces the voltage feedback to the first load impedance when in its second mode of operation. A switching device is provided to effectively switch the second load impedance in and out of circuit with the photodetector to effectively change the photodetector load impedance and alter the bias voltage to the feedback amplifier.
    Type: Grant
    Filed: October 20, 1987
    Date of Patent: August 16, 1988
    Assignee: General Electric Company
    Inventor: Bruno Dion
  • Patent number: 4752702
    Abstract: A bootstrap condenser connected to the output of the circuit is preloaded during the low output state when the load transistor is off and the drive transistor is normally on. A commutation signal brings about extinction of the drive transistor and connection of the condenser to the gate of the load transistor to turn on the latter and secure the resulting rise of the circuit output. Transistors of the pilot circuit are arranged for maximum bootstrap efficiency.
    Type: Grant
    Filed: July 31, 1986
    Date of Patent: June 21, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventor: Maurizio Gaibotti
  • Patent number: 4746877
    Abstract: An improved gain stage includes a pair of differentially-connected, matched, bipolar transistors and local positive feedback from the output to the collector electrode of one input transistor to provide D.C. balance and substantially enhanced voltage gain.
    Type: Grant
    Filed: September 25, 1986
    Date of Patent: May 24, 1988
    Assignee: Elantec
    Inventor: Barry Siegel
  • Patent number: 4706039
    Abstract: A class-G amplifier comprises first, second and third terminals connected to a load, first supply voltage (V.sub.1) and second supply voltage (V.sub.2), respectively, where V.sub.2 >V.sub.1. First (T.sub.1) and second (T.sub.2) transistors are series-connected between the first and third terminals with the collector of T.sub.1 coupled via first diode (D.sub.1) to the second terminal. A third emitter follower transistor (T.sub.3) has a B/E junction coupled between a signal input terminal and base of T.sub.1. A first current source (5) couples the third terminal and third transistor. A driver circuit includes a first current path between the third terminal and emitter of T.sub.3 comprising, in series, a second current source (7), a fourth transistor (T.sub.5) and second diode (D.sub.4). A second current path between a junction point (3) and common point (11) comprises, in series, third (D.sub.2) and fourth (D.sub.3) diodes and a third current source (8).
    Type: Grant
    Filed: March 11, 1986
    Date of Patent: November 10, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Eise C. Dijkmans, Joseph G. G. Raets, Norbert J. L. Philips
  • Patent number: 4706035
    Abstract: A high-efficiency class-G type amplifier comprises a first transistor (T.sub.1), having its collector connected to a first supply voltage (V.sub.1) via a first diode (D.sub.1) and a second transistor (T.sub.2), connected in series with the first transistor and which has its collector connected to a second supply voltage (V.sub.2). The series arrangement of a second (D.sub.2), a third (D.sub.3) and a fourth diode (D.sub.4) is connected between the bases of the first and the second transistor (T.sub.1, T.sub.2) the fourth diode (D.sub.4) is poled in a direction opposite to that of the second (D.sub.2) and the third diode (D.sub.3). The series arrangement of a first resistor (R.sub.1) and the emitter-collector path of a first current-source transistor (T.sub.4) connects the second supply voltage to the anode of the fourth diode (D.sub.4). The junction point (5) between the first resistor (R.sub.1) and the current-source transistor (T.sub.4) is connected to the output (2) by means of a capacitor (C.sub.1).
    Type: Grant
    Filed: March 11, 1986
    Date of Patent: November 10, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Eise C. Dijkmans, Joseph G. G. Raets, Norbert J. L. Philips
  • Patent number: 4688001
    Abstract: A high efficiency class-G amplifier comprises first (2), second (4) and third (10) terminals connected to a load, a first (V.sub.1) and second (V.sub.2) supply voltage, respectively, where voltage V.sub.2 >V.sub.1. First (T.sub.1) and second (T.sub.2) transistors are serially connected between the first and third terminals. A third transistor (T.sub.3, emitter-follower) couples a signal input terminal (6) to the base of the first transistor. A first diode (D.sub.1) connects the collector of T.sub.1 to the second terminal. A driver circuit includes a current path between the third terminal and a common terminal (11) having, in series, a first current source (7), second (D.sub.2) and third (D.sub.3) diodes and a second current source (8). A fourth diode (D.sub.4) connects junction point 3 to junction point 9. A fifth diode (D.sub.5) connects the emitter of the third transistor to the second current source.
    Type: Grant
    Filed: March 11, 1986
    Date of Patent: August 18, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Eise C. Dijkmans, Joseph G. G. Raets, Norbert J. L. Philips
  • Patent number: 4646002
    Abstract: A zero capacitance measurement probe to be used to make electrical measurements at a broad range of frequencies without having the probe itself affect the measured values. The probe reduces internal capacitances in the solid state active elements or creates a negative impedance to counteract capacitance external capacitance. Elimination of capacitance is accomplished by adjusting gains and current flow within active elements and by insulating the elements from ground by an additional substrate and metalized layer.
    Type: Grant
    Filed: May 10, 1984
    Date of Patent: February 24, 1987
    Assignee: Regents of the University of Minnesota
    Inventor: Alfons A. Tuszyski
  • Patent number: 4622498
    Abstract: Dynamic focus system utilizing an improved cascode amplifier is provided wherein the amplifier provides substantial voltage gain for a composite horizontal and vertical parabola signal and the output of the cascode amplifier is provided to the focus control electrode of a cathode ray tube. Undesired phase shift of the output of the cascode amplifier is prevented by AC coupling a signal corresponding to the noninverted input signal applied to the cascode amplifier to the base of the second transistor of the cascode amplifier.
    Type: Grant
    Filed: September 3, 1985
    Date of Patent: November 11, 1986
    Assignee: Motorola, Inc.
    Inventor: Theodore V. Lester
  • Patent number: 4524331
    Abstract: A three-stage amplifier circuit specially configured to provide a high input impedance. An initial emitter follower transistor stage amplifies the current level of an ac input signal to produce a first intermediate signal, a common-base transistor stage amplifies the voltage level of the first intermediate signal to produce a second intermediate signal, and a final emitter-follower transistor stage amplifies the current level of the second intermediate signal to produce an output signal in phase with the input signal. A feedback circuit feeds back the output signal to the input of the common-base transistor stage, to supplement the first intermediate signal input. This effectively increases the input impedance of the common-base transistor stage and, likewise, the initial emitter follower transistor stage, whereby the amplifier circuit can be used to amplify signals produced by high impedance sources.
    Type: Grant
    Filed: September 13, 1982
    Date of Patent: June 18, 1985
    Assignee: Orion Industries, Inc.
    Inventor: Richard W. Faith
  • Patent number: 4500849
    Abstract: A low noise power amplifier in which a buffer including a field effect transistor coupled in a source follower configuration is interposed between a voltage amplifying stage and a power amplifying stage, the latter utilizing a single-ended push-pull emitter follower configuration. A cascode transistor is cascade connected with the field effect transistor. A constant current source is provided for supplying current to the source of the field effect transistor. Field effect transistor buffers are preferably provided between the voltage amplifying stage and both positive and negative amplifying portions of the power amplifying stage.
    Type: Grant
    Filed: February 4, 1983
    Date of Patent: February 19, 1985
    Assignee: Pioneoer Electronic Corporation
    Inventor: Kazuaki Nakayama
  • Patent number: 4499432
    Abstract: An operational power amplifier having a bootstrap power output stage is designed to provide maximum dynamic range over a wide range of supply voltages. A control circuit in the form of a switched current mirror is added to the amplifier biasing circuit. At supply voltage higher than a predetermined threshold, the amplifier bias is adjusted to provide one half of this voltage at the output terminal. For supply voltages less than the threshold value, the output voltage is made less than half supply voltage.
    Type: Grant
    Filed: November 4, 1982
    Date of Patent: February 12, 1985
    Assignee: National Semiconductor Corporation
    Inventors: William H. Gross, Tadashi Sakurai
  • Patent number: 4492932
    Abstract: An electronic circuit for a high impedance probe for an instrument for measuring electrical voltages, comprising an input field effect transistor 15 connected in a source-follower configuration, a bipolar transistor 17 connected in an emitter-follower configuration and controlled by the transistor 15, a current source 18 serving as a load for the transistor 17, an amplifier 19 having a gain G which is slightly less than unity, the input of the amplifier being controlled by the transistor 15, and finally a resistor 20 which serves as a load for the transistor 15 and which connects the source of the transistor 15 to the output 8 of the amplifier 19, said output also serving as the output of the circuit, which is supplied by a voltage source applied between the current source 18 and the collector of the transistor 17. By virtue of the amplifier 19, the effective load resistance seen by the transistor 15 is R.sub.20 /(1-G), R.sub.20 being the value of the resistor 20.
    Type: Grant
    Filed: September 20, 1982
    Date of Patent: January 8, 1985
    Assignee: Asulab S.A.
    Inventor: Andreas Rusznyak
  • Patent number: 4484147
    Abstract: An improved bootstrapped shunt feedback amplifier is provided in which a minimum number of transistors are arranged to provide a higher slew rate of output voltage at lower power, while minimizing distortion and thus providing a more precise signal replication. Features include the use of three-terminal composite transistors to increase bandwidth and bootstrapping to improve amplifier response while reducing voltage stress on the active devices.
    Type: Grant
    Filed: March 31, 1983
    Date of Patent: November 20, 1984
    Assignee: Tektronix, Inc.
    Inventor: Arthur J. Metz
  • Patent number: 4412183
    Abstract: An AC resistor attenuator with low parasitic capacitance coupling and, thus, a substantially constant attenuation value over a relatively wide frequency range is disclosed. The AC resistor attenuator comprises a first elongate resistor substantially entirely surrounded by a second elongate resistor. The first and second elongate resistors are thermally matched and have a substantially identical resistance profile. The first and second resistors are connected in series. The other ends of the first and second resistors are connected across the source of the signal to be attenuated. The attenuated signal is obtained at the junction between the first and second resistors. Except in the case where fifty percent (50%) attenuation is to be provided, the higher value resistance of the attenuator forms the first resistor and the lower value forms the second resistor.
    Type: Grant
    Filed: October 6, 1980
    Date of Patent: October 25, 1983
    Inventor: Benjamin T. Brodie
  • Patent number: 4390852
    Abstract: A buffer amplifier suitable for use as an input amplifier for an oscilloscope comprises a hybrid FET-bipolar transistor source follower input stage and a complementary emitter follower output stage. Both the input and output stages include bootstraps to eliminate thermal transient response aberrations, to increase input impedance, and to maintain standing current in the output stage. Other attributes include a very short response time for high bandwidth operation, and high linearity.
    Type: Grant
    Filed: April 13, 1981
    Date of Patent: June 28, 1983
    Assignee: Tektronix, Inc.
    Inventor: John L. Addis
  • Patent number: 4371847
    Abstract: A method and apparatus for altering the apparent electrical characteristic of a distributed electrical component in an integrated circuit is disclosed. In one form a distributed load resistor is sunk into a parallel distributed guard resistor. The mutual distributed capacitance between the distributed load resistor and the parallel distributed guard resistor is substantially greater than the distributed capacitance between the distributed load resistor and any other electrical component. A follower circuit for driving the voltage across the parallel distributed guard resistor by the voltage across the distributed load resistor is provided.
    Type: Grant
    Filed: October 6, 1980
    Date of Patent: February 1, 1983
    Assignee: Spectronics, Inc.
    Inventors: James R. Biard, Ben R. Elmer
  • Patent number: 4268796
    Abstract: An a-c linear amplifier with two push-pull-connected output transistors includes an ancillary transistor which, during saturation of one of the output transistors and the simultaneous cutoff of a controlled transistor driving these output transistors through a set of pilot transistors, conducts to maintain the base potential of this controlled transistor at its conduction threshold for preventing a distortion of the end of the flattened peak of the corresponding half-cycle of the output voltage. The ancillary transistor has one of its input leads maintained at a fixed biasing potential and the other of its input leads connected to a point of output-dependent variable voltage that allows its conduction during the flattened peak only.
    Type: Grant
    Filed: March 26, 1979
    Date of Patent: May 19, 1981
    Assignee: SGS-ATES Componenti Elettronici S.p.A.
    Inventor: Sergio Palara
  • Patent number: 4206419
    Abstract: A power amplifier comprises: a complementary symmetry push-pull circuit formed with two complementary transistors mutually coupled at their emitters and having an operating point for Class-A mode operation; a floating power supply having a neutral terminal serving as the output terminal of the power amplifier, a positive and a negative terminal connected respectively to the collectors of the respective transistors; a bootstrapping circuit for driving the mutually coupled emitters in proportion to the potential at the output terminal; and a circuit for negative feedback of signal from the output terminal to the bases of the transistors.
    Type: Grant
    Filed: January 8, 1979
    Date of Patent: June 3, 1980
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Kenji Yokoyama
  • Patent number: 4125814
    Abstract: A switching amplifier includes a grounded collector NPN Darlington amplifier having a main current path connected between a terminal for receiving an operating voltage and an output terminal, and an input base and output emitter electrodes across which a series circuit of the main conduction of an NPN transistor and a floating DC voltage supply are connected. In response to a switching signal applied to its base electrode, the NPN transistor turns on to connect in "bootstrap" the DC voltage supply directly across the base and emitter electrodes of the Darlington amplifier, for turning on and operating the Darlington amplifier at its maximum power and rated voltage or current capability.The field of the invention relates generally to switching amplifiers, and more particularly to high-power switching amplifiers.Many present high-power semiconductor switching amplifiers or circuits include in their output stages a combination of NPN and PNP transistors.
    Type: Grant
    Filed: August 31, 1977
    Date of Patent: November 14, 1978
    Assignee: Exxon Research & Engineering Co.
    Inventor: Richard H. Baker
  • Patent number: 4000474
    Abstract: A bootstrap driver circuit directly coupled to a complementary pushpull output circuit and including a field effect transistor with current unsaturated triode vacuum tube characteristics. The output of the pushpull output circuit is coupled to the drain and source circuits of the driver field effect transistor by means of capacitors. The present invention also discloses a predriver circuit which uses a current unsaturated type field effect transistor and can be directly coupled to the driver circuit.
    Type: Grant
    Filed: June 10, 1975
    Date of Patent: December 28, 1976
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Shigeru Todokoro
  • Patent number: RE29286
    Abstract: A power amplifier includes a bootstrapped driver circuit in which the load element is divided into two parts. A single-ended push-pull circuit provides a feedback to the junction point of those two parts. A resistor element having 0.1 to 10 times the resistance of the load element is connected in parallel with the load element.
    Type: Grant
    Filed: October 4, 1976
    Date of Patent: June 28, 1977
    Assignee: Nippon Electric Company, Limited
    Inventors: Hirokazu Fukaya, Naotoshi Higashiyama