Plural Functions Simultaneously Patents (Class 331/58)
  • Patent number: 8952759
    Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 10, 2015
    Assignee: MediaTek Inc.
    Inventors: Ping-Ying Wang, Kuan-Hua Chao, Jeng-Horng Tsai
  • Publication number: 20030034849
    Abstract: The present invention relates to a ring oscillator stage, comprising delay means (32) having an input and an output, and further comprising adjustable negative resistor means (−RTUNE) coupled to the output of said delay means (32).
    Type: Application
    Filed: August 13, 2002
    Publication date: February 20, 2003
    Inventor: Mihai Adrian Tiberiu Sanduleanu
  • Publication number: 20030034850
    Abstract: The present invention relates to a differential ring oscillator stage, comprising differential delay means (Q1, Q2) having a first input (IN+) and an inverse second input (IN−) and a first output and an inverse second output, a first output buffer means (34a) having its input connected to the first output of said delay means (Q1, Q2), and a second output buffer means (34b) having its input connected to the second output of said delay means (Q1, Q2), and further comprising a first controllable current source means (M6) which is connected to the output (OUT+) of said first output buffer means (34a) and controlled in accordance with the signal from said second output of said delay means (Q1, Q2), and a second controllable current source means (M5) which is connected to the output (OUT−) of said second output buffer means (34b) and controlled in accordance with the signal from said first output of said delay means (Q1, Q2), said controllable current source means (M5, M6) supplying currents t
    Type: Application
    Filed: August 13, 2002
    Publication date: February 20, 2003
    Inventor: Mihai Adrian Tiberiu Sanduleanu
  • Patent number: 4672379
    Abstract: A doppler radar transceiver comprising a transceiving module including a reflex circuit having a single transistor which simultaneously acts as both an oscillator and an amplifier. A capacitor and a resistor are provided in the transistor base element bias circuit to reduce the source impedance of the base bias current to said transistor in the doppler signal frequency band without effecting the radar frequency system of the transceiver.
    Type: Grant
    Filed: December 4, 1985
    Date of Patent: June 9, 1987
    Inventor: Frank W. Bishop
  • Patent number: 4470040
    Abstract: An alarm device comprises a blocking oscillator circuit composed of a transformer and a transistor and a sound emitter using a piezoelectric effect exhibiting element and interposed between one end of the secondary coil of the transformer and a power source, with the other end of the secondary coil connected to the base of the transistor. When the sound emitter receives a slight vibration, it generates an electromotive force, which is applied to the base of the transistor. Consequently, the blocking oscillation circuit oscillates and causes the sound emitter to issue an alarm.
    Type: Grant
    Filed: November 4, 1981
    Date of Patent: September 4, 1984
    Assignees: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventor: Tokishi Kaminishi
  • Patent number: 4160953
    Abstract: A self-oscillation mixer circuit includes a cascade amplifier circuitry which is composed of a first transistor of a common emitter connection having a collector connected to an emitter of a second transistor of a common base connection, a filter circuitry for deriving an intermediate frequency signal and a resonance circuit adapted to resonate at a local oscillation frequency being connected to the collector of the second transistor and a feedback circuitry connected between the resonance circuitry and the emitter of the first transistor.
    Type: Grant
    Filed: March 13, 1978
    Date of Patent: July 10, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Shigeo Matsuura, Toshio Nagashima, Mitsuhisa Shinagawa
  • Patent number: 4053839
    Abstract: A frequency multiplying system and method in which a time varying analog input signal is sampled and stored in a memory matrix at a predetermined rate. The signal thus stored is read out from the memory matrix at a different rate and reconstructed into a time varying analog signal. The storage rates and readout rates are controlled by a command signal generator including a master run-up generator run up at a first run-up rate and reset by the fundamental input frequency, the highest level at the output of the run-up generator being continually stored in a memory circuit. Slave run-up generators which cycle at frequencies corresponding to the storage and reading-out of the sampled information are reset upon coincidence of their levels with the level in the memory connected to the master run-up generator. The command signal generator may be in either digital or analog form employing either counters or integrators as run-up generators. The analog input signal may be processed by either digital or analog means.
    Type: Grant
    Filed: May 29, 1973
    Date of Patent: October 11, 1977
    Inventor: George Knoedl, Jr.