Abstract: Position information estimation in a distributed radio frequency (RF) communications system is provided. Embodiments disclosed herein facilitate high-precision estimations of positions, orientations, velocities, and acceleration of network nodes in a distributed RF network (e.g., including base stations and vehicles, such as aircraft or unmanned aerial systems (UASs)). Modern radio systems must adapt to limited spectral access by reducing spectrum demand and increasing operational efficiency. In this regard, an RF system is provided which simultaneously performs positioning and communications tasks. This system specifically addresses the issue of spectral congestion by employing an extremely efficient positioning strategy and using a joint waveform that simultaneously enables both tasks. This efficiency in turn supports more users in a given frequency allocation.

Abstract: Techniques and architectures for providing FSK signal modulation using mixing for the generation of the two output frequencies are described. In an embodiment, a frequency-shift keying (FSK) transmitter may be operative to provide transmission of wireless signals. The FSK transmitter may include a high-frequency generator to generate at least one high-frequency wave signal based on a fixed frequency signal, a low-frequency generator to generate at least one low-frequency wave signal based on the fixed frequency signal, and at least one mixer to mix the at least one high-frequency wave signal and the at least one low-frequency wave signal to generate a logic signal, the logic signal comprising one of a logic 0 signal or a logic 1 signal based on digital input data.

Abstract: An alternating least square recommendation method, system, and non-transitory computer readable medium, include receiving an existing sparse matrix factorization saved in a data store to incrementally update factorized features when users change ratings of the sparse matrix factorization, determining an update ratio based on the number of changed ratings of the sparse matrix factorization, and updating the users' features by using the existing content ratings of the existing sparse matrix factorization if the update ratio is less than a pre-defined threshold ratio.

Abstract: Embodiments of the disclosure relate to combining uplink radio frequency (RF) communications signals in a remote unit in a wireless distribution system (WDS) using a differential mixer. A remote unit in a WDS receives a first uplink RF communications signal(s) and a second uplink RF communications signal(s). A differential mixer, which is typically configured to combine a pair of differential input signals, is controlled to combine the first uplink RF communications signal(s) and second uplink RF communications signal(s) without requiring the first uplink RF communications signal(s) and second uplink RF communications signal(s) to be converted into the pair of differential input signals. As a result, it may be possible to eliminate a signal combiner and a BalUn circuit from the remote unit, thus helping to save component costs and board space, and to reduce insertion loss and ripple to improve uplink signal quality in the remote unit.

Abstract: Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal.

Abstract: A code generator, for providing a PRN sequence in a GNSS receiver, has the capability to store an internal status at any given point of the generated sequence. The stored status can be reloaded in the generator, upon an external command, or after a given number of generation cycles, thus slewing the phase of the generated PRN sequence to the value corresponding to the stored status. A parallel-correlation GNSS receiver includes one or more slewable code generators, for successively generating local replicas of GNSS PRN sequences, having different code phases, corresponding to a plurality of candidate signals of different code and Doppler shifts. Each time the code generator must switch from one candidate to a second, it is preemptively controlled or programmed, while generating the code for the first candidate, to store the internal status at the phase point almost aligned with the start of the PRN sequence for the second candidate.

Abstract: A frequency-shift keying (FSK) receiver includes an injection-locking oscillating circuit to receive a FSK input signal, and a phase detecting circuit. The injection-locking oscillating circuit outputs a locked signal having a phase that tracks a phase of the FSK input signal. A difference between the phases of the FSK input signal and the locked signal is associated with a difference between a frequency of the FSK input signal and a free-running frequency of the injection-locking oscillating circuit. The phase detecting circuit receives the FSK input signal and the locked signal, and outputs a baseband logic signal according to the difference between the phases of the FSK input signal and the locked signal.

Abstract: A modulator for an electrical signal comprises a data input port and a clock frequency input port. The modulator also comprises a first phase shifter for subjecting input clock frequency signals to a phase shift and adapted to keep the phase of an input clock frequency signal aligned with the phase of a data stream which is input at the data input port. The modulator also comprises a first XOR gate with an output port, to which first XOR gate said input ports of the modulator are connected, by means of which a BPSK signal is created at the output port when a first data stream is connected to the data input port and a first clock frequency signal is connected to the clock frequency input port.

Abstract: An integrated circuit device has a modulator module that provides a modulation signal comprising one frequency keyed on and off, or alternating between two or more different frequencies or phases that are selected based upon a modulator signal. The one or more frequencies or phases may be selected from a plurality of frequency sources. Switching the one frequency on or off, or between the at least two different frequencies or phases may be synchronized with one or both of the two or more different frequencies or phases so that “glitches” or spurs are not introduced into the modulation signal. The integrated circuit device may also comprise a processor, memory, digital logic and input-output. Frequency sources may be internal to the digital device or external. The modulator signal may comprise serial data generated from the digital logic and/or processor of the digital device.

Abstract: An apparatus and method for digital up converting in a mobile communication system are provided. The apparatus includes a Selectable Input Logic (SIL), a Scalable Clock Distribution Logic (SCDL), a filter logic, and a mixer logic. The SIL performs decimation at a decimation rate. The SCDL controls a clock frequency. The filter logic performs channel filtering for the decimated signal, and performs interpolation at an interpolation rate variable. The mixer logic up-converts the signal provided from the filter logic.

Abstract: A method and system for a frequency shift key demodulation is provided. The system includes a counting block for counting a reference clock within a window defined by a modulated signal, a detector for comparing a count value output from the counting block with digital multi-level thresholds and outputting baseband data based on the comparison, and a configurations block for configuring at least one of the counting block and the detector. The method includes counting a reference clock within a window defined by the FSK modulated signal and outputting a count value as a result of the counting, and comparing the count value with multi-level thresholds to output baseband data based on the comparison.

Abstract: A method, system and digital modulator for modulation are provided The modulator includes a dividing mechanism for dividing a reference clock by a divide value to produce a modulated signal associated with at least one input data, and a control unit for providing at least one divide sequence to the dividing mechanism. The at least one divide sequence includes a sequence of one or more divide values. The divide value of the divide sequence is configurable and selectively provided to the dividing mechanism based on the at least one input data. The method includes configuring at least one divide sequence including a sequence of one or more divide values, and selecting a divide value from the at least one divide sequence based on at least one input data. The method includes dividing a reference clock by the selected divide value and generating a modulated signal based on the divide operation.

Abstract: A GMSK modulator includes a dual-port memory, an address generator and a signal provider, where the dual-port memory respectively outputs in-phase and quadrature phase waveform data to first and second ports in response to in-phase and quadrature phase waveform address signals, the address generator generates the in-phase and quadrature phase waveform address signals based on a differential encoded bit stream, the signal provider selects one of the in-phase and the quadrature phase waveform data in response to the differential encoded bit stream, and outputs continuous GMSK in-phase and quadrature phase channel signals, and the redundancy of the memory that stores the GMSK in-phase and quadrature phase waveform data may be reduced using the dual-port memory so that the size of the memory may be reduced.

Abstract: A method, system and digital modulator for modulation are provided The modulator includes a dividing mechanism for dividing a reference clock by a divide value to produce a modulated signal associated with at least one input data, and a control unit for providing at least one divide sequence to the dividing mechanism. The at least one divide sequence includes a sequence of one or more divide values. The divide value of the divide sequence is configurable and selectively provided to the dividing mechanism based on the at least one input data. The method includes configuring at least one divide sequence including a sequence of one or more divide values, and selecting a divide value from the at least one divide sequence based on at least one input data. The method includes dividing a reference clock by the selected divide value and generating a modulated signal based on the divide operation.

Abstract: A tri-state pulse density modulator includes a first switch device coupled to a high voltage, and a second switch device coupled to a low voltage. An adder receives a pulse density modulation (PDM) input signal and a latched input signal to generate an output sum signal and a carry signal. A latch module coupled with the adder latches the output sum signal with a clock signal to generate the latched input signal. A control circuit module responsive to the carry signal for selectively turns off the first and second switch devices to generate the PDM output signal at a tri-state voltage between the first and second voltages, or turns on the first or second switch device to generate the PDM output signal at the first or second voltage, respectively. Thus, the PDM output signal only switches between the tri-state voltage and either the first voltage or the second voltage.

Abstract: This disclosure is directed to digitally implemented GMSK modulation techniques. The digital GMSK modulation techniques make use of a lookup table (LUT) and mapping logic to digitally generate GMSK waveforms. The mapping logic can significantly reduce the size of the LUT, and thereby reduce memory requirements needed for effective digitally implemented GMSK modulation.

Abstract: A cost-effective continuous phase logic-based modulator and demodulator are provided to allow communications using binary frequency shift keying (BFSK) as well as M-ary FSK techniques. The modulator of the 1-bit precision modem architecture is based on a 1-bit precision numerically controlled oscillator (NCO), which provides complete programmability with respect to a frequency of the 1-bit precision logic-based modulator and/or demodulator. The 1-bit precision NCO includes an adder and a phase accumulator register which is clocked by a master clock signal. A two-input multiplexer has a single bit symbol value to generate BFSK, or larger input multiplexers can be implemented to provide M-ary FSK. The output of the 1-bit precision NCO is upconverted to an intermediate frequency using a simple logic function, i.e., XNOR logic. Alternatively, the intermediate frequency may be arrived at without the need for upconversion by directly utilizing a harmonic alias at a desired IF frequency.

Abstract: A high-speed power-efficient coded M-ary Frequency-Shift Keying (M-ary FSK) modulator. The modulator includes a coding logic, which generates (M/2) Gray code signals in accordance with an (N−1) bits control signal; and (M/2) switching oscillators. Each switching oscillator includes: a composite crystal resonator with a first end and a second end; a first switch, which is controlled by Gray code signals, with one end connected to the first end of the composite crystal resonator, and the other end grounded via an equivalent negative resistance circuit; a second switch, which is controlled by serial data, with one end connected to the second end of the composite crystal resonator, and the other end grounded; and a capacitor, with one end connected to the second end of the composite crystal resonator, and the other end grounded.

Abstract: A frequency shift modulation circuit has a direct digital synthesizer DDS and a phase-locked loop PLL. DDS stores output signal frequency data in a plurality of registers. DDS selects the register storing the frequency data in accordance with a frequency shift keying FSK data signal whose voltage was controlled by a comparator. A signal output from DDS is input to PLL. PLL generates a signal whose phase is synchronized with the signal supplied from DDS, and outputs a frequency shift signal having a shift amount corresponding to the digital value of the FSK data signal. The FSK data signal is input via a balance adjustor to PLL so that a large frequency shift is possible. Since the frequency data is set to DDS, a stable modulation even for a low frequency is possible. In this manner, the frequency of an output signal can be stably shifted.

Abstract: A high-speed power-efficient coded M-ary Frequency-Shift Keying (M-ary FSK) modulator. The modulator includes a coding logic, which generates (M/2) Gray code signals in accordance with an (N−1) bits control signal; and (M/2) switching oscillators. Each switching oscillator includes: a composite crystal resonator with a first end and a second end; a first switch, which is controlled by Gray code signals, with one end connected to the first end of the composite crystal resonator, and the other end grounded via an equivalent negative resistance circuit; a second switch, which is controlled by serial data, with one end connected to the second end of the composite crystal resonator, and the other end grounded; and a capacitor, with one end connected to the second end of the composite crystal resonator, and the other end grounded.

Abstract: To provide a new data transmission system between a game device and related peripheral devices, and a device using same. Serial transmission data is divided into an odd-numbered bit sequence and an even-numbered bit sequence. Each bit of the odd-numbered bit sequence data is distributed respectively between pulses of a first pulse sequence signal having a constant interval, thereby forming a first pulse sequence signal (SDCKA). Each bit of the even-numbered bit sequence data is distributed respectively between pulses of a second pulse sequence signal having a constant interval, thereby forming a second pulse sequence signal (SDCKB). The respective time axes are adjusted such that the clock component of the first pulse sequence signal is located in the data section of the second pulse sequence signal, the clock .component of the second pulse sequence signal is located in the data section of the first pulse sequence signal.

Abstract: The present invention teaches a system for selectably oscillating at a first or a second oscillating frequency. The system comprises an oscillator for providing an oscillating output. Moreover, the system comprises a switching device for selecting a first or a second impedance in response to a select signal having a voltage. Each of the first and second impedances are fixed independently of the select signal voltage such that the oscillating output oscillates at the first oscillating frequency when the first impedance is provided and oscillates at the second oscillating frequency when the second impedance is provided.

Abstract: A method for generating digital carrier signals for application as the carrier to a digital modulator includes providing a first repeating sequence of complex values occurring at a given sample rate and upsampling these values to a higher sample rate. A second repeating sequence of complex values is provided, wherein respective complex values in the second repeating sequence occur at the higher sample rate. The second sequence of complex values is employed to modulate the upsampled first sequence of complex values and thereby provide the complex carrier signal.

Abstract: The present invention teaches a system for selectably oscillating at a first or a second oscillating frequency. The system comprises an oscillator for providing an oscillating output. Moreover, the system comprises a switching device for selecting a first or a second impedance in response to a select signal having a voltage. Each of the first and second impedances are fixed independently of the select signal voltage such that the oscillating output oscillates at the first oscillating frequency when the first impedance is provided and oscillates at the second oscillating frequency when the second impedance is provided.

Abstract: A cost-effective continuous phase logic-based modulator and demodulator are provided to allow communications using binary frequency shift keying (BFSK) as well as M-ary FSK techniques. The modulator of the 1-bit precision modem architecture is based on a 1-bit precision numerically controlled oscillator (NCO), which provides complete programmability with respect to a frequency of the 1-bit precision logic-based modulator and/or demodulator. The output of the 1-bit precision NCO is upconverted to an intermediate frequency using a simple logic function, i.e., XNOR logic. The undesirable portion of the upconverted signal may be suppressed using I/Q image rejection, and/or an appropriate bandpass filter may be used. A band limited, hard limited signal at the high IF is presented to the 1-bit precision demodulator as a receive IF signal, which is treated as a 1-bit quantization of the signal. The receive IF signal is digitally down-converted to a low IF signal to produce an alias signal at the low IF frequency.

Abstract: A cost-effective continuous phase logic-based modulator and demodulator are provided to allow communications using binary frequency shift keying (BFSK) as well as M-ary FSK techniques. The modulator of the 1-bit precision modem architecture is based on a 1-bit precision numerically controlled oscillator (NCO), which provides complete programmability with respect to a frequency of the 1-bit precision logic-based modulator and/or demodulator. The 1-bit precision NCO includes an adder and a phase accumulator register which is clocked by a master clock signal. A two-input multiplexer has a single bit symbol value to generate BFSK, or larger input multiplexers can be implemented to provide M-ary FSK. The output of the 1-bit precision NCO is upconverted to an intermediate frequency using a simple logic function, i.e., XNOR logic. Alternatively, the intermediate frequency may be arrived at without the need for upconversion by directly utilizing a harmonic alias at a desired IF frequency.

Abstract: The present invention teaches a system for selectably oscillating at a first or a second oscillating frequency. The system comprises an oscillator for providing an oscillating output. Moreover, the system comprises a switching device for selecting a first or a second impedance in response to a select signal having a voltage. Each of the first and second impedances is fixed independently of the select signal voltage such that the oscillating output oscillates at the first oscillating frequency when the first impedance is provided and oscillates at the second oscillating frequency when the second impedance is provided.

Abstract: A frequency generating circuit scales a warp range of a frequency signal. The frequency generating circuit includes a first frequency signal (10) having a first offset signal with a first frequency relationship to the first frequency signal, and a second frequency signal (14). A frequency scaling element (16) receives the first frequency signal (10) and second frequency signal and provides a third frequency signal, such that the third frequency signal includes the first offset signal having a second frequency relationship to the third signal. A switch (54), has a control input (74), a first input for receiving the first frequency signal, a second input operably coupled to the frequency scaling element (16, 42) for receiving the third frequency signal and an output (76) operably coupled to the first input or the second input dependent upon a control signal applied to the control input (74).

Abstract: A modulation system is provided with a data analyzer detecting input of a modulated data and a modulation clock signal and latching and detecting an edge of the modulated data, in response to the modulated data and the modulation clock signal, a signal controller, responsive to an output of the data analyzer, carrying out an operation process with respect to the frequency deviation data and carrying out one of a frequency deviation amplitude control operation and a frequency deviation time control operation, a digital-to-analog converter converting an output of the signal controller into an analog signal, and a transmitting unit transmitting an output of the digital-to-analog converter.

Abstract: In order to provide a digital GMSK modulator operating sufficiently stably without aliasing distortion even with a sampling rate of twice of that of input signal, a quasi-GMSK modulator of the invention comprises: integration means (105) for integrating an input signal; filtering means (106, 107) for performing a digital Gaussian filter manipulation of output of the integration means with a low sampling rate of twice or more of a data rate of the output of the integration means; a phase modulator (107, 108 and 111) for obtaining a continuous wave phase-modulated with output of the filtering means; and a limiter (112) for limiting amplitude of the continuous wave within a fixed value.

Abstract: A frequency modulation circuit includes an emitter-follower connection transistor (2), having a base supplied with a modulation signal, for generating an emitter voltage which is in proportion to a modulation signal level; and an integrated mono-stable multi-vibrator (1) having an inversion trigger terminal ((A*)), a non-inversion trigger terminal (B), a resister/capacitor terminal (R.sub.X /C.sub.X), a capacitor terminal (C.sub.X), complementary output terminals (Q, (Q*)), and the like. The inversion trigger terminal ((A*)) is connected to the complementary output terminal (Q), the non-inversion trigger terminal (B) is connected to a partial voltage point of partial voltage resistors (10, 11), the capacitor/resistor terminal (R.sub.X /C.sub.X) is connected to the emitter of the transistor (2) through a resistor (3) and connected to the capacitor terminal (C.sub.

Abstract: A frequency synthesizing circuit has an input on which a bit flow is received, and an output on which a data-modulated output signal is supplied. The circuit moreover comprises a crystal oscillator supplying a reference clock signal, a phase-locked loop (PLL) having a VCO and a phase detector. The phase detector compares the data-modulated output signal with the reference clock signal and, in response to this, supplies an error signal by means of which the VCO output frequency is controlled. A compensation circuit, which receives a measure of the bit flow received, compensates the data-modulated output signal in the phase-locked loop in response to this before it is supplied to the phase detector.

Abstract: In a modulating system, a converting unit generates first and second quadrature signals based on a transmission data signal in synchronous with a transmission clock signal. First and second filters perform band limitation to the first and second quadrature signals to generate first and second band-limited quadrature signals. An oscillator generates a sine wave signal and a phase shifter phase-shifts the sine wave signal from the oscillator to generate first and second phase-shifted sine wave signals. A phase difference between them is .pi./2, and the first phased-shifted sine wave signal precedes the second phased-shifted sine wave signal in the phase. First and second multipliers multiply the first and second phase-shifted sine wave signals by the first and second band-limited quadrature signals to generate first and second multiplied signals, respectively. An adder synthesizes the first and second multiplied signals to generate an synthesis signal.

Abstract: The FSK modulator for modulating binary data of the present invention has an object to provide an FSK modulator which can operate at a stable frequency also when a discontinuous data row is entered. The FSK modulator comprises a PLL (phase locked loop) in which binary data is entered at two types of voltage levels different each other, an oscillation output of the PLL treated as output data of the modulator, allows a voltage at an almost-intermediate level to the PLL instead of binary data when the binary data has not been entered.

Abstract: A signal FSK-modulated with a binary data signal has first signal portions representing first logical level data contained in the binary data signal and second signal portions representing second logical level data contained in the binary data signal. Each of the first signal portions has a first frequency and lasts for a first time period and each of the second signal portions has a second frequency and lasts for a second time period. These first and second time periods are determined such that a number of cycles of the FSK-modulated signal appearing in each of the first time periods is equal to a number of cycles of the FSK-modulated signal appearing in each of the second time periods.

Abstract: A method and apparatus for digitally phase modulating and frequency upconverting communication signals to an intermediate frequency, producing the IF output with only digital hardware and without the use of digital to analog converters, analog multipliers (mixers) or power combiners. A digital phase modulator provides an in-phase and a quadrature output, each of which is coupled to one input of a relatively simple multi-bit to single-bit delta-sigma data converter. The output from the converter is a pair of single-bit digital output signals. Each such single-bit output is inverted and both the inverted single-bit output and the non-inverted single-bit output of both the in-phase and the quadrature outputs are coupled to a 4:1 multiplexer. One of these four inputs is then selected by a modulo-4 counter. The modulo-4 counter is incremented at a rate that is selected based upon the desired IF frequency.

Abstract: An apparatus (500) for generating first and second output signals having predetermined frequency shifts relative to a frequency provided by a reference signal is included in a system comprising a phase-locked loop (206) coupled to the reference signal for generating the first and second output signals. The apparatus (500) includes pulse deletion circuitry (204) coupled to the reference signal and the phase-locked loop (206) for deleting pulses from the reference signal at a first deletion rate to generate the first output signal and for deleting pulses from the reference signal at a second deletion rate to generate the second output signal.

Abstract: In the modulation and demodulation of a plurality of frequency separated channels on a radio frequency carrier by digitally coded speech or data, the speech or data is modulated on a digitally generated sub-carrier by quadrature phase shift keying and after conversion to analogue form the modulated sub-carrier is mixed with an RF carrier of fixed frequency to produce the signal for transmission. Reception and demodulation of the transmitted signal are effected by the reverse processes. Frequency multiplication is effected after the digital to analogue conversion by producing analogue samples of very short duration and applying them to a suitable filter. Frequency division during the analogue to digital conversion is effected by sub-sampling.

Abstract: An apparatus for generating output signals having predetermined frequency shifts relative to a frequency provided by a reference signal is included in a system (500) comprising a phase-locked loop (206) coupled to the reference signal for generating the first and second output signals. The apparatus comprises pulse addition circuitry (204) coupled to the reference signal and the phase-locked loop (206) for adding pulses to the reference signal at a first cyclical rate to generate the first output signal and for adding pulses to the reference signal at a second cyclical rate to generate the second output signal.

Abstract: An A/D converter (1) converts analog modulation signals, such as video signals and audio signals, into digital modulation signals. A center frequency data setting circuit (6) outputs center frequency data for setting the center frequency of an FM wave. An operation unit (5) outputs such addition data, on the basis of the center frequency data and average frequency data from a counter circuit (4) as will make the average frequency of the FM wave substantially identical with the center frequency that has been set. An adder (2) adds the digital modulation signals and the addition data, and outputs addition digital signals. A DDS (3) accumulates an addition digital signal in every sampling period supplied from a reference oscillator (7). In the ROM (32) of the DDS (3) are stored sine wave data and the ROM (32), having the accumulated signals as its address input, outputs the sine wave data.

Abstract: A modulator is adapted for use in a transmitter of an information transmission signal in which the information is in the form of a frequency shift keyed code. The signal is centered on a fictional carrier frequency fc, on either side of which are emitted two actual frequencies separated from the frequency fc by .DELTA.f, according to whether the binary information has a high value (+1) or a low value (-1). A first generator (1) creates carrier signals in the form of sin(2.pi.f.sub.c t) and cos(2.pi.f.sub.c t). A second generator (6) creates, as a function of the information, modulation signals of the form sin(2.pi..DELTA.ft) and cos(2.pi..DELTA.ft) which are mixed with the carrier signals. At each transition of the information, first phase shifting means (8,14) modify by k.pi. the phase of one of the modulation signals.

Abstract: A digital FSK transmitter utilizing a clock feedback signal driving an accumulator to operate a pair of registers having a pair of preset numbers stored therein to selectively add said numbers through a binary adder to the accumulator to output the FSK signal thereby.

Abstract: A modulator capable of providing a fractional sample or symbol 995486 time employs a decimation counter (23) responsive to a clock having a frequency equal to M/N.times.(data symbol clock), where M is an interpolation factor and N is a decimation factor, for generating a data symbol clock to select FSK symbols from a sampled data array (21). A multiplier (26) receives the FSK symbols and multiplies the symbols by a weighting factor determined by the decimation counter. When the decimation counter wraps around due to a modulo M operation, a fractional weight is calculated for the current FSK symbol, then a new FSK symbol is selected, and then a fractional weight is calculated for the new FSK symbol. When the decimation counter has not wrapped, the full weighting, N, is output for the current FSK symbol.

Abstract: A method and apparatus for generating an output signal (616) having a pre-determined frequency shift relative to the frequency of a reference signal from a reference frequency generator (202) comprise a digital phase-locked loop (206) coupled to the reference signal for generating the output signal (616). The method and apparatus further comprise adding pulses to the reference signal in a pulse addition circuit (304), the pulses recurring at a first cyclical rate determined by a microprocessor (702). The method and apparatus further comprise concurrently subtracting pulses from the reference signal in a pulse subtraction circuit (302) at a second cyclical rate.

Abstract: A modem for use in a simulcast paging system includes a modulator (26) and a demodulator (30), both of which produce very low jitter, enabling the modem to be used at data rates well in excess of 1,200 baud. Both the modulator and the demodulator are implemented in software using a digital signal processor (DSP) (66). The modulator initially samples a non-return-to-zero (NRZ) input at a sample rate of 19.2 KHz, interpolates transitions between logic levels, and produces a frequency shift keyed (FSK) modulated signal at a center frequency different than that used for transmitting the modulated signal. Using an interpolation timer that responds to changes in logic level on the input, the modulator changes the frequency of the FSK modulated signal at the appropriate time with much greater accuracy than would be possible without interpolation. The FSK modulated signal is filtered to substantially attenuate frequencies outside a 3 KHz bandwidth, producing a filtered signal.

Abstract: An MSK modulator providing a high precision digital phase adjustment with a simple circuit structure. A sample data of a sine wave or cosine wave is read from a memory at an address calculated from an initial address value. The initial address value is set in accordance with the amount of phase to be adjusted. A predetermined number of sample data read from the memory is held, outputted in a predetermined order, and converted into an analog signal. The phase of the converted analog signal is adjusted, and thereafter multiplied by an input baseband signal. The multiplied result is outputted as a modulation signal.

Abstract: The present invention provides a modulator/generator circuit which includes the following features: a 1200 baud 4-phase differential phase shift keying (DPSK) modulator, a 300 baud frequency shift keying (FSK) modulator, a dual tone multi-frequency (DTMF) generator and 2100/2225 Hz answer tone generators. The DPSK modulator utilizes time-domain filtering techniques. It includes a spectrum controller that shapes the in-band frequency spectrum and attenuates the adjacent channel frequency components to eliminate the conventional requirement of band-pass filters after the modulator. The FSK modulator also utilizes a spectrum controller which, during each data transition, sends out six intermediate frequencies to smooth the frequency changeover. DTMF generation is accomplished by multiplexing two sine-wave counters into a DPSK sinewave look-up ROM.

Abstract: A control circuit (10) controls a voltage controlled oscillator (15) to cause the signal at the output of the oscillator to have slopes of frequency variation in accordance with biphase encoded data to be transmitted. The control circuit (10) limits abrupt frequency shifts in the oscillator output signal by inverting a sign multiplying the slope of frequency variation, utilizing an amplifier (50) with a controllable inversion state, in response to whether the state of the data to be transmitted, and a state, indicative of whether a frequency control voltage exceeds a zero threshold at sampling instants synchronous with the biphase data, are the same or different.

Abstract: In a direct sequence spread spectrum modulation apparatus, the data of predetermined bit inserted in a phase shift time data period provided between the respective PN codes, or a predetermined bit at the latter half portion of the PN code, is phase shifted in accordance with the data to be modulated. The thereby conducts spread spectrum and data modulation.

Abstract: The analog data representing a value measured of a product by means of a measuring device such as a vernier calipers is converted into digital data by an analog-to-digital converter. A CPU incorporates the digital data into a data message. The CPU is driven by a clock signal output from a quartz crystal oscillator. A first frequency divider divides the clock signal, thus generating a signal of a first frequency, and a second frequency divider divides the clock signal, thereby generating a signal of a second frequency. During the duration of each digital data signal at the "0" (low) level, the CPU generates a signal at the "low" or "high" level, in accordance with the signal generated by the first frequency divider. Similarly, during the duration of each digital data signal at the "1" (high) level, the CPU generates a signal at the "low" or "high" level, in accordance with the signal generated by the second frequency divider. The signals generated by the CPU are supplied to a transmitter.