Abstract: A differential positive coefficient weighted quadrature modulator is actuated responsive to quadrature clock signals and positive digital modulation signals input to the modulator. The modulator includes an I-channel positive coefficient weighted modulator (PCWM) and a Q-channel PCWM. The I-channel PCWM has differential output nodes configured to output a differential I-channel signal responsive to the state of first and second positive digital modulation signals and first and second complimentary quadrature clock signals input to the I-channel PCWM. The Q-channel PCWM has differential output nodes configured to output a differential Q-channel signal responsive to the state of third and fourth positive digital modulation signals and third and fourth complimentary quadrature clock signals input to the Q-channel PCWM.

Abstract: A bi-polar modulator that can perform quadrature modulation using amplitude modulators is described. In one design, the bi-polar modulator includes first and second amplitude modulators and a summer. The first amplitude modulator amplitude modulates a first carrier signal with a first input signal and provides a first amplitude modulated signal. The second amplitude modulator amplitude modulates a second carrier signal with a second input signal and provides a second amplitude modulated signal. The summer sums the first and second amplitude modulated signals and provides a quadrature modulated signal that is both amplitude and phase modulated. The first and second input signals may be obtained based on absolute values of first and second modulating signals, respectively. The first and second carrier signals have phases determined based on the sign of the first and second modulating signals, respectively. Each amplitude modulator may be implemented with a class-E amplifier.

Abstract: A modulation/demodulation apparatus according to an embodiment of the present invention includes a sine wave generating circuit configured to output two sine waves which are orthogonal to each other and have equal amplitude, an orthogonal modulator connected to the sine wave generating circuit and configured to modulate the sine waves to generate a modulated signal, a detecting section configured to detect amplitude fluctuation in the modulated signal, a multiplying section configured to multiply the modulated signal and the amplitude fluctuation detected by the detecting section together, and an orthogonal demodulator configured to demodulate the modulated signal multiplied with the amplitude fluctuation by the multiplying section to generate a demodulated signal.

Abstract: The present disclosure relates to circuits and methods for improving the performance of a polar modulator by maintaining the input to a phase modulator.

Abstract: Disclose is a modulation method that transmits n bits per modulation symbol, comprising the steps of: (a) generating a constellation of which 2n constellation points are arranged to be angular point of equilateral triangle; (b) generating a modulation symbol by mapping the constellation point with digital signal. According to the present invention, average power consumed by constellation points can be reduced by using equilateral triangular constellation.

Abstract: Without influenced by a symbol rate of a baseband signal, a power consumption is kept low approximately to zero in a phase shifter. In order to control an output signal of an orthogonal modulator, in a phase shifter adding phase to I signal and Q signal inputted to the orthogonal modulator, interchange of the I signal and the Q signal, or interchange of polarities of I signal and Q signal respectively, interchange of both of the above is performed.

Abstract: Apparatus and methods for improving the performance of a modulator, typically in an I/Q modulation system, are described. Input I and Q current modulation signals may be processed to generate a sign signal and a magnitude signal, with the magnitude signal selectively applied to the inputs of a mixer based on the sign signal so as to generate respective I and Q modulation signal components. These may then be combined to generate a composite modulation signal.

Abstract: A vector signal generator with direct RF signal synthesis is disclosed. The vector signal generator comprises an RF signal synthesizer, a switch, and a memory. The RF signal synthesizer is configured for converting baseband IQ signals into a modulated digital RF signal. The RF signal synthesizer is connected to an I input, a Q input, a clock input, a control input, and an output, where the clock input is a clock input of the vector signal generator, the control input is a control input of the vector signal generator, and the output is an RF signal output of the vector signal generator. The switch is configured for selecting a source of IQ signals and is connected to an external I input, an external Q input, a stored signal I input, a stored signal Q input, the control input, an I output, and a Q output. The external I input and external Q input are external IQ inputs to the vector signal generator and the I output and the Q output are connected to the I input and the Q input of the RF signal synthesizer.

Abstract: A method and apparatus for compensating for a mismatch in a radio frequency (RF) quadrature transceiver using a direct-conversion scheme is provided. The method includes setting an amplification gain for a baseband quadrature signal to be larger than an amplification gain for a baseband in-phase signal in a reception module; receiving only a baseband in-phase signal in a transmission module; and compensating for a phase mismatch on a basis of a signal output from a quadrature output port. The apparatus includes a phase mismatch compensator which sets an amplification gain for a baseband quadrature signal to be larger than an amplification gain for a baseband in-phase signal in a reception module, inputs only a baseband in-phase signal to a transmission module, and compensates for a phase mismatch on a basis of a signal output from a quadrature output port.

Abstract: An apparatus and method for generating piecewise linear phase transitions during a phase transition interval of a first signal to control controlling the phase/frequency of a second signal. The initiation point, duration and shaping parameters of the piecewise linear phase transitions are selected to control adjacent channel emissions in the second signal.

Abstract: Polar feedback architecture. A polar modulator, as may be implemented within a transmitter module, of a communication device includes feedback. This feedback involves monitoring of phase information and magnitude/amplitude information of an output signal generated by the polar modulator. The output signal can be a radio frequency (RF) signal such as may be transmitted via a communication channel within a communication system. A baseband processing module processes the monitored phase information and magnitude/amplitude information to perform adjustment of a phase modulator and/or other components within the polar modulator.

Abstract: An integrated circuit device has a modulator module that provides a modulation signal comprising one frequency keyed on and off, or alternating between two or more different frequencies or phases that are selected based upon a modulator signal. The one or more frequencies or phases may be selected from a plurality of frequency sources. Switching the one frequency on or off, or between the at least two different frequencies or phases may be synchronized with one or both of the two or more different frequencies or phases so that “glitches” or spurs are not introduced into the modulation signal. The integrated circuit device may also comprise a processor, memory, digital logic and input-output. Frequency sources may be internal to the digital device or external. The modulator signal may comprise serial data generated from the digital logic and/or processor of the digital device.

Abstract: An accurate total error rate performance can be measured using a computed error vector magnitude (EVM) per stream. Using this EVM, the receiver or the transmitter can advantageously generate an optimized modulation and coding scheme (MCS) that corresponds to a specific number of streams, modulation and coding rate for the transmitter. For example, the receiver can compute an SNR from the EVM and then use an SNR vs. MCS table to determine the optimized MCS. In contrast, the transmitter can receive an EVM-to-RSSI mapping and an EVM-to-MCS mapping from the receiver. These mappings and an EVM can facilitate selecting the optimized MCS.

Abstract: Apparatus and methods for adjusting spectral characteristics of a polar modulation signal in a polar modulator are described. A detection circuit is configured to determine when an FM signal component of the modulation signal exceeds a threshold value. The output of the detection circuit is coupled with FM and AM mapping circuits to selectively map the FM signal component and an AM signal component of the modulation signal to mapped signals, thereby reducing FM deviation.

Abstract: A switching circuit comprising: first and second steering switches operable to make or break a path between first and second terminals thereof, and each steering switch further having a control terminal for controlling the switch, the first and second steering switches having their control terminals driven by first and second switching signals, the first and second switching signals having a first frequency and the second switching signal being in anti-phase with the first switching signal and a first chopping switch operable to make or break a path between first and second terminals thereof and being connected in series with at least one of the first and second steering switches and receiving at its first terminal an input to be modulated, wherein the control terminal of the chopping switch is driven by a first switching control signal such that the chopping switch is non-conducting while the first and second steering switches are changing between being conducting and being non-conducting.

Abstract: Compensating for wideband quadrature imbalance error by introducing inverse complex inputs to phase quadrature estimator filters to generate estimated quadrature distortion; summing estimator quadrature distortion with a delayed version of the actual complex input to obtain estimated quadrature output; comparing the output with the true output to obtain residual quadrature imbalance error; applying a least mean square to the inverse input and imbalance residual error to obtain an updated estimate of filter coefficients; updating the filter coefficients of the phase quadrature estimator; and updating the filter coefficients of a phase quadrature compensator with the filter coefficients of the phase quadrature estimator to obtain a quadrature output pre-compensated for quadrature imbalance error.

Abstract: A frequency transposition device including an input terminal for receiving an incident signal SI and a modulator of the one-bit delta-sigma type MDU connected to the input terminal. A generator MGN provides a periodic auxiliary signal SAX with a frequency equal to a desired transposition frequency. A frequency transposer of the Gilbert cell type has a signal input BES connected to the output of the generator, a control input BCO connected to the output of the delta-sigma modulator MDU, and an output BS delivering a transposed signal STR.

Abstract: A simple, interference-free digital phase modulator is to be provided. To this end, the phase modulator is provided with a counter for outputting a counter signal on the basis of a predetermined clock signal and a comparator, which receives a current counter state from the counter, in order to record a digital input signal. The comparator compares the input signal with the current counter state on the basis of a predetermined allocation table and resets the counter, if the input signal corresponds to a counter state assigned via the allocation table. A predetermined signal value of the output counter signal is herewith phase-modulated as a function of the input signal. As only one phase position is generated with the circuit at any point in time, interferences, which are produced by the digital phase modulator itself, are significantly less.

Abstract: DQPSK modulator control is provided using a single monitor photodiode with a selectively injected dither tone. The dither tone signal is sequentially injected into arm modulators and/or to a modulator driver port in time slots. A tapped signal at the output of the modulator is monitored synchronously with injected dither (I arm, Q arm, or phase modulator in third slot). The recovered dither output from a single photodiode is processed in the same sequence as the dither injection to adjust the bias to the optimal point: I-arm at the null point, Q-arm at the null point, and phase modulator at the quadrature point. This technique can be used for any control where the rate of change of the monitored condition due to systemic or environmental conditions (e.g., temperature, aging, etc.) is slow enough to allow time slot dither injection, monitor, and control.

Abstract: A Phased Locked Loop (PLL) circuit includes: a clock signal generating unit for generating a first clock signal and a second clock signal of which the phase differs from the first clock signal by ?/2; a computing unit for computing first phase comparison results showing the results of comparing the phases of a signal wherein the first clock signal is subjected to phase shifting with the PSK modulation signal and second phase comparison results showing the results of comparing the phases of a signal wherein the second clock signal is subjected to phase shifting with the PSK modulation signal based on first and second parameters, the first clock signal, the second clock signal, and the PSK modulation signal; a control direction setting unit for virtually controlling the control angle; a parameter control unit; and a reading control unit for controlling the timing of reading data from the PSK modulation.

Abstract: A modulator for radio-frequency signals designed an entirely digital modulator has two mixer stages connected in series. The first mixer stage implements with a relatively low first sample rate a frequency mixing with a first oscillator frequency that is adjustable with high precision. The second mixer stage implements a frequency mixing with a significantly higher second sample rate and with a relatively coarsely adjustable second oscillator frequency. The downstream second mixer stage, in the case of a single mixer stage, the mixer stage, has at least two phase accumulators that are incremented with the higher second sample rate but with different incremental values. The output signal of at maximum one of the phase accumulators is evaluated at any point in time.

Abstract: Modulator system (1) comprising modulators (2, 3, 4) for modulating input signals (A) according to different modulation schemes (8PSK, GMSK) cause discontinuities in the output signals (F) when switching between the schemes. By providing the modulator systems (1) with compensators (13, 22-26) for compensating amplitudes/phases of the output signals (F) of the modulator system (1) for discontinuities, these discontinuities resulting from modulation scheme changes are reduced to a large extent. This may be done before/after the pulse shapers (11, 21). The compensators (13, 22-26) comprise multipliers for multiplying pulse shaped modulated signals with complex valued waveforms (E), or for multiplying modulated signals with waveforms (S, T), or for multiplying complex valued signals (B, C, D) with complex valued phase offsets (X, Y, Z), which complex valued signals (B, C, D) are to be multiplied with mapped input signals.

Abstract: A device and a method are presented for generating an intermitted oscillating signal comprising a plurality of oscillating portions separated from each other in time. The device and method are suited for communication systems, in particular for Ultra-Wide Bandwidth (UWB) applications. The device comprises a variable oscillator for generating the oscillating portions; switching circuitry for switching on/switching off the variable oscillator at the beginning/end of each oscillating portion; and circuitry for setting initial conditions in the variable oscillator to impose a predefined transient and a characterizing frequency upon each start-up.

Abstract: Quadrature modulation systems, circuits and methods are provided to support various modulation modes including ASK (amplitude shift key), FSK (frequency shift key) and PSK (phase shift key) modulation at high data rates (e.g., gigabit data rates). For example, a modulation circuit includes a mixer circuit including an integrated sign modulation control circuit and a plurality of mixer ports. The mixer ports include a first input port, a second input port, an output port and a sign modulation control port. The modulation circuit generates a modulated signal by operation of the mixer circuit multiplying a modulating signal applied to the first input port with a carrier signal applied to the second input port to generate a mixed signal output from the output port, and by operation of the integrated sign modulation control circuit controlling polarity switching of a signal at one of the mixer ports in response to a sign modulation control signal input to the sign modulation control port.

Abstract: An offset errors of a quadrature modulator is corrected. A device including a first correction signal output unit (50) for outputting a first correction signal based upon a local signal (phase: 0°) from a 180°-phase amplifier (27) or a phase shift local signal (phase: 180°) from a 180°-phase amplifier (23), a second correction signal output unit (60) for outputting a second correction signal based upon an orthogonal local signal (phase: 90°) from a 180°-phase amplifier (37) or an orthogonal phase shift local signal (phase: 270°) from a 180°-phase amplifier (33), and a correction signal output unit (70) for outputting a correction signal based upon the first and second correction signals, wherein a correction signal is further added to outputs from an I signal mixer (42) and a Q signal mixer (44) by an adder (46) resulting in correcting offset errors of the quadrature modulation.

Abstract: A circuit 30 for upsampling and upconverting a high rate signal that is divided into M in-phase (I) symbols and M quadrature (Q) symbols. A Nyquist filter 32 upsamples by a factor of k each of the 2M symbols in parallel during one system clock period (CP). The filter 32 has a plurality of 2kM filter components 40, 42, that each provides a continuous output. A plurality of multipliers 50, 52 each upconverts a filter component output with a carrier wave signal 46, 48 that is output from a numerically controlled oscillator 44. A plurality of adders 54 each adds the output of two multipliers 50 to recombine corresponding I and Q samples to output kM samples during a CP. For continuous phase modulation, N parallel bits are input into the filter 32, upsampled in one CP, and accumulated and modulated 82 in parallel in one CP. For analog processing, M (I) and M (Q) symbols are input into an FIR filter 77a, 77b for upsampling, and decimated at a MUX/DAC block 78 for subsequent analog upconversion.

Abstract: A plurality of RF signals are generated with the RF signals synchronized with each other with high accuracy. Transmission data of the multiple channels are modulated, the modulated data of the channels are added to produce composite data and the composite data is stored in a data storage device. In the modulation process, the carrier frequencies are different from each other. The composite data comprises the data of the channels modulated in the frequency division multiplexing manner. The composite data is converted into an analog composite signal by a D/A converter and this analog signal is upconverted to an RF frequency by a frequency conversion circuit. A signal separation circuit produces two channel signals from the RF frequency signal. A signal output circuit generates the output signals having desired frequencies and signal levels.

Abstract: A transmitter providing a wide output control variable width with high efficiency is provided. Saturation mode operation is performed in the vicinity of the maximum transmission power and the input level of a large power amplifier is enlarged and fixed. When the large power amplifier is operated in a saturation state, the amplitude component of a modulation signal is input to an R input terminal in the range responsive to an output power control level and power supply voltage of a power supply terminal is amplitude-modulated, whereby highly efficient polar coordinate modulation is performed. In smaller transmission power, linear mode operation is performed, the input level of the large power amplifier is lessened for operating the large power amplifier in the linear mode, and the power supply voltage of the power supply terminal is made variable in response to the output power control level, whereby transmission power control is performed.

Abstract: A method and system generates a higher order modulation, in which a complex sequence of binary digits corresponding to symbols of a higher order modulation is received. The symbols correspond to constellation points of the higher order modulation. First mapping means map the symbols of the higher order modulation to first constellation points of a first QPSK modulation and output an output signal of the first QPSK modulation corresponding to the first constellation points. Similarly, second mapping means map the symbols of the higher order modulation to second constellation points of a second QPSK modulation and output an output signal of the second QPSK modulation corresponding to the second constellation points. Adding means add the output signals of the first and second QPSK modulations, thereby generating the constellation points of the higher order modulation.

Abstract: The present invention relates to an apparatus and a method for compensating carrier feedthrough in a quadrature modulation system. In order to suppress the carrier feedthrough, and minimize and compensate the carrier feedthrough, differences of baseband differential input DC voltages in an in-phase as well as a quadrature-phase are simultaneously adjusted to 0 or a certain slight voltage difference by a simple analog circuit. Therefore, it is possible to suppress carrier feedthrough using a simple analog type apparatus for compensating carrier feedthrough, and simply achieve an apparatus for carrier feedthrough using a variety of quadrature modulators.

Abstract: A quadrature modulator divides a first signal input as a local signal into an I channel signal and a Q channel signal orthogonal to each other and outputs a second signal having a desired phase delay corresponding to direct current voltages as for the first signal by giving the direct current voltages Vi and Vq to the I channel signal and the Q channel signal, respectively. A phase comparison unit detects a phase difference ? between the first signal and the second signal. A setting unit sets the desired phase delay. A controller section controls the direct current voltages supplied to the I channel signal and the Q channel signal respectively in the quadrature modulator so that an output value corresponding to the phase difference ? detected by the phase comparison unit is equal to a value corresponding to the desired phase delay set by the setting unit, and controls the direct current voltages to be the direct current voltages Vi and Vq satisfying the relation of Vi=cos ? and Vq=sin ?.

Abstract: In a radio communication system, transmitter and receiver stations share information on a maximum number of bits communicated per symbol. The transmitter station encodes a signal with sufficient error correcting capabilities to create a codeword. The transmitter station allocates the bits from the codeword to each symbol, modulates the symbols using a modulation type which processes symbols each having a number of bits equal to or smaller than the maximum number of bits per symbol, and transmits the modulated symbols. The receiver station demodulates the symbols using a modulation type which processes a larger number of bits per symbol as the transmission path quality is higher from among modulation types which process symbols having a number of bits equal to or smaller than the maximum number of bits per symbol.

Abstract: A method and apparatus for modulating an input signal comprised of an ordered series of samples separated by a substantially constant period T comprising the steps of providing a carrier signal, the carrier signal comprised of a series of samples separated by a substantially constant period T, wherein one of the carrier samples corresponds to each of the input signal samples, selecting a plurality of N successive samples from the series of input signal samples, the series of samples having an input order, for each of the N selected samples in parallel, multiplying the selected sample by the corresponding carrier sample and recombining the N multiplied samples while maintaining the input order.

Abstract: The invention relates to a method and a system for calibrating an analogue I/Q-modulator (2) of a transmitter (3), wherein a calibration signal (s(tk)) is transmitted and an in-phase signal (sI(tk)) and a quadrature-phase signal (sQ(tk)) of the calibration signal (s(tk)) are adjusted by at least one predetermined compensation coefficient (C, D, E) in two calibration steps in at least one compensation measurement set (un, vn, wn), whereby: in a first calibration step, the calibration signal (s(tk)) is adjusted by a first complex compensation value (Cn,1, Dn,1, En,1) and an output signal of the detector circuit (20) is correlated with a harmonic (H1, H2) of said calibration signal (s(tk)) to yield a first complex compensation measurement result (un,1, vn,1, wn,1), in a second calibration step, the calibration signal (s(tk)) is adjusted by a second complex compensation value (Cn,2, Dn,2, En,2) and the output signal of the detector circuit (20) is correlated with said harmonic (H1, H2) of said calibration sign

Abstract: Provided is a digital modulator, including a carrier wave output section that outputs a carrier wave, a variable delay section that delays the carrier wave, and a delay amount setting section that sets a delay amount by which the variable delay section delays the carrier wave based on transmission data being transmitted by the carrier wave. The variable delay section may include a multi-stage delay buffer circuit in which delay buffers that delay an input signal by a unit shift amount are connected in a cascade connection, the multi-stage delay buffer circuit may receive the carrier wave at a first-stage delay buffer as input, and the delay amount setting section may include a multiplexer that selects either an output from the carrier wave output section or an output from each stage of the multi-stage delay buffer circuit.

Abstract: The invention is directed at a hybrid modulation apparatus which combines a polar modulation circuit and a linear modulation circuit. The hybrid apparatus allows a communications device to function as a polar or a linear modulation circuit with less components as the output of the linear modulation circuit is an input of the polar modulation circuit.

Abstract: There is provided a multi sub-carrier communication system for providing improved performance of a frequency equalizer and a method thereof. The multi sub-carrier communication system includes a frequency equalization coefficient (vector) calculation unit that receives an equalized signal outputted from a frequency equalizer and periodically calculates a new frequency equalizer coefficient (vector) which is used to update the frequency equalizer coefficient (vector) used by the frequency equalizer. The multi sub-carrier communication system periodically updates the frequency equalization coefficient (vector) (after an initialization interval for initially estimating a channel characteristic) by periodically calculating the frequency equalization coefficient (vector) during a data receiving interval and thus, it is possible to dynamically adapt to changes of the channel characteristic over the passage of time, thereby improving performance of the frequency equalizer.

Abstract: A polar modulator for generating a polar-modulated signal based on amplitude information and phase information includes a phase-locked loop which is implemented to enable a setting of a frequency depending on a control value to obtain a phase-locked loop output signal. The polar modulator further includes a modulation means which is implemented to combine an amplitude modulation signal derived from the amplitude information with the phase-locked loop output signal to generate the polar-modulated signal. The polar modulator further includes a control value generator which is implemented to high-pass filter an amplitude signal derived from the amplitude information, to obtain a high-pass filtered amplitude signal, wherein the control value generator is implemented to combine the high-pass filtered amplitude signal with a phase signal based on the phase information to generate the control value signal representing the control value.

Abstract: A modulator includes a micro-electromechanical resonator device configured to receive an input signal and generate two output signals in response thereto, wherein the two signals having a predetermined phase relationship therebetween. The modulator further includes a switching system configured to selectively pass one of the two signals to an output of the modulator in an alternating fashion in response to phase modulation data.

Abstract: A quadrature modulator and a method of calibrating same by applying a first test tone signal to an in-phase modulation branch input of the modulator and a ninety degree phase-shifted version of the first test tone signal to a quadrature modulation branch input of the modulator. The carrier leakage level in an output signal of the modulator is measured and in response base band dc offset voltages are adjusted to minimize the carrier leakage. A second test tone signal is applied to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input. The level of an undesired upper sideband frequency component in the output signal is measured and in response base band gains the in-phase and quadrature modulation branches and a local oscillator phase error are adjusted to minimize the undesired side band.

Abstract: A DC offset cancellation circuit used for compensating a carrier leak at an output signal of a modulator has a sign extraction unit for extracting sign of an information signal which is applied to the modulator, an envelope detecting unit for performing envelope detection on the output signal of the modulator to output the resulting envelope, a slope detecting unit for performing polarity detection on the slope of the envelope; and a signal processing unit for generating a DC offset cancellation signal for compensating the carrier leak based on the result of the sign extraction and the result of the polarity detection. The signal processing unit preferably calculates the DC offset cancellation signal by multiplying the sign of the information signal by the polarity of the slope of the envelope and accumulating the result of multiplication.

Abstract: A digital up-sampling converter (DUSC) employs a signal input provided by a digital signal process (DSP) at a first rate feeding a Square Root Raised Cosine (SRRC) filter which provides for table look up of filter coefficients for a multiple symbol span and provides a sampling output at a second rate which is a multiple M of the first rate. A digital to analog converter (DAC) receives the sampling output at the second rate for conversion to an analog signal and a low pass analog filter processes the analog signal for delivery to an RF transmitter.

Abstract: A modulation apparatus 24 comprises a monitoring section 207 operable to monitor information about a control voltage applied to a VCO 201 as control voltage information, during any period, when a low-frequency signal having a frequency within a loop band of a PLL circuit is input at least before an LPF 209, a correction table storing section 206 operable to associate the control voltage information monitored by the monitoring section 207 as information about a control voltage after correction with information about a control voltage before correction, and store the associated information as a correction table, and a correction section 204 operable to correct a control voltage applied to the VCO 201 based on the correction table stored in the correction table storing section.

Abstract: The present invention discloses a method of transmitting a first signal and a second signal in a wideband code-division multiple access network, wherein a probability of the appearance of signal bit “1” or “0” in each signal of the first signal and the second signal is remarkably higher than a probability of the appearance of “0” or “1”, the method including: a step of determining constellation points, for determining combinations of different states of the first signal and the second signal and for determining each combination as a constellation point; a step of determining locations of constellation points, for determining a location of each constellation point on I-Q plane based on a priori knowledge of said combination; and a step of transmission, for, after modulating said different combinations in different ways according to the location of each constellation point, transporting them to a user equipment via a physical channel.

Abstract: A modulation system includes a modulator configured to employ a modulation mechanism on data. The mechanism includes a signal constellation configured to map sub-carriers which include a signal to be modulated. The signal constellation has a plurality of points asymmetrically disposed on a circle about an origin and a point at the origin wherein a number of sub-carriers becomes variable over different symbol intervals. Corresponding demodulators and corresponding methods are also disclosed.

Abstract: The present invention relates to a polar signal generator and method of deriving phase and amplitude components from in-phase (I) and quadrature-phase (Q) components of an input signal, wherein the I and Q components are generated at a first sampling frequency based on the input signal, and are then up-sampled in accordance with a predetermined first interpolation factor (N), to generate up-sampled I and Q components at a second sampling frequency higher than the first sampling frequency. The up-sampled I and Q components are converted into the phase and amplitude components, wherein the converting step is operated at the second sampling frequency. Moreover, the phase and amplitude components can be further up-sampled, optionally by different sampling frequencies, to a third and a fourth sampling frequency. Thereby, I-Q generation and cartesian-to-polar transformation can be performed at lower frequencies, which reduces power consumption.

Abstract: A GMSK modulator includes a dual-port memory, an address generator and a signal provider, where the dual-port memory respectively outputs in-phase and quadrature phase waveform data to first and second ports in response to in-phase and quadrature phase waveform address signals, the address generator generates the in-phase and quadrature phase waveform address signals based on a differential encoded bit stream, the signal provider selects one of the in-phase and the quadrature phase waveform data in response to the differential encoded bit stream, and outputs continuous GMSK in-phase and quadrature phase channel signals, and the redundancy of the memory that stores the GMSK in-phase and quadrature phase waveform data may be reduced using the dual-port memory so that the size of the memory may be reduced.

Abstract: Compensating for wideband quadrature imbalance error by introducing inverse complex inputs to phase quadrature estimator filters to generate estimated quadrature distortion; summing estimator quadrature distortion with a delayed version of the actual complex input to obtain estimated quadrature output; comparing the output with the true output to obtain residual quadrature imbalance error; applying a least mean square to the inverse input and imbalance residual error to obtain an updated estimate of filter coefficients; updating the filter coefficients of the phase quadrature estimator; and updating the filter coefficients of a phase quadrature compensator with the filter coefficients of the phase quadrature estimator to obtain a quadrature output pre-compensated for quadrature imbalance error.

Abstract: A quadrature transmitter and receiver have configurable I and Q channel paths that facilitate the application of selected test signals to determine gain and phase imbalances introduced by the transmitter and receiver. In a first ‘normal’ configuration, the I and Q channels are independently tested by applying an I-only test signal, followed by a Q-only test signal. In a second ‘switched transmitter’ configuration, the Q-only test signal is again applied. In a third ‘switched receiver’ configuration, the I-only test signal is again applied. By combining the results, gain and phase imbalances of the transmitter and the receiver can be determined. In a preferred embodiment, these configurations and test signals are applied within a single transceiver that has the output of its transmitter closed-loop coupled to the input of its receiver.

Abstract: A constrained-envelope digital-communications transmitter circuit (22) in which a binary data source (32) provides an input signal stream (34), a phase mapper (44) maps the input signal stream (34) into a quadrature phase-point signal stream (50) having a predetermined number of symbols per unit baud interval (64) and defining a phase point (54) in a phase-point constellation (46), a pulse-spreading filter (76) filters the phase-point signal stream (50) into a filtered signal stream (74), a constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the filtered signal stream (74), a delay element (138) delays the filtered signal stream (74) into a delayed signal stream (140) synchronized with the constrained-bandwidth error signal stream (108), a complex summing circuit (110) sums the delayed signal stream (140) and the constrained-bandwidth error signal stream (108) into a constrained-envelope signal stream (112), and a substantially linear amplifier (146) amplifies