Abstract: A calibration system may be provided for calibrating wireless communications circuitry in an electronic device during manufacturing. The calibration system may include data acquisition equipment for receiving an amplitude-modulated calibration signal from the electronic device. The calibration system may include calibration computing equipment for extracting pre-distortion coefficients from the amplitude-modulated calibration signal. The calibration computing equipment may be configured to detect a bulk phase drift in the amplitude-modulated calibration signal. The calibration computing equipment may be configured to remove the bulk phase drift from the amplitude-modulated calibration signal. The wireless communications circuitry may include a power amplifier that distorts a signal generated by the wireless communications circuitry. The wireless communications circuitry may include a pre-distortion compensator for countering the distortion.

Abstract: A modulation apparatus comprising a first modulating section that outputs a first modulated signal having a fixed amplitude and a set phase; a second modulating section that outputs a second modulated signal having the fixed amplitude and a set phase; an adding section that outputs the output signal as the sum of the first and second modulated signals; a calculating section that calculates two phases to be set respectively in the first and second modulating sections, based on designated amplitude and phase; an allocating section that allocates, for the first and second modulated signals, the two phases calculated by the calculating section such that the first and second modulated signals are each connected more smoothly; and a setting section that sets the phase allocated for the first modulated signal in the first modulating section and sets the phase allocated for the second modulated signal in the second modulating section.

Abstract: Aspects of a method and system for direct and polar modulation using a two input PLL are presented. Aspects of the system may include generating digital signals Wn and Vn from an input data signal Un and a feedback signal Yn. The generated digital signals Wn and Vn combined may carry the information content of Un while they compensate the non-idealities of the two-input analog phase locked loop (PLL). The digital signal Wn, which may be scaled appropriately in frequency, and the digital signal Vn may be provided as inputs to the PLL. The feedback signal Yn may be a digital signal that may correspond to the analog feedback signal Pt that may be generated by the PLL. Accordingly, the PLL may be adaptively controlled via the digital signals Wn and Vn for properly transmitting the input data signal Un.

Abstract: A method and device for reducing error components of a multi-channel modulator. The method comprises the steps of inverting substantially half of the channels of a modulator, and reducing error components between said inverted channels and said non inverted channels by inductive and/or capacitive summing. The method is especially suitable for synchronized pulses and similar signals to be modulated.

Abstract: The operating method is based on the simultaneous application of FM and AM. In this process, the fundamental frequency of the AM is derived from at least one, preferably the second, longitudinal mode. In continuous operation of the lamp, the color temperature is set for a prescribed power by setting the AM degree controllably.

Abstract: An integrated data jitter generator for the testing of high speed serial interfaces is provided. A transmit timing generator for use in a transmit data path includes a high frequency clock generator such as a phase-locked loop or a delay-locked loop having an input for receiving an oscillator or reference clock input. A clock modulator receives both an existing low frequency modulation signal and a high frequency modulation signal. A high-speed modulated clock signal is generated to enable jitter testing by a downstream-coupled receiver. Fixed frequencies such as 3, 6, 125, 150, 250, 300, 750, or 1500 MHz are used for the high-speed modulation signal, but any high-speed modulation frequency can be used to generate the desired amount of jitter. Likewise, the amplitude of the high frequency modulation signal can also be varied as desired.

Abstract: Apparatus for phase/frequency digital modulation includes a digital circuit receiving and processing a digital modulation input signal to generate a digital modulation control signal, a digital-to-analog converter coupled to the digital circuit converts the digital modulation control signal into an analog modulation control signal, and an RF/analog circuit is coupled to the digital-to-analog converter. The RF/analog circuit includes a voltage controlled oscillator to generate a modulated output signal in response to the analog modulation control signal, and a quadrature tuner coupled to the voltage controlled oscillator generates an in-phase tuner output and a quadrature tuner output in response to the modulated output signal. An analog-to-digital converter is coupled to the quadrature tuner and converts the in-phase tuner output and the quadrature tuner output to digital in-phase and quadrature tuner outputs.

Abstract: An ASK modulator including a switching diode connected in series to a carrier signal transmitting path, a first resistor connected between one end of the switching diode and a digital signal input end and a second resistor connected between one end of the switching diode and the reference voltage point. The digital signal to be applied to the digital signal input end is divided by the first and second resistors and the switching diode is turned ON and OFF to generate the ASK modulated signal with the logical level of the divided digital signal. In this case, the switching level of the switching diode rises substantially to prevent that the switching diode turns ON by the ringing phenomenon.

Abstract: A quadrature modulator with set-and-forget carrier leakage compensation. The quadrature modulator comprises an in-phase and a quadrature branch. In the in-phase and quadrature branches, real-time digital signals are converted to analog signals, the analog signals are filtered, and the filtered analog signals are modulated with a carrier signal and a ninety degrees phase shifted version of the carrier, respectively. The modulated in-phase and quadrature signals are added so as to form a quadrature amplitude modulated signal. Preferably upon powering up of the quadrature modulator, in the in-phase and quadrature branches, carrier leakage is measured. The measured carrier leakage is supplied to comparators, which toggle, when carrier leakage is minimal in the respective in-phase and quadrature branches.

Abstract: A circuit for reducing phase noise in a transmitted radio signal includes a first phase-locked loop circuit including a first controlled oscillator generating a first output signal at a first desired frequency, and a first phase comparator developing a first phase error signal to control the first controlled oscillator, the first error signal representative of phase differences between the first output signal and the first desired frequency. A second phase-locked loop circuit includes a second controlled oscillator generating a second output signal at a desired frequency of transmission related to the first desired frequency, and a second phase comparator developing a second phase error signal representative of phase differences between the first output signal and the desired frequency of transmission.

Abstract: A digital transmission system for a selective call message communication network such as a paging network utilizes a quadrature amplitude modulation (QAM) transmitter (40) and receiver (42). The QAM transmitter (40) receives as a modulating input thereto, a message data encoded signal with a pilot carrier in a notch of the power spectrum of the signal. In order to generate the signal, the system generates a Hilbert transform of a wave-form representing message data to be transmitted. The Hilbert transform and message data waveform are combined to provide a positive frequency component and a negative frequency component. These frequency components are shifted apart and combined to provide a notch in which a DC component can be added to form a pilot carrier. A receiver of the system removes the pilot carrier from a received signal and shifts the positive and negative frequency components together to recover the message data.

Abstract: A quadrature modulator multiplies two carriers which are 90.degree. out of phase with each other by a sine component and a cosine component of a baseband signal, respectively, adds the product signals to each other, and amplifies the sum signal to produce a quadrature-modulated output signal. The quadrature modulator includes a phase comparator for detecting a phase distortion suffered when the sum signal is amplified, a first phase controller for correcting the phase of a single carrier generated by a carrier oscillator based on a compared phase output signal from the phase comparator, a phase difference detector for detecting the difference between 90.degree.

Abstract: An RF amplitude modulated amplifier system is presented incorporating a plurality of RF amplifiers which are compensated for unwanted phase modulation. The system includes a common RF driver for supplying a common RF driver signal. A plurality of actuatable RF amplifiers are provided with each having an input circuit for receiving the common RF drive signal. Each amplifier has a fully on condition for amplifying the common drive signal to provide an amplified RF signal, and a fully off condition. Each of these RF amplifiers exhibits a characteristic in that its input circuit has an input impedance which is greater when fully on than that when fully off, thereby tending to present unwanted phase modulation of the plurality of RF amplifiers. One or more of the RF amplifiers are selectively turned fully on in dependence upon the magnitude of an input signal.

Abstract: In a modulation circuit, a variable frequency carrier is modulated by a binary PSK (phase shift keying) modulator with the digital signal of a selected data channel. A plurality of error correction values are stored in storage locations of a memory corresponding to the channels, each of the error correction values being representative of a deviation of the inherent operating characteristic of the modulator when operating at a particular frequency of the carrier from a predetermined operating characteristic. The carrier is generated by a channel synthesizer and its frequency is varied corresponding to the selected channel. The memory is addressed to read an error correction value from one of the storage locations corresponding to the selected channel. An error correction circuit is provided to correct the deviation in response to the error correction value read out of the memory.