Abstract: A variable delay line includes a housing package (20, 21); an input terminal (27) extending outwardly from a first side of the housing package; an output terminal (28) extending outwardly from a second side of the housing package which is opposite to the first side; a circuit board (23) provided within the housing package; an input terminal connection land (31) provided on the circuit board and connected to an end of the input terminal; an output terminal connection land (32) provided on the circuit board and connected to an end of the output terminal; a plurality of delay elements (36); a plurality of pairs of delay element connection fixed pads (33), each pair thereof connected to each of the delay elements; and a plurality of series connection fixed contact pads (34, 35) each corresponding to each pair of the delay element connection fixed pads and connectable in series across the input and output terminal connection lands.

Abstract: A broadband phase shifter and vector modulator includes two artificial transmission lines interconnected by FETs to selectively produce and sum incremental phase shifts of an input signal. A number of low pass filter sections are connected in series to form the first of the two artificial transmission lines and a number of high pass filter sections are connected in series to form the second artificial transmission line. Use of low pass and high pass filters equalizes transit times of each phasor through the phase shifter so as to maintain the proper phase relationship between the phasors over a broad bandwidth. Each of the two artificial transmission lines are coupled to a transistor circuit connecting corresponding low and high pass filter sections. The phase shifter operates by selectively summing the output variable-amplitude phase-shifted signals generated within the transmission lines to produce an output signal having a phase shift between 0.degree. and 360.degree..

Abstract: A digital phase shift apparatus having a pair of single gate FETs which are connected in a common source configuration. Transmission line segments which respectively connect the sources and drains of the FET pair, provides a phase shift to an applied RF signal. The operating FET provides signal gain as well as switch the signal path length.

Abstract: A phase shifter network which alternates between structurally dual networks is provided. In particular, the phase shifter has a topography which permits the network to be configured as alternatively T or .pi. networks of low pass and high pass delay circuits in accordance with states of a single control signal fed to the phase shifter.

Abstract: A parallel branched N-state design method is used for discrete increment signal processing systems, such as incremental phase shifters and attenuators. These systems are implemented using parallel branched signal processing networks, each with N parallel discrete increment branch circuits (i.e., without being restricted to binary-state networks). In comparison with conventional cascaded binary-state networks, the parallel branched N-state design achieves reduced complexity and insertion loss. An exemplary embodiment of a phase shift system providing 32 phase increments (or states) uses three cascaded phase shift networks--two quaternary-state networks (Quits 10, 20) and a single binary-state network (Bit 30). The most significant Quit (10) illustrates the N-state design, providing the four most significant phase states (reference, +90.degree., -180.degree., -90.degree.

Abstract: An electronically variable delay line having adjustable delay and bandwidth characteristics is provided. A varactor diode functioning as a variable controlled capacitance is coupled between a signal conductor and a ground reference conductor, thereby segmenting the signal conductor into two, individual smaller segments of conductor which function as fixed inductances. The delay characteristic of the line is adjusted by varying the varactor's biasing voltage which, in turn, varies the varactor's capacitance. A staggered termination technique is implemented to stabilize the insertion loss characteristics of the delay line.

Abstract: A variable phase shifter and amplitude weighting (VPSAW) device capable of selectively varying the phase and amplitude of an incoming RF signal (RF.sub.IN) in such a manner as to produce an output RF signal (RF.sub.OUT) having a selected phase and amplitude, by means of splitting the RF.sub.IN signal into first and second signal components, selectively shifting the phase of each of these two components, and then combining the thusly selectively phase-shifted first and second signal components. In the presently contemplated best mode of the present invention, the VPSAW device includes digitally-implemented componentry, e.g., microprocessor-controlled direct, digital synthesizers, for generating first and second control signals, e.g., selectively phase-shifted sinusoidal signals, indicative of first and second phase shift increments, .phi..sub.a and .phi..sub.b, respectively, to be imparted to the first and second signal components, respectively.

Abstract: A microwave frequency group delay corrector operates by reflecting the microwave on a correcting complex impedance (jx). It makes use of a power divider (13), of the Wilkinson type. The complex impedance (20) is connected to the port (14) which is normally the inlet port to the power divider (13). The microwave (E) is applied to one of the other two ports (15), and the remaining other port (16) is used as the port from which the phase corrected outlet microwave (S) is taken.

Abstract: A phase shifter providing constant group delay and a wide instantaneous bandwidth is taught. In one embodiment, an input port is connected to an output port with a power splitter formed of a transformer connected between the input port and the output port, and having a center tap serving as a sum port. An impedance, such as a resistor, is connected in parallel with the transformer between the input port and the output port. A reactive network is connected between the sum port and ground, including one or more variable reactance device, such as a varactor, which alter the reactance of the reactive network in response to a control signal. Additional reactive elements are included in the reactive network to provide additional poles and zeros which change frequency in response to the variable reactance elements, in order to provide a group delay which is constant for various reactance values provided by the reactive network between the lowest frequency of interest and a higher frequency of interest.

Abstract: An analog phase shifter is provided by cascading T high pass filter and .pi. low pass filter sections. The low pass filter network is selected to have a cut-off frequency above the highest frequency in a predetermined frequency range of the phase shifter and includes a fixed inductor element as a series element of the network and a pair of variable capacitor elements disposed in shunt between said inductor element and ground. The high pass filter network has a cut-off frequency below the lowest frequency of the predetermined frequency band. The network includes a fixed inductor element disposed as a shunt element of said network and a pair of variable capacitor elements disposed in series. The inductor element is coupled between a common connection of said pair of variable capacitor elements and the reference potential. The .pi. network and the T network are cascaded connected between the pair of terminals of the network.

Abstract: A time delay shifter imparts a constant time delay to an electromagnetic signal, preferably a signal at a microwave frequency, over a band of frequencies. The phase shift imparted to the signal is a linear function of frequency. The shifter comprises a finite number of delay units (1) each having four single-pole single-throw switches (11-14). Closure of the first and third switches (11, 13) causes the signal to traverse a first path (2) containing a preselected length of transmission line that imparts a fixed time delay to the signal. Closure of the second and fourth switches (12,14) causes the signal to traverse a minimum-delay path (3) which is shorter than the delay path (2). The paths (2,3) are fabricated of coplanar waveguide. Each switch (11-14) is resonated by an inductor (21-24) for purposes of increasing isolation. An attenuator (70) is inserted in each minimum-delay path (3).

Abstract: A programmable computer shift register or other time delay means of variable length that provides time delays that are integral multiples of a predetermined time delay unit .DELTA.t, that uses relatively few switches, that controls time delays introduced by passage of signals through multiple-state switches that are in different states.

Abstract: According to the invention, the circuit comprises at least one two-port network of the "M-derived" section type and connected as an all-pass filter with a phase law which is a linear function of frequency. The two-port network is made in monolithic technology on gallium arsenide and the plane of its structure includes at least one elementary section, which, between an inlet and an outlet which are situated at a distance apart, is constituted by a spiral connected in parallel with a capacitor of metal-insulator-metal structure, with the mid point of the spiral being connected via another capacitor of metal-insulator metal structure to a ground plane. It is applicable to making transmission lines which are programamble in length.

Abstract: An electromagnetic variable delay line system in which the change in the output impedance of the delay line as its delay time is varied is compensated by an electronic device such as a field effect transistor which is connected across the output end of the variable delay line system. Therefore, generation of undesirable reflected waves can be prevented and high speed signals can be processed without distorting the signals.

Abstract: This electromagnetic variable delay line includes: a delay line, which includes an inductance device and at least one variable capacitance diode connected thereto, and possessing a non linear operational property; and a circuit device for supplying an output control signal to the variable capacitance diode in a manner which varies non linearly with an input control signal. The circuit means has a non linear property which is substantially complementary and opposite to the non linear delay property of the delay line. Optionally but desirably, the delay line may include: several delay line elments, connected in series, each of which includes an inductance device and a variable capacitance diode connected to the inductance device, the variable capacitance diodes being connected together; and buffer circuits connecting together each adjacent pair of these delay line elements.

Abstract: The present invention relates to a reflection diode phase shifter that achieves amplitude equality between phase shifts of incident energy. Amplitude equality is achieved by placing a resistor R to ground in parallel with the transmission lines connecting a four-port coupler to symmetric reflection terminators having an impedance that is varied by a diode. The resistor is placed at a point on the transmission line having the lowest voltage when the greatest power loss is realized by the phase shifter.

Abstract: A network is provided which is selectively configurable as a high pass and low pass filter. A pair of sets of field effect transistors FETS is provided, each set comprising three FETS connected in a T-configuration. A pair of the FETS in each set have a drain electrode of one FET coupled to the source electrode of the other FET to provide a series element of the T-configured set. The third FET has drain and source electrodes coupled between the common connection of the pair of FETS and ground to form a shunt element of the T-configured set. The gate electrodes of the series elements of a first one of the sets of FETS and the shunt element of the other set of the FETS are each fed a common control voltage signal. A first one of the sets of FETS is capacitively coupled between the input and output terminals of the network, and the second one of the set of FETS is inductively coupled between the input and output terminals of the network.

Abstract: This variable delay line system includes a variable delay line which has two output ends and a plurality of signal input points at its intermediate points, a means for selecting one of the input points of the variable delay line and for inputting a signal thereto, and a means for switching the signals from the output ends of the variable delay line and for outputting them. Optionally, a fixed delay line can further be included. Thereby, the varibale delay line system has a simple and compact structure and is effective.

Abstract: This distributed constant type delay line has an inductance element which has a plurality of main portions lying generally in parallel stacked planes. Each of the main portions has a conducting portion with a generally central line, the conducting portions being connected in series with one another with their the central lines lying generally parallel to one another and being alternately staggered to and fro in the direction generally perpendicular to them and generally parallel to the stacked planes. A ground electrode is interposed between the conducting portions of two neighboring ones of the main portions of the inductance element. And a dielectric layer is interposed between the ground electrode and a neighboring one of the main portions of the inductance element. Thereby, a very efficient and compact construction becomes available, which is suitable for being made as a chip. Optionally, capacitance compensating electrodes are defined as extending out from the main portions of the inductance element.

Abstract: This finely variable delay line includes a first variable delay line element the delay time provided by which can be relatively coarsely varied, and a second variable delay line element the delay time provided by which can be relatively finely varied, connected in series with the first variable delay line. A reflection circuit is constituted between an element included in the second variable delay line and another element of the construction, the reflection circuit reflecting back a signal towards the element of the second variable delay line. Although some slight mismatching is in fact present, such mismatching is quite negligible in practice, and this variable delay line can be very finely adjusted by steps of as little as 0.5% of its total range or less.

Abstract: A phase shifter with a phase shift primarily independent of frequency includes first and second quadrature hybrids, a delay and a ganged switch. A first path includes an input into the delay, the delay output being connected into the first quadrature hybrid. The corresponding isolated terminal of the first quadrature hybrid forms the output of the first path. A second path includes an input to the second hybrid quadrature with a terminal thereof as an output. Two remaining terminals of the second quadrature hybrid are taken to a common ground through two capacitors of preselected value. The ganged switch selectively engages a system input to either the inputs of the first path or the second path and simultaneously engages a system output to the outputs of the first path or the second path.

Abstract: This variable delay line makes use of a transmission line as a delay line element and is suitable for switching over the delay time of a high speed signal having for instance a rise time of one nanosecond or less. And this variable delay line includes a transmission line which includes an electroconductive path and a ground plate disposed opposingly with a dielectric body interposed therebetween, a fixed contact array consisting of fixed contacts provided at certain intervals along the electroconductive path, and a movable contact which may be slid along contacting the fixed contacts of the fixed contact array. Particularly, the movable contact contacts one of the fixed contacts in the fixed contact array in a first state and contacts two neighboring ones of the fixed contacts in the fixed contact array in a second state, and the movable contact may be slid over the fixed contact array by alternatingly repeating the first and the second states.

Abstract: A radar phase shifter is described, of the type which includes several phase shift devices whose phase shift angles can be added together, which produces a minimal VSWR and an accurately controllable total phase shift. A five bit phase shifter includes devices that phase shift by angles that are nominally 11.25.degree., 22.5.degree., 45.degree., 90.degree., and 180.degree.. The 45.degree. device is located between the 90.degree. and 180.degree. devices to minimize the VSWR. In addition to the preset phase shift devices, an analog phase shifter device is provided which compensates for the inaccuracy of the other devices.

Abstract: Steerable phased array antennas of the tapered type in which the antenna ment power is maximum at the center of the array and tapers off on either side thereof. The phase shifters of each antenna element are of the binary digital type with the number of stages and hence the phase accuracy being maximum for the high power center antenna elements and tapering off on either side thereof. Redundant stages for the binary phase shifters can be provided to increase reliability.

Abstract: This invention aims to provide a method of adjustment for a variable delay line which is provided with two delay line elements of dissimilar delay times and switch means capable of selectively switching from one to the other of the two delay line elements and adapted to enable the delay time to be digitally increased or decreased by the delay time difference produced by the selective switching between the delay time elements. This method allows the delay time to be finely adjusted with high accuracy of the order of 1 to some tens of ps by changing the delay time of either of the two delay line elements which has a smaller delay time than the other.

Abstract: A surface acoustic wave (SAW) device provides a phase shift and a first predetermined phase shift variation as a function of temperature. A passive network including a passive, reactive component is thermally and electrically coupled to the SAW device. An electrical characteristic of the component has a predetermined variation as a function of the temperature of the reactive component which provides the network with a second, predetermined phase variation as a function of temperature to compensate for the first predetermined phase variation as a function of temperature provided from the surface acoustic wave device. With this arrangement, the phase shift provided from the surface acoustic wave device is substantially invariant with temperature.

Abstract: A low pass T-section digital phase shifter apparatus having a pair of serially connected inductor-diode combinations connected in series which includes a parallel circuit connected between the common junction and ground. The parallel circuit has an inductor in parallel with a series capacitor and diode to provide a balanced insertion loss at each diode switching state. When the diodes are in the forward-biased state they act as closed short circuit switches. When the diodes are reversed-biased, the inductance in the series circuit resonates with the diode capacitance to provide a short path to the RF signal to pass the center frequency of the RF signal at the desired phase.

Abstract: A variable delay line using a lumped constant type electromagnetic delay line and enjoying a superhigh-speed rising characteristic is disclosed, which comprises an inductance element formed by winding a conductor and possessed of a plurality of taps, a plurality of capacitors having electrodes thereof on one side kept in common connection, a plurality of linking electrodes disposed along the inductance element and adapted to interconnect the taps of the inductance element and the electrodes of the capacitors on the other side, fixed contacts formed of limited surface regions of the linking electrodes, and movable contact means adapted to advance on the fixed contacts while keeping pressed contact with each fixed contact so as to permit selection of the taps of the inductance element.

Abstract: A low pass .pi. section digital phase shifter apparatus having an inductor and a diode connected in series between two identical parallel circuits. The parallel circuits connect to the series inductor/diode circuit at both the input and output and each circuit has inductor connected in parallel with a capacitor and a diode to provide balanced insertion loss at each diode switching state. When the diodes of the circuit are in the forward biased state they act as closed short circuit switches. When the diodes are reversed biased, the inductance in the series circuit resonates with the diode capacitance to provide a short circuit path to the RF signal to pass the center frequency of the RF signal at the desired phase.

Abstract: An extra high frequency .pi.-section digital phase shifter apparatus having a diode connected between two identical parallel shunt circuits. The parallel shunt circuits connect to the series inductor/diode circuit at both the input and output and each parallel shunt circuit has inductor connected in parallel with a capacitor and a diode to provide balanced insertion loss at each diode switching state. When the diodes of the circuit are in the forward-biased state they act as closed short circuit switches. When the diodes are reverse-biased, the inductance in the shunt circuit resonates with the diode capacitance to provide a short circuit path to the RF signal at the center frequency of the RF signal at the desired phase.

Abstract: A circuit for detecting a Frequency Modulated (FM) signal is provided. An amplitude limited FM signal is propated through a delay circuit comprising a plurality of cascaded saturating inverters. A Boolean logic "Exclusive Or" (XOR) operation is performed between the FM signal before entering the delay circuit and after exiting the delay circuit.

Abstract: An extra high frequency T-section digital phase shifter apparatus having a pair of back to back diodes connected between the input and output terminals with a parallel circuit connected between the common junction and ground. The shunt parallel circuit has an inductor in parallel with the series combination of a capacitor and a diode to provide a balanced insertion loss at each diode switching state. When the diodes are in the forward-biased state they act as closed short circuit switches and in the shunt circuit, the inductance resonates with the diode capacitance to provide a perfect transmission for the RF signal.

Abstract: A n-bit digitally controlled phase shifter for controlling the phase of an applied signal over the range of 0.degree. to 360.degree. includes n, cascade interconnected phase shifter stages. Each phase shifter stage is formed on a semi-insulating substrate having a pair of field effect transistors and a pair of transmission lines formed thereon. Each field effect transistor (FET), includes a pair of gate electrodes, a drain electrode, and a source electrode, connected in a common (grounded) source configuration. Each transmission line is coupled between a corresponding one of the drain electrodes and a common output port. The lengths of the transmission lines are selected to provide two paths having an electrical pathlength corresponding to a phase shift of .phi..sub.1 or a phase shift of .phi..sub.1 +.DELTA..phi..sub.1 where .DELTA..phi..sub.i is the phase shift increment of the i.sup.th stage. A first one of the gate electrodes of each field effect transistor is fed by the applied signal.

Abstract: An improved phase shift network is disclosed which is applicable to broadband systems, particularly in connection with feedforward power amplifier systems. The phase shift network includes a splitter for receiving an input signal and providing outputs which are coupled through all pass networks to produce signals differing in phase by a predetermined angle. The signals from the all pass networks are coupled through variable attenuators having their outputs recombined in a combiner to produce an output representing the input signal phase shifted by a predetermined angle. The phase shift may be adjusted by changing only one variable attenuator at a time to produce phase shifts of 90.degree. or greater.

Abstract: Microwave couplers such as power splitters and combiners for coupling a common terminal to two branch terminals are disclosed which are compact and provide gain. Each leg of the branching circuit comprises a dual gate FET device. The dual gate FET device has its first gate connected to receive an input signal, its second gate biased and terminated in accordance with the phase shift desired from that FET device and its drain coupled to provide an output signal. Where equal phases are desired from both legs, the second gates of all of the FET devices are capacitively terminated. Where a differential phase shift is desired over the two legs, the second gate of the FET device in one leg is capacitively terminated and the second gate of the FET device in the other leg is inductively terminated. The bias voltages on the second gates are preferably selected to produce the same gain for both.

Abstract: An ultra-high speed lumped constant delay line includes an inductance element formed by winding a conductor into a single layer solenoid shape of predescribed pitch P, and a plurality of capacitors connected between ground and the conductor at every turn of the inductance element. The pitch P and the winding diameter T in the direction of short diameter are set according to the relation 0.2<P/T<1.9.

Abstract: A circuit capable of vector magnitude control and phase reversal for a radio signal such as an intermediate frequency signal. The circuit includes an inverting signal path and a noninverting signal path and means for selecting between the two. Further, a variable attenuation controllable from a function control input establishes the magnitude of the output signal vector. There is also disclosed a phase shifter employing two such circuits. In the phase shifter, a radio signal vector to be shifted is applied to the inputs of the two circuits, with a 90.degree. shift between the two inputs. With proper vector magnitude and phase reversal control of the two circuits, there can be provided a preselected phase shift in any quadrant.

Abstract: A variable delay line is disclosed which comprises an electromagnetic delay line formed of an inductance element and capacitors, a conductive plate disposed along the electromagnetic delay line and opposed thereto, and a movable contact adapted to move along the delay line while remaining in continuous contact with the conductive plate and the inductance element. The variable delay line has its delay characteristics improved by bending the aforementioned conductive plate in such a manner that it is separated from the delay line along the contact parts exposed to contact with the movable contact and, as a result, the stray capacitance formed between the delay line and the conductive plate is kept down to a negligibly small level.

Abstract: A lumped constant type ultra-high speed variable delay line includes an inductance element consisting of a single layer solenoid formed by winding a conductor with a prescribed pitch, a capacitor connected between said conductor and ground at each turn, a fixed contact array consisting of fixed contacts respectively formed on said each conductor at each turn of said inductance element, and a movable contact element for sliding on said fixed contact array while alternately making single-contact with one of said fixed contacts and multi-contact with adjacent fixed contacts.

Abstract: A tuneable lumped LC electronic delay line for delaying RF signals in a bandwidth of at least 100 MHz by a substantially constant amount throughout the band, the delay line including a plurality of deformable air coil inductors that are inductively coupled to one another, a plurality of capacitors connected between each inductor pair and electrical ground, and a reactive element connected at one end of the series of inductors and reactively coupled to electrical ground.

Abstract: A high speed reflectance type phase shifter is described incorporating a wide bandwidth coupler having four ports, two of the ports having a high speed diode coupled thereacross a resistor coupled in shunt across each diode to provide power dissipation at times the diodes are non-conducting and a current driver to provide bias current to the diodes. The invention provides constant insertion loss through the phase shifter during the on state and off state of the diodes corresponding to the two phase conditions of the output signal without affecting bandwidth.

Abstract: The delay line has a number of sections in tandem. Each section comprises o line segments in parallel, one of which is relatively short and the other of a length to provide a given differential delay for the section. Each segment has a PIN diode at each end, poled in one direction for the short segment and in the other direction for the other. The bias arrangement for the PIN diodes includes four transistor switches in a bridge, with a selected pair in opposite legs turned on to cause a polarity which permits it to flow through only that segment in which the PIN diodes are forward biased. The given differential delay for the several sections has a binary relation.

Abstract: A serrodyne includes a phase shifting circuit adapted to receive a sawtooth modulating signal for providing frequency translation of a radio frequency signal which can be at any of a range of input frequencies. The serrodyne also includes a discriminator which produces in response to the input RF signal a voltage of amplitude proportional thereto. The serrodyne further includes a circuit producing a sawtooth voltage waveform of period 1.div.m, where m is the amount of frequency shift desired in the serrodyne. The sawtooth waveform is applied to the phase shifting circuit. The sawtooth waveform is amplified by an amplifier to which is applied the sawtooth voltage waveform and the signal from the frequency discriminator. The amplification is such that the peak-to-peak magnitude of the amplified waveform is dependent on the amplitude value of the voltage from the frequency discriminator and causes the serrodyne frequency to be shifted by 360.degree. at any of the range of input frequencies.

Abstract: Two adjustable level signal translating devices in separate signal paths are arranged to receive an input alternating frequency signal and to pass the signal at respective desired levels to a vector summing circuit. One of the signal paths undergoes an additional 90.degree. phase shift. The vector summing circuit produces an output signal shifted in phase by an amount between 0.degree. and 90.degree. relative to the input signal depending on the levels of signals from the two translating devices.

Abstract: A distortion-corrector which comprises a filter of the low-pass type, of the .pi. or T configuration, and two diodes, in parallel opposition, disposed between the input and output of the filter. This corrector compensates amplitude-and-phase- distortions of the tube associated with the corrector, over a given operational frequency-band of the tube which is below the cut-off frequency of the filter, by compressing weak signals, for which no diode conducts, with respect to strong signals, for which there is at least a start of conduction of one of the diodes and by producing a phase-lead which increases with the input power of the tube.

Abstract: An apparatus for measuring the amount of relative displacement of mutually facing electrodes in such a direction as to cause a change in the distance therebetween, comprises:a power source generating an AC signal of a determined frequency;a phase-shifting means comprising a resistor and the mutually facing electrodes, the phase-shifting means being adapted to apply the AC signal to the mutually facing electrodes through the resistor and to generate an output signal of which the phase is shifted in response to the amount of relative displacement of the mutually facing electrodes; anda phase difference measuring means for measuring phase difference between the output signal of the phase-shifting means and the AC signal and generating a signal corresponding to the amount of relative displacement of the mutually facing electrodes.

Abstract: A delay network, having a chain of all-pass sections, each comprising two separate branches, a resistive and a capacitive branch, which terminate in amplifiers with negligible signal consumption whose output signals are combined. This enables an analog delay network to be realized in integrated circuit technology.