Physical Structure Patents (Class 333/140)
  • Patent number: 10447226
    Abstract: Some aspects pertain to an apparatus that includes a plurality of stacked metal layers configured in a spiral shape. The plurality of stacked metal layers include a first metal layer including a first inductor, a second metal layer including a plurality of first pads and a plurality of second pads, a third metal layer including a plurality of third pads and a plurality of fourth pads, a fourth metal layer including a second inductor, a plurality of first vias configured to couple the first metal layer to the second metal layer, a plurality of second vias configured to couple the second metal layer to the third metal layer, a plurality of third vias configured to couple the third metal layer to the fourth metal layer; and a dielectric layer at least partially surrounding the apparatus.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 15, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Yu-Chun Liu, Arjun Ravindran
  • Patent number: 10419128
    Abstract: An integrated circuit that includes an optical receiver is described. This integrated circuit may include an optical receiver. The optical receiver may include a photodiode that receives an optical signal and that outputs a corresponding current. Moreover, the optical receiver may include an inductor that is electrically coupled to the photodiode. Furthermore, the optical receiver may include a resistive analog front-end stage that is electrically coupled to the inductor. Note that the inductor may have a resistance per unit length that is greater than a first threshold value (such as 40 m?/?m), and the inductor may be approximately dispersion-less. For example, a Q factor for inductive peaking associated with the inductor is less than a second threshold value (such as 5).
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: September 17, 2019
    Assignee: Axalume, Inc.
    Inventors: Saman Saeedi, Ashok V. Krishnamoorthy
  • Patent number: 10319511
    Abstract: A coil component includes a body; and a coil disposed within the body, wherein the coil includes: a first coil conductor including a first conductor pattern with a planar coil shape and a first lead terminal extended to at least one surface of the body; a second coil conductor including a second conductor pattern with a planar coil shape and a second lead terminal extended to at least one surface of the body; and a connection conductor connecting the first and second coil conductors to each other and including a third lead terminal extended to at least one surface of the body.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD
    Inventor: Jin Hwan Kim
  • Patent number: 10290416
    Abstract: Exemplary embodiments of the present disclosure are directed to resonant transformers (or reactors) and coil arrangements associated with resonant transformers. The coil arrangements can include a grounding coil configured to generate a net-zero induced voltage between a first end of the grounding coil and a second end of the grounding coil layer, and one or more step-up coil layers formed by one or more layers of pressure tape, insulating materials, and wire wrapped to form coils about a portions of a split magnetic core. The split magnetic core can include a first core segment and a second core segment, where one of the core segments is disposed within a main housing and one of the core segments is disposed external to the main housing. A gap between the first and second core segments can be manipulated to control an inductance of the resonant transformer.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: May 14, 2019
    Assignee: Instrument Manufacturing Company
    Inventors: Matthew S. Mashikian, Andrzej Pawel Szatkowski
  • Patent number: 10153558
    Abstract: A component including a substrate with dielectric coating on the substrate. The electrical reactance of the dielectric coating configured for the propagation of electromagnetic surface waves. The dielectric coating is arranged as a plurality of discrete pathways. Also a signal transmission system including a component, an electromagnetic surface wave transmitter coupled to the substrate, and an electromagnetic surface wave receiver also coupled to the substrate.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: December 11, 2018
    Assignee: ROLLS-ROYCE PLC
    Inventors: Daniel Clark, Werner P. Schiffers
  • Patent number: 10145873
    Abstract: A bobbin and coil architecture is provided for use in an inductive sensor. The architecture eliminates the need for coil shielding and reduces the sensor's sensitivity to temperature and proximate mounting hardware. In one or more embodiments, all or portions of separate coils are located in a common slot on the bobbin, rather than being segregated into separate slots. In an example configuration, two receiver coils may be located in respective two slots on the bobbin, and a transmitter coil may divided into two substantially equal subsets of windings, with each subset wound together with one of the receiver coils in a common slot. This yields a symmetrical and balanced winding architecture that requires fewer slots relative to designs that segregate all coils into separate slots.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: December 4, 2018
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Lin Wang, Frederic Boutaud
  • Patent number: 9397631
    Abstract: Disclosed herein is a filter chip element including a ferrite substrate, internal coil patterns formed on the ferrite substrate; and a ferrite composite layer filled between the internal coil patterns formed on the ferrite substrate, wherein the ferrite composite layer includes foaming resin, thereby increasing magnetic permeability and a Q value which are important characteristics of a filter chip element for noise prevention among electromagnetic shielding components.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: July 19, 2016
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Suk Kim, Sung Kwon Wi, Hyeog Soo Shin, Sang Moon Lee, Young Seuck Yoo, Sung Jin Park
  • Patent number: 8680946
    Abstract: A programmable transversal structure that may serve as a filter, or more generally, a transversal network. A pair of time delay elements are implemented using one or more grating control propagation path structures, multilayer waveguides with configurable gaps, or variable impedance meander lines. Electro active actuators responsive to bandwidth, center frequency, and stop band attenuation control inputs control the delay of such elements. Impedance elements are distributed between the time delay elements to provide the desired transversal response.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: March 25, 2014
    Assignee: AMI Research & Development, LLC
    Inventors: John T. Apostolos, Judy Feng, William Mouyos
  • Patent number: 8216701
    Abstract: A compositionally stratified multi-layer Ba1-xSrxTiO3 (BST) heterostructure material is described which includes a lower layer of crystallized Ba1-xSrxTiO3 perovskite oxide where x is in the range of 0.36-0.44, inclusive, deposited on a substrate; an intermediate layer of crystallized Ba1-xSrxTiO3 perovskite oxide where x is in the range of 0.23-0.27, inclusive, in contact with the lower layer; and an upper layer of crystallized Ba1-xSrxTiO3 perovskite oxide where x in the range of 0.08-0.13, inclusive, in contact with the intermediate layer. A phase shifter and/or preselector tunable device including a compositionally stratified multi-layer BST hererostructure material is described according to the present invention. Temperature sensitivity of an inventive phase shifter is reduced by at least 70% in the temperature interval of 20 to 90° C., inclusive, and by at least 14% in the temperature interval of ?10 to 20° C., inclusive, compared to a compositionally homogeneous 60/40 BST material.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: July 10, 2012
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Melanie Will Cole
  • Publication number: 20120075036
    Abstract: There is provided a common mode filter capable of allowing an ultrahigh speed differential signal to transmit and hardly allowing a common mode noise to transmit, comprising: a lumped-constant differential delay line DL formed by arranging inductors Lo, being passive series elements, and capacitors Co, being passive parallel elements, in a ladder-shaped differential four terminal network composed of the passive series elements and the passive parallel elements arranged in the differential lines 1, 3. In the lumped-constant differential delay line DL, the capacitors Co, being the parallel elements, are formed of two capacitors connected in series equivalent to each other and having same values with each other such as Co/2 and Co/2, or Co and Co.
    Type: Application
    Filed: October 13, 2010
    Publication date: March 29, 2012
    Applicant: MATSUE ELMEC CORPORATION
    Inventor: Masaaki Kameya
  • Patent number: 8031033
    Abstract: A printed solenoid inductor delay line system comprises discrete delay sections, where the inductor is implemented in the form of a printed, spiraling solenoid, with the solenoid axis in the plane of the multi-layer printed circuit board (PCB).
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: October 4, 2011
    Assignee: Avocent Corporation
    Inventors: Barry Mansell, Gail E. Mansell, legal representative
  • Publication number: 20110210806
    Abstract: A compositionally stratified multi-layer Ba1-xSrxTiO3 (BST) heterostructure material is described which includes a lower layer of crystallized Ba1-xSrxTiO3 perovskite oxide where x is in the range of 0.36-0.44, inclusive, deposited on a substrate; an intermediate layer of crystallized Ba1-xSrxTiO3 perovskite oxide where x is in the range of 0.23-0.27, inclusive, in contact with the lower layer; and an upper layer of crystallized Ba1-xSrxTiO3 perovskite oxide where x in the range of 0.08-0.13, inclusive, in contact with the intermediate layer. A phase shifter and/or preselector tunable device including a compositionally stratified multi-layer BST hererostructure material is described according to the present invention. Temperature sensitivity of an inventive phase shifter is reduced by at least 70% in the temperature interval of 20 to 90° C., inclusive, and by at least 14% in the temperature interval of ?10 to 20° C., inclusive, compared to a compositionally homogeneous 60/40 BST material.
    Type: Application
    Filed: April 13, 2011
    Publication date: September 1, 2011
    Applicant: US Government as Represented by the Secretary of the Army
    Inventor: MELANIE WILL COLE
  • Publication number: 20110074525
    Abstract: To pass an ultra high-speed differential signal and make it difficult to pass a common mode noise. Lamped-constant differential delay line DL is formed by arranging inductors Lo, being passive series elements, and capacitors Co, being passive parallel elements, in a differential four terminal network of a ladder shape composed of the passive series elements and the passive parallel elements arranged in differential lines 1 and 3. The lumped-constant differential delay line DL is composed of capacitors Co including two capacitors Co/2 and Co/2, or Co and Co equivalent to the aforementioned capacitors, having equal values, and connected in series. Inductors L1 to L4 for attenuating a common mode noise are connected between connection points of the capacitors Co/2 and Co/2 or Co and Co connected in series, and a ground potential, so that attenuation poles are formed for attenuating the common mode noise together with the capacitors Co/2 and Co.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 31, 2011
    Applicant: ELMEC CORPORATION
    Inventor: Masaaki Kameya
  • Publication number: 20100090741
    Abstract: A delay circuit with a delay time being more accurate and a circuit area being reduced is provided. The delay circuit includes a resistance element 3, a capacitor element 4 and a connection wiring 6. The connection wiring 6 includes a first polysilicon layer 13a above a substrate 10, and a first silicide layer 14a which connects the resistance element 3 and the capacitor element 4 and is on the first polysilicon layer 13a. The capacitor element 4 includes a diffusion layer 12b in the surface region of the semiconductor substrate 10, a gate insulating layer 15b on the diffusion layer 12b, a second polysilicon layer 13b on the gate insulating layer 15b, and a second silicide layer 14b on the second polysilicon layer 13b. The resistance element 3 includes a third polysilicon layer 13c above the semiconductor substrate 10. The first, second and third polysilicon layers 13a, 13b and 13c are integrally provided. The first and second silicide layers 14a and 14b are integrally provided.
    Type: Application
    Filed: October 1, 2009
    Publication date: April 15, 2010
    Inventor: Hiroyuki TAKAHASHI
  • Patent number: 7683738
    Abstract: A transmission line includes a signal conductor and at least one varactor diode capacitively coupled to the signal conductor. The transmission line's signal path delay is a function of its shunt capacitance, and the varactor's capacitance forms a part of the transmission line's shunt capacitance. The transmission line's signal path delay is adjusted by adjusting a control voltage across the varactor diode thereby to adjust the varactor diode's capacitance.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: March 23, 2010
    Assignee: FormFactor, Inc.
    Inventor: Charles A. Miller
  • Patent number: 7606338
    Abstract: An analog correlator for very high speed data communication, including a single transmission line receiving an input signal and used as a signal delay circuit, a plurality of analog multipliers connected in parallel with a predetermined gap from the transmission line, for receiving a predetermined size of voltages, respectively, and an adder for adding the signals from the plurality of analog multipliers and transmitting the resultant signal as an output signal. The analog correlator can perform very high speed data communication, and can be applied to a high precision position estimation system. Moreover, the time delay is controlled in each part of the transmission line by adjusting a size of a variable capacitor. As a result, the length of the transmission line can be adjusted. Furthermore, the correlator is adaptively used according to variations of the very high speed communication environment by adjusting voltages of application voltage devices.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: October 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-hwan Kim, Hak-sun Kim, Chang-seok Lee, Kwy-ro Lee, Seong-soo Lee
  • Publication number: 20090179320
    Abstract: The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package such as a quad flat pack, a ball grid array or hybrid style module. The present invention takes the normally undesirable wire bond inductance and uses it in an operational circuit where positive inductance is required. The circuit in which the wire bond inductance is used is located primarily in the integrated circuit die housed in the integrated circuit package, but may also include off-die components. In one example, a wire bond is used as the required series inductance in a discrete circuit impedance inverter which consists of two shunt-to-ground negative inductances and one series positive inductance. One of the negative inductances is located on-die, while the other is located off-die.
    Type: Application
    Filed: March 23, 2009
    Publication date: July 16, 2009
    Inventors: James Stuart Wight, Johan M. Grundlingh
  • Publication number: 20090051465
    Abstract: In a band-pass filter of a delay line, an input terminal and a first resonator adjacent to the input terminal are coupled through a capacitor. The first resonator and a second resonator adjacent to the first resonator are coupled through a capacitor. The second resonator and a third resonator adjacent to the second resonator are coupled through an inductance. The third resonator and a fourth resonator adjacent to the third resonator are coupled through a capacitor. The fourth resonator and an output terminal adjacent to the fourth resonator are coupled through a capacitor.
    Type: Application
    Filed: March 10, 2006
    Publication date: February 26, 2009
    Applicant: SOSHIN ELECTRIC CO., LTD.
    Inventors: Hiroyuki Morikaku, Itsuaki Katsumata
  • Patent number: 7456706
    Abstract: An apparatus and method for providing an electrically adjustable RF delay in which a splitter splits an input signal into two signal paths, one signal path providing a delay fixed at an integral number of wavelengths of a desired center frequency and both signal paths providing electrically adjustable attenuation. A combiner combines the signals passing through the signal paths, such that the sum of the electrically-adjustable attenuation provided by the signal paths adds to unity, whereby the input signal is delayed by an adjustable time depending upon the attenuations provided by the signal paths.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: November 25, 2008
    Assignee: SOMA Networks, Inc.
    Inventor: James R. Blodgett
  • Patent number: 7355492
    Abstract: The inventions presented herein provide a electronically controlled phase shifters that incorporate analog and digital phase shift architectures in a novel manner that realizes the best advantages of each architecture. This combination of complementary phase shift architectures provides the high-performance and low loss characteristics of switched digital phase shift architectures with the high resolution and precision of continuous analog phase shift architectures. The circuit embodiments are electronically controlled, which simplifies implementation of what is a complex circuit. The analog phase shift elements comprise electronically-tuned varactors, which provide fine resolution and enables the incorporation of active compensation for manufacturing variation before use or for environmental conditions during use.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: April 8, 2008
    Assignee: Xcom Wireless
    Inventors: Daniel J. Hyman, Roger T. Kuroda
  • Patent number: 7342534
    Abstract: A phased array radio frequency pulse generator includes a plurality of radio frequency pulse generator units (4, 4a, 4b, 4c) each having a non-linear dispersive electrical circuit (1) incorporating at least one non-linear element (5) including a material sensitive to low power signals (7) and a means (6) for producing a variable power control signal (7) and applying it to be at least one non-linear element (5) to modify the extent of the non-linearity of the element and thereby vary the timing of the radio frequency electrical output signal generated, and means (13) for adjusting the value of the control signals (7) provided in each unit (4, 4a, 4b, 4c), to vary the relative phases of the output signals from the units (4, 4a, 4b, 4c) in a phased array on a pulse to pulse basis.
    Type: Grant
    Filed: November 3, 1998
    Date of Patent: March 11, 2008
    Assignee: Bae Systems, plc
    Inventors: Nigel Seddon, Christopher R. Spikings
  • Patent number: 7292124
    Abstract: A variable resonator is provided which comprises signal conductor 13 formed on top side surface of dielectric substrate 12, ground conductor layer 11 formed on back side surface thereof and switches 14, wherein signal conductor comprises a plurality of first conductor lines 13-1 and second conductor line 13-2 connected with all of first conductor lines, each first conductor line has a width larger than that of second conductor line to thereby a signal path through which high-frequency electric signal passes and which is longer than length of second conductor line is provided, switches 14 are connected to the ends of first conductor lines, whereby selectively opening and closing switches will electrically disconnect and interconnect interspaces between ends of first conductor lines to thereby vary length of signal path and thus change resonance frequency.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: November 6, 2007
    Assignee: NTT DoCoMo, Inc.
    Inventors: Kunihiro Kawai, Daisuke Koizumi, Hiroshi Okazaki, Shoichi Narahashi, Yasushi Yamao
  • Patent number: 6828876
    Abstract: Thin film devices having conductors of non-uniform line width and line spacing between adjacent conductors at uncoupled regions of symmetrical conductive pathways. Several coil-shaped delay line circuits are disclosed wherein the innermost and outermost conductors exhibit different line width and spacing between adjoining conductors. The devices are constructed on rigid and flexible, folding substrates and necessary terminations are connected with solder filled vias and/or edge connections.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: December 7, 2004
    Assignee: Thin Film Technology Corp.
    Inventors: Mark Brooks, Hiroo Inoue
  • Patent number: 6816031
    Abstract: A transmission line includes a signal conductor and at least one varactor diode capacitively coupled to the signal conductor. The transmission line's signal path delay is a function of its shunt capacitance, and the varactor's capacitance forms a part of the transmission line's shunt capacitance. The transmission line's signal path delay is adjusted by adjusting a control voltage across the varactor diode thereby to adjust the varactor diode's capacitance.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: November 9, 2004
    Assignee: Formfactor, Inc.
    Inventor: Charles A. Miller
  • Patent number: 6788169
    Abstract: In a broadband communication system there are multi-stage power amplifier systems for amplifying the power of radio-frequency (RF) communication signals. Each stage of the amplifier system results in composite triple beat (CTB) distortion, and if the phase of the CTB distortions are approximately the same (i.e. are in-phase), then the amplitudes of the distortions are added (i.e. “20 dB” rule). The amplifier system of the invention includes one or more phase filters positioned in series between the power amplifier stages. The phase filters are adapted to shift the phase of the communication signals, so that the phase of CTB distortions, resulting from the amplification of the communication signals in the amplifier stages between the phase filters, are substantially different (i.e. are out-of-phase). Thus, only the power of the CTB distortions are added (i.e. “10 dB” rule).
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: September 7, 2004
    Assignee: Broadband Royalty Corporation
    Inventors: Marcel F. Schemmann, Zoran Maricevic
  • Patent number: 6762654
    Abstract: A compact, small-size delay line that has excellent flatness in group delay time characteristic and an excellent frequency characteristic, is constructed such that one coil is divided into four inductors, and four stages of LC-&pgr; type low pass filters including inductors and capacitors are contained within a laminated body. The inductors are defined by connecting together in series coil conductor patterns arranged in a matrix on insulating sheets provided in the laminated body. Mutually adjacent inductors are arranged so that their coiling directions are opposite to each other. The insulating sheets may be made of non-magnetic material having a dielectric constant of about 15 or lower.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: July 13, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hideaki Tanaka
  • Patent number: 6476685
    Abstract: A circuit and method for creating an all pass network for equalizing the group delay of a filter. The all pass filter provides an equalization network including a transformer having a primary and secondary winding magnetically coupled together. One end of each primary and secondary winding is connected together to form a connection, the remaining ends of the primary and secondary winding constitute input and output terminals to the equalization network. Control over the group delay response is effected by a bias conductor serially connected to the common ends of the primary and secondary winding and a capacitor connected to the common terminal. The bias conductor modifies the mutual inductance, therefore modifying the coupling factor for the transformer. By shifting control of the coupling to the bias conductor, group delay response may be controlled without further modifications of the transformer coupling.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: November 5, 2002
    Inventor: William S. H. Cheung
  • Patent number: 6335666
    Abstract: To make a variable phase shifter at low cost and that is easy to manufacture, two propagation paths for a high frequency signal are provided in parallel between the input and the output of the phase shifter. These two paths are of different lengths. An intermediate node on one of the paths is connected to an intermediate node on the other path by a PIN diode. The diode is connected to the paths by a segment of line further enhancing the length difference. By biasing the diode to a desired level, it is caused to present a particular impedance to propagation. It is shown that by acting in this way the diode can vary the phase shift between the input and the output without needing to use harmful reactive components.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: January 1, 2002
    Assignee: Alcatel
    Inventors: Jean-Pierre Lemonnier, Maurice Bernaud
  • Patent number: 6317013
    Abstract: A filter, for use with a delay compensating circuit in a delay line filter, formed from co-located capacitors. The capacitors may be formed as traces disposed on a circuit card and co-located to provide capacitive coupling to each other and ground. Proximity coupling wires are connected at one end to capacitive traces, and at the other end hang in mid-air above the next adjacent capacitive trace. The distance between each proximity coupling wire and the neighboring capacitive trace can be varied to control the capacitance coupling between neighboring capacitive traces. The filter is thus tuned by controlling the distances between the proximity coupling wires, and by squeezing or stretching the inductors. The shunt coils control the frequency of the filter, while the series of capacitive traces control the bandwidth.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: November 13, 2001
    Assignee: K & L Microwave Incorporated
    Inventor: Rafi Hershtig
  • Patent number: 6281765
    Abstract: A non-mechanical electrically adjustable delay device which does not suffer from interruptions in impedance inherent in multiple-tap delay lines. The wide band electrical delay line is capable of delaying a wide band of signals without significant distortion, e.g., up into the microwave range, and allows continuous transmission of a signal between the input port and the output port. The exemplary wide band electrical delay line comprises two transmission lines, preferably parallel to one another, and having different propagation velocities. A plurality of electrical cross connect circuits are connected between the two transmission lines. The electrical cross connect circuits are spaced along the lengths of the two transmission lines, e.g., preferably to form evenly spaced distances therebetween. The total delay through the wide band electrical delay line is adjusted by selectively activating an appropriate one of the plurality of cross connect circuits between the two transmission lines.
    Type: Grant
    Filed: March 9, 1999
    Date of Patent: August 28, 2001
    Assignee: Agere Systems Optoelectronics Guardian Corp.
    Inventors: Basil Wahid Hakki, Ton Van Nguyen
  • Patent number: 6078228
    Abstract: A phase shifting electric circuit (1) comprises units for conveying an input signal (V1) from a main signal input (12) to a main signal output (11). The circuit (1) has a first signal path (18), from the input (12) to the output (11), along which a connectable and disconnectable first active unit (3) is arranged and also a second signal path (19) along which a connectable and disconnectable second active unit (4) and a 180 degrees phase shifting unit (2) are arranged. By a method a selection is made which of the active units (3,4) is to be in a connected condition after which control signals (U1,U2) to the units (3,4) sets them in a connected and disconnected condition respectively with the outcome of a transmission from the output (11), depending on the selection, either a non-phase shifted signal (V1') or a 180 degrees phase shifted signal (V2'). Depending on the function of the active units (3,4) the signal (V1',V2') can also be affected in other respects than its relative phase.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: June 20, 2000
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventor: Jacob Mannerstr.ang.le
  • Patent number: 5923227
    Abstract: A non-linear dispersive transmission line includes a plurality of substantially block-like shaped capacitor elements (4) arranged in sequence in at least two arrays. The even numbered elements (4b, 4d etc) extend side by side to form a first array and the odd numbered elements (4a, 4c) etc extend side by side to form the second array. Each element (4) in one array is connected via inductors (3) to two immediately adjacent elements in the other array. Facing surfaces (5) of each two immediately adjacent elements (4a, 4c) in each array form cross link capacitors.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: July 13, 1999
    Assignee: British Aerospace Public Limited Company
    Inventor: Nigel Seddon
  • Patent number: 5844460
    Abstract: Wound, solid state inductors are provided by winding flexible plastic tape having electrically insulative and magnetic permeability properties. Such tape is sometimes referred to as magnetic tape. An electrically conductive layer is placed on at least one surface of the magnetic tape, or both, and electrical connections are provided to the ends of the electrically conductive layer or layers. When the magnetic tape is wound into a coil, spirally or helically, and an alternating current is applied to the electrical connection, an inductive reactance will be noted. If there are two electrically conductive layers, and a voltage is applied between them, a capacitive reactance will be noted. In that case, a complex capacitive inductor element or inductive capacitor element has been configured. The wound inductors are small, light weight, inexpensive, and relatively shock proof, when compared with prior wound inductors having separate magnetic cones and wire windings placed over them.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: December 1, 1998
    Assignee: Dyalem Concepts Inc.
    Inventors: Alexei Bogdan, Emil S. Sagalovich
  • Patent number: 5825172
    Abstract: A rotating transmission line for use in spectrum up-scaling or down-scaling of signals. The rotating medium is characterized by different velocity gradients, whereby when a signal propagates in such medium, the signal undergoes a Doppler effect as it propagates through the moving medium.
    Type: Grant
    Filed: April 11, 1997
    Date of Patent: October 20, 1998
    Inventor: Gopalkrishna G. Nadkarni
  • Patent number: 5521568
    Abstract: An electrical delay line is described. Said line is free from early or late arriving false signals of sufficient amplitude to trigger subsequent stages in the circuitry. This has been accomplished through use of a novel approach to designing the delay line. Said approach is described and data is given comparing conventional delay lines with the present invention.
    Type: Grant
    Filed: April 4, 1995
    Date of Patent: May 28, 1996
    Assignee: Industrial Technology Research Institute
    Inventors: Ruey-Beei Wu, Fang-Lin Chao
  • Patent number: 5436601
    Abstract: Earth electrodes are formed on two layers. A capacitor electrode is formed on a layer therebetween. A capacitor is formed by the capacitor electrode and the earth electrodes. Coil electrodes are formed respectively on a plural number of layers. The plural number of coil electrodes are connected through a through hole. An intermediate portion of the connected coil electrodes is connected to the earth electrodes to form a transformer. A delay line is formed by connecting the capacitor electrode and the coil electrodes via external electrodes.
    Type: Grant
    Filed: January 18, 1994
    Date of Patent: July 25, 1995
    Assignee: Muraka Manufacturing Co., Ltd.
    Inventors: Harufumi Mandai, Noboru Kato, Akihiro Ochii
  • Patent number: 5389902
    Abstract: The size of the electromagnetic delay line is reduced by arranging chip capacitors in two rows in a staggered relationship along the lengthwise direction of a base board so that the overall length can be substantially reduced as compared to the conventional structure in which the chip capacitors are arranged in a single row. In particular, the height of the profile of the package for the electromagnetic delay line can be substantially reduced as compared to the comparable conventional ones. Furthermore, this electromagnetic delay line can cover a wide range of delay time while maintaining a same size and configuration, and offers stable and desirable properties. The present invention also offers an electric advantage in that the bridging capacitance is produced while the parallel capacitance is reduced. This contributes to the improvement in the performance of the electromagnetic delay line.
    Type: Grant
    Filed: November 9, 1993
    Date of Patent: February 14, 1995
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 5339056
    Abstract: A variable delay line includes a package housing (61); a circuit board (68) provided within the package housing; a ground conductor pattern (69) provided on a backside of the circuit board; an electrical circuit (70) provided on a top surface of the circuit board and including input and output terminal lands (72, 75); a plurality of pairs of shunt lands (76), each pair being connected by a microstrip line (77); a plurality of pairs of element connection lands (78), each being connected to a delay element (79, 80, 81); and a plurality of pairs of connecting contacts (67) movable between a first position in which the connecting contacts connect the shunt microstrip line in series to the electrical circuit and a second position in which the connecting contacts connect the delay element in series to the electrical circuit while disconnecting the shunt microstrip line from the electrical circuit, eliminating major mismatching elements from the delay line, thereby improving high-frequency characteristics.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: August 16, 1994
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Mitsunori Kaneko, Yukinori Miyake
  • Patent number: 5331298
    Abstract: A lumped constant type electromagnetic delay line employs an inductive device consisting of a plurality of turns of electroconductive wire in combination with chip capacitors connected to a plurality of taps provided in the inductive device so as to form a ladder circuit consisting of a plurality of delay circuit sections. The coil wire ends and the taps of the inductive device of the present invention are all twisted and extended in the same direction, and are all provided with a uniform and sufficient rigidity. Therefore, the process of connecting these taps and coil wire ends to the corresponding electrodes is simplified, and is therefore made better adapted for automatization. During the process of manufacture, a series of inductive devices can be fabricated as a continuous process of winding a coil wire around an elongated bobbin, and all the taps and coil wire ends are laterally extended and twisted in the same manner so that the entire process is significantly simplified.
    Type: Grant
    Filed: January 12, 1993
    Date of Patent: July 19, 1994
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 5177457
    Abstract: A variable delay line includes a housing package (20, 21); an input terminal (27) extending outwardly from a first side of the housing package; an output terminal (28) extending outwardly from a second side of the housing package which is opposite to the first side; a circuit board (23) provided within the housing package; an input terminal connection land (31) provided on the circuit board and connected to an end of the input terminal; an output terminal connection land (32) provided on the circuit board and connected to an end of the output terminal; a plurality of delay elements (36); a plurality of pairs of delay element connection fixed pads (33), each pair thereof connected to each of the delay elements; and a plurality of series connection fixed contact pads (34, 35) each corresponding to each pair of the delay element connection fixed pads and connectable in series across the input and output terminal connection lands.
    Type: Grant
    Filed: August 30, 1991
    Date of Patent: January 5, 1993
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Mitsunori Kaneko, Yukinori Miyake
  • Patent number: 5146191
    Abstract: A delay line device for delaying signal transmission. A lamination comprises an uppermost grounding electrode, a lowermost grounding electrode, a plurality of strip-line conductors, a plurality of intermediate grounding electrodes, dielectric layers, and protective layers. The strip-line conductors and the intermediate grounding electrodes are accumulated alternately and are interposed between the uppermost and the lowermost grounding electrodes. The dielectric layers are each interposed between each adjacent pair of the strip-line conductor and the intermediate grounding electrode. The protective layers are respectively provided on outer surfaces of the uppermost and the lowermost grounding electrodes. The strip-line conductors are connected via a through hole to form a strip-line conductor series and both ends of the series are extended onto a side surface of the lamination. An external input electrode is connected to one of the ends of the strip-line conductor series on the side surface of the lamination.
    Type: Grant
    Filed: June 10, 1991
    Date of Patent: September 8, 1992
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Harufumi Mandai, Yoshikazu Chigodo, Atsushi Tojo
  • Patent number: 5098528
    Abstract: A method for the making of an integrated type of LC component comprises the following steps;the coiling of an elongated element made of a metal with valve effect, the ends of which constitute two electrodes;the anodization of the element to form a dielectric layer;impregnation by an electrolyte, andthe positioning of a third electrode in a known way.Application to integrated passive components.
    Type: Grant
    Filed: June 26, 1991
    Date of Patent: March 24, 1992
    Assignee: Compagnie Europeene de Composants Electroniques LCC
    Inventors: Francois DeLalande, Dominique Poupard
  • Patent number: 5043671
    Abstract: An improvement in a device for the combination of two alternating signals of the same frequency in which two microwave combination devices are associated with two phase shifters to combine the two signals. By coupling the two phase shifters according to a particular coupling relationship, the two alternating signals are combined regardless of the load presented at one of the these two signals.
    Type: Grant
    Filed: November 27, 1989
    Date of Patent: August 27, 1991
    Assignee: CGR MeV
    Inventor: Duc Tien Tran
  • Patent number: 5030931
    Abstract: A flexible laminated delay line assembly formed to include a plurality of patterned regions which may be folded into sandwiched relation to one another without affecting electrical continuity. The transmission line layer is laminated between successively adjacent dielectric and ground plane layers. Windows cut into the ground plane and dielectric layers facilitate folding and decoupling of a support spine, folding of the conductor sections and sizing of the assembly. In one construction, the dielectric layers comprise a flexible insulative substrate laminated between upper and lower thermoset layers. In another construction the dielectric layers comprise a polyetherimide that is melt flowed about the pathways of the transmission line.
    Type: Grant
    Filed: May 16, 1989
    Date of Patent: July 9, 1991
    Assignee: Thin Film Technology Corporation
    Inventors: Mark Brooks, J. Paul Ozawa, Gary L. Seibel
  • Patent number: 5030932
    Abstract: This electromagnetic delay line is formed by disposing a ground electrode on one surface of a thin dielectric layer and serially connecting main electroconductive strips which are arranged in parallel at certain intervals on the opposite surface of the dielectric layer to form a zigzag strip to face the ground electrode and further, each main electroconductive strip itself is folded to be configured. Accordingly, the negative coupling produced in the zigzag strip is decreased and dispersed as well, thus improving the delay characteristics for the ultra-high frequency signal.
    Type: Grant
    Filed: July 5, 1989
    Date of Patent: July 9, 1991
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4967172
    Abstract: Disclosed are microwave phase shifter circuits which achieve phase shifts of elementary values and of whole number multiples of the values. The phase shifter circuit is made by utilizing of strip lines arranged in candlestick form on one face of a substrate and a slot line arranged on the other face. The length of the branches of the candlestick differ by b/4, b being the wavelength, and the ends of the branches are short-circuited or not short-circuited by utilizing of diodes which can be forward biased or reverse biased.
    Type: Grant
    Filed: March 28, 1989
    Date of Patent: October 30, 1990
    Assignee: Thomson-CSF
    Inventors: Joelle Ariel, Jacques Legendre
  • Patent number: 4961060
    Abstract: The disclosure concerns electromagnetic delay lines of the type having localized constants and being formed by a cascade of derived m networks. The chokes of the delay line are arranged in a folded line, the chokes of two consecutive networks being separated by a distance determined to obtain the desired parameter m, two non-neighboring chokes being separated by a distance sufficient to make their coupling negligible.
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: October 2, 1990
    Assignee: Compagnie Europeenne de Composants Electroniques LCC
    Inventors: Daniel Grandjean, Jean-Michel Seurre, Didier Zastko
  • Patent number: 4885562
    Abstract: According to the invention, the circuit comprises at least one two-port network of the "M-derived" section type and connected as an all-pass filter with a phase law which is a linear function of frequency. The two-port network is made in monolithic technology on gallium arsenide and the plane of its structure includes at least one elementary section, which, between an inlet and an outlet which are situated at a distance apart, is constituted by a spiral connected in parallel with a capacitor of metal-insulator-metal structure, with the mid point of the spiral being connected via another capacitor of metal-insulator metal structure to a ground plane. It is applicable to making transmission lines which are programamble in length.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: December 5, 1989
    Assignee: Electronique Serge Dassault
    Inventors: Pierre-Louis Ouvrard, Philippe Dueme
  • Patent number: 4800346
    Abstract: A lumped constant delay line has a substrate, capacitor element disposed on one surface of the substrate provided with a through hole therein, an inductor electrode which is dispossed on the other surface of the substrate and is connected to the capacitor elements by means of a through hole conductive section consisting of coated inside wall of the through hole by means of conductive adhesive and an inductor pin soldered onto the inductor electrode while a distributed constant type delay line has an insulating substrate on which a ferrite layer, an inductance layer, a dielectric layer and a ground electrode layer are superposed one after another and a wiper makes sliding on a wiper base composed of a group of parallel taps which are led out from the meandering paths of the inductance conductive layer and converged toward one side of the insulating substrate whereby to cause variation of delay time of the delay line.
    Type: Grant
    Filed: May 13, 1987
    Date of Patent: January 24, 1989
    Assignee: Delphi Company Ltd.
    Inventors: Masayauki Muramatsu, Toshiki Morozumi
  • Patent number: 4722027
    Abstract: In a hybrid circuit device comprising a base plate on which a circuit including coils is provided, and a flat package of integrated circuit having a smaller flat area than that of the base plate, the flat package and base plate are superimposed upon each other; the two circuits are connected together through terminals of the flat package; external terminals are connected to at least one of the two circuits; the hybrid circuit device is encapsulated with plastics as a whole, with the external terminals being exposed through the encapsulation; and on that part of the base plate which does not overlap the flat package, circuit components constituting the circuit provided on the base plate are securely mounted at lateral positions with respect to the flat package.
    Type: Grant
    Filed: August 5, 1986
    Date of Patent: January 26, 1988
    Assignee: Toko Inc.
    Inventor: Yasumitsu Hayakawa