Digital Comparator Systems Patents (Class 340/146.2)
  • Patent number: 10318291
    Abstract: A processor includes a vector register including data fields to store values of vector elements of data, a decoder to decode a single instruction multiple data (SIMD) instruction specifying a source operand and a mask to identify a masked portion of the data fields. An execution unit is to read a plurality of values from unmasked data fields of the plurality of data fields of the vector register; compare, within the vector register, each of the plurality of values from the unmasked data fields for equality with all other values of the plurality of values; and responsive to a detection of an inequality of any two values of the plurality of values, set a mask field, corresponding to a detected unequal value, to a masked state with a flip of a bit value of the mask field, to signal the detection of the inequality.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Charles R. Yount, Suleyman Sair, Kshitij A. Doshi
  • Patent number: 10284204
    Abstract: There are provided a logic unit circuit and a pixel driving circuit, which relate to a display technical field and are used to solve the problem that technical difficulties are increased due to mixed use of different types of transistors in the logic unit circuit. The logic unit circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor of a same type. The logic unit circuit is used to realize logic gate operation.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: May 7, 2019
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Xuehuan Feng, Bo Mao
  • Patent number: 10175943
    Abstract: An efficient hardware apparatus for calculating the maximum and/or minimum of two n-bit binary input values generates a number of separate select signals, each of which is then used to control the selection of a single bit from one of the two binary inputs. A select signal for an ith bit of the output depends upon bits [n?1, i] in each of the two binary inputs and based on the select signal the ith bit is selected from one of the two inputs.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: January 8, 2019
    Assignee: Imagination Technologies Limited
    Inventors: Theo Alan Drane, Thomas Michael Rose
  • Patent number: 10169451
    Abstract: A processor unit can be used to rapidly search a string of characters. The processor unit can include vector registers each having M vector elements, each vector element having n bits of data for containing an encoded character. An M×M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each diagonal of the matrix of comparators, and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. Correction logic within the processor unit can suppress indications of a partial match or of a full match in the bit vector.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stefan Payer, Razvan Peter Figuli, Cedric Lichtenau, Michael Klein
  • Patent number: 10091128
    Abstract: Dynamic history multistream long range compression (DHC) techniques are described for efficiently compressing multiple, prioritized data streams received over a channel. A history buffer is associated with each received stream and a DHC compressor dynamically allocates fixed sized history sections to and from each history buffer. In implementations, the DHC compressor makes stream history size adjustments prior to compressing a block of data and sends information identifying the change in history size to a DHC decompressor. The DHC decompressor sends signaling information to the DHC compressor that is used to ensure that the DHC decompressor can operate with a fixed amount of total history memory.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: October 2, 2018
    Assignee: Hughes Network Systems, LLC
    Inventors: Douglas Merrill Dillon, Uday R. Bhaskar
  • Patent number: 10089073
    Abstract: Apparatus and methods for conversion from signed integer to a floating point representation are provided. Two's complementation and lead zero count operations are performed in parallel. Exponent generation and mantissa shifting are performed in parallel. Generation of the floating point exponent from the signed integer, including application of a scaling factor, is performed using a 3:2 compressor or carry-save adder and an adder. Two's complementation for generation of the mantissa in unsigned integer format is performed using an adder. Lead zero count for controlling mantissa shifting is performed by one's complementing the signed integer if negative, counting lead zeros in the one's complement output, and determining, using the one's complement output, whether the one's complement lead zero count differs from the two's complement lead zero count by one.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 2, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Huong Ho, Michel Kafrouni
  • Patent number: 10061623
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S Farrell, Charles W Gainey, Jeffrey P Kubala, Donald W Schmidt
  • Patent number: 10055194
    Abstract: A method for performing an operation based on at least two operands is proposed, in which steps of the operation are performed in time-randomized fashion. In addition, an apparatus, a computer program product and a computer-readable storage medium are accordingly specified.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: August 21, 2018
    Assignee: Infineon Technologies AG
    Inventors: Stefan Heiss, Markus Rau
  • Patent number: 10055261
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S Farrell, Charles W Gainey, Jr., Jeffrey P. Kubala, Donald W Schmidt
  • Patent number: 10002147
    Abstract: The formulation of a merged sorted list from multiple input sorted lists in multiple phases using an array pair. Initially, the first array is populated with the input sorted lists. In the first phase, the first and second input sorted lists are merged into a first intermediary merged list within the second array. Each subsequent phase merges a prior intermediary merged list resulting from the prior phase and, a next input sorted list in the first array to generate a next intermediary merged list, or a merged sorted list if there or no further input in the first array. The intermediary merged lists alternate between the first array and the second array from one phase to the next phase.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: June 19, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jonathan David Goldstein, Badrish Chandramouli
  • Patent number: 9930052
    Abstract: A method for pattern matching finds a target pattern from a stream of patterns, both of the stream of patterns and the target pattern being comprised of elements. The method includes acquiring occurrence numbers of target elements in the target pattern, initializing the buffer, the buffer indicating a section in the stream of patterns, determining whether occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern, updating the buffer and then returning to the determining step, in response to determining that the occurrence numbers of the target elements in the buffer do not reach the occurrence numbers of the target elements in the target pattern, and outputting the elements in the buffer for subsequent processing, in response to determining that the occurrence numbers of the target elements in the buffer reach the occurrence numbers of the target elements in the target pattern.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dan U. Liu, Yang L. Liu, Yong Lu, Yong Feng Pan, Yan Ying
  • Patent number: 9928583
    Abstract: A scalable rank filter and method that performs rank filtering based on input data samples are disclosed. In one embodiment, the rank filter comprises a pipeline that receives input data samples and generates an output based on the input data samples as a result of completing execution of the pipeline. The rank filter includes output logic to determine the output prior completing execution of the pipeline and outputs an indication of a median.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: March 27, 2018
    Assignee: INTEL CORPORATION
    Inventor: Jun Nishimura
  • Patent number: 9905279
    Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: February 27, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Venkatraghavan Bringivijayaraghavan
  • Patent number: 9898285
    Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
  • Patent number: 9868418
    Abstract: A vehicle includes a gateway controller configured to interface a diagnostic port to a vehicle communication network. In response to a perimeter alarm system being in an armed state, transfer of messages from the diagnostic port to the vehicle communication network is inhibited. A change session diagnostic request received from the diagnostic port is transferred to the vehicle communication network in response to vehicle speed being less than a threshold and an ignition switch begin in a run position. The transfer of the change session diagnostic request is otherwise inhibited unless intended for a module designated for reprogramming keys.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: January 16, 2018
    Assignee: Ford Global Technologies, LLC
    Inventors: James M. Weinfurther, Eric Ramsay Paton, Aldi Caushi, Lisa T. Boran
  • Patent number: 9824017
    Abstract: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: November 21, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin Ho Han, Young Su Kwon, Kyoung Seon Shin
  • Patent number: 9792157
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: October 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: Mark S Farrell, Charles W Gainey, Jeffrey P Kubala, Donald W Schmidt
  • Patent number: 9779062
    Abstract: According to an embodiment, a computing apparatus includes a memory, and a processor. The memory stores N first vectors in a d-dimensional binary vector space consisting of binary values. The processor acquires a second vector in the d-dimensional binary vector space. The processor extracts M first vectors having a distance from the second vector satisfying a first condition out of the N first vectors, and calculate a distribution of distances of the M first vectors from the second vector. The processor acquires a first kernel function per a first distance between the M first vectors and the second vector in a first range. The processor generates a second kernel function based on the distribution and the first kernel functions. The processor calculates an occurrence probability of the second vector in the N first vectors based on the second kernel function.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: October 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Ito, Susumu Kubota, Tomohiro Nakai
  • Patent number: 9619500
    Abstract: Embodiments include methods, systems and computer program products for performing a tournament tree sort on a hardware accelerator. The method includes receiving a plurality of key values by the hardware accelerator, storing each the plurality of keys into a location on a memory of the hardware accelerator, and creating a pointer to each of the locations of the plurality of keys. The method also includes storing the pointer to each of the plurality of keys into a first array stored by the hardware accelerator, sorting the plurality of keys by ordering the pointers in the first array and by using a second array for storing the pointers, wherein the sorting identifies a winning key from the plurality of keys in the memory, and outputting the winning key.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh W. Asaad, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • Patent number: 9619499
    Abstract: Embodiments include methods, systems and computer program products for performing a tournament tree sort on a hardware accelerator. The method includes receiving a plurality of key values by the hardware accelerator, storing each the plurality of keys into a location on a memory of the hardware accelerator, and creating a pointer to each of the locations of the plurality of keys. The method also includes storing the pointer to each of the plurality of keys into a first array stored by the hardware accelerator, sorting the plurality of keys by ordering the pointers in the first array and by using a second array for storing the pointers, wherein the sorting identifies a winning key from the plurality of keys in the memory, and outputting the winning key.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh W. Asaad, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • Patent number: 9514481
    Abstract: Techniques are described herein for, among other things, selecting and/or modifying an ad based on an emotional state of a user. The user's emotional state is determined based on the user's online activity. Advertisement(s) are selected and/or modified for provision to the user based on the user's emotional state. An advertisement may be modified in any of a variety of ways. For example, a color that is included in an advertisement may be replaced with a different color. In another example, a color filter may be applied to the advertisement. In yet another example, visual attribute(s) of the advertisement may be modified. Examples of a visual attribute include, but are not limited to, hue, brightness, contrast, and saturation.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: December 6, 2016
    Assignee: EXCALIBUR IP, LLC
    Inventors: Varun Kumar, Srinivas Reddy Punur
  • Patent number: 9477473
    Abstract: This document discusses, among other things, systems and methods to receive an instruction to selectively update a value of one or more selected bits of a first register, to receive the one or more selected bits of the first register to be updated and one or more selected bits of the first register to remain unchanged, and to selectively update the value of the one or more selected bits of the first register using a first write port without receiving the value of the one or more selected bits of the first register. In an example, the value of the one or more selected bits of the first register can be updated without receiving the value of the first register, in certain applications, reducing the number of read ports required to update the value of the first register.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: October 25, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventor: Fei Sun
  • Patent number: 9479363
    Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: October 25, 2016
    Assignee: Rambus Inc.
    Inventor: Aliazam Abbasfar
  • Patent number: 9424308
    Abstract: A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: August 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Srivatsan Chellappa, Toshiaki Kirihata, Karthik V. Swaminathan
  • Patent number: 9418089
    Abstract: The formulation of a merged sorted list from multiple input sorted lists in multiple phases using an array pair. Initially, the first array is contiguously populated with the input sorted lists. In the first phase, the first and second input sorted lists are merged into a first intermediary merged list within the second array. Each subsequent phase merges a prior intermediary merged list resulting from the prior phase and, a next input sorted list in the first array to generate a next intermediary merged list, or a merged sorted list if there or no further input in the first array. The intermediary merged lists alternate between the first array and the second array from one phase to the next phase.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: August 16, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jonathan David Goldstein, Badrish Chandramouli
  • Patent number: 9350355
    Abstract: A semiconductor apparatus may include an operation signal input selection block configured to output one of either a first operation signal or a second operation signal, as a select signal, in response to an operation select signal. The semiconductor apparatus may include a target code selection block configured to output one of either a first target code or a second target code, as a select code, in response to the operation select signal. The semiconductor apparatus may include an enable signal generation block configured to generate an enable signal when a time corresponding to the select code passes, in response to the select signal. The semiconductor apparatus may include an operation signal output selection block configured to output the enable signal, as one of either a third operation signal or a fourth operation signal, in response to the operation select signal.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: May 24, 2016
    Assignee: SK HYNIX INC.
    Inventor: Jae Bum Ko
  • Patent number: 9208259
    Abstract: An approach is provided that uses symbols to represent search criteria. In this approach, a symbol is received from a user in a search request. Search criteria that corresponds to the received symbol is retrieved from a computer accessible data store. Data stores are searched for the plurality of search criteria that correspond with the received symbol and search results are retrieved based on the searching performed. These retrieved search results are then provided to the user.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Lisa Seacat DeLuca, Lydia M. Do
  • Patent number: 9146891
    Abstract: A timing control circuit includes a single chip having a plurality of output ports; a chip selecting circuit having a plurality of control ports connected to the output ports and paths; a signal input circuit; a signal output circuit; and a switching circuit including a plurality of signal channels. The chip selecting circuit generates a selection signal according to a control signal and outputs the selected signal via one of the selected paths. One of the channels is selected when a selection signal is output via the selected channel. When one of the signal channels is selected and there are signals inputted by the signal input circuit via the signal channel, the signals from the signal input circuit are passed to the signal output circuit through the signal channel and the light emitting diode in the signal channel is turned on.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: September 29, 2015
    Assignee: ShenZhen Treasure City Technology Co., LTD.
    Inventor: Guang-Chen Li
  • Patent number: 9136857
    Abstract: Representative implementations of devices and techniques provide analog to digital conversion of multiple parallel analog inputs. An input interface is arranged to organize the parallel analog inputs and an analog-to-digital converter (ADC) is arranged to sequentially convert the multiple parallel analog inputs to digital results.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: September 15, 2015
    Assignee: IFINEON TECHNOLOGIES AG
    Inventors: Peter Bogner, Franz Kuttner
  • Patent number: 9129455
    Abstract: A passive entry system is disclosed. The system comprises an unlocking module that performs a key operation in a keyless environment and a plurality of fobs configured to trigger the unlocking module to perform the key operation. each fob has a unique value associated thereto. The unlocking module determines a range of identification values, generates an authentication request packet based on the range, of identification values, and broadcasts the request packet. Each fob receives the request packet; and determines whether the unique identification value of the corresponding fob falls within the range of identification values. The fob also generates a response packet if the unique identification value falls within the range of identification values and transmits the response packet to the unlocking module. The unlocking module receives the response packets from the fobs, and performs the key operation based on one of the received response packets.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: September 8, 2015
    Assignee: FCA US LLC
    Inventor: Timothy K. Mitchell
  • Patent number: 9117241
    Abstract: An inputter can intuitively understand a numerical value input by himself/herself and the possibility of ignoring an erroneous input can be reduced. Only an Arabic numeral representing the input numerical value is displayed in a first display area. At least one of (i) a character string comprising an Arabic numeral and a character or a character string other than the Arabic numeral and (ii) only a character or a character string other than the Arabic numeral, which represents the input numerical value, is displayed in a second display area.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: August 25, 2015
    Assignee: Rakuten, Inc.
    Inventor: Hisanori Yamahara
  • Patent number: 8935095
    Abstract: Various embodiments of a device, system and methods that promote safety and security within an organization. Sensor data from one or more installation sensors is collected, analyzed and used to create a map and/or directions that, when received by a wireless mobile device, facilitate a person's possible egress around or from a detected event. The information provided to the person by the map and/or the directions may be individually crafted to be of maximum use to the specific recipient so the person can understand, plan and execute the most appropriate danger avoidance maneuvers in minimal time.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: January 13, 2015
    Assignee: UTC Fire & Security Americas Corporation, Inc.
    Inventors: Michael James Hartman, John E. Hershey, Robert J. Mitchell, Jr.
  • Patent number: 8907798
    Abstract: An ice detection system comprising a first group of sensors and a second group of sensors. The first group of sensors is located in a first group of locations on an aircraft. The first group of sensors in the first group of locations is configured to detect a first type of icing condition for the aircraft. The second group of sensors is located in a second group of locations on the aircraft. The second group of sensors in the second group of locations is configured to detect a second type of icing condition for the aircraft.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: December 9, 2014
    Assignee: The Boeing Company
    Inventors: Charles Steven Meis, Cris Kevin Bosetti
  • Patent number: 8751557
    Abstract: Embodiments of methods, apparatuses, devices and/or systems for manipulating character expressions to determine relationships among such character expressions.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: June 10, 2014
    Assignee: Robert T. and Virginia T. Jenkins
    Inventors: Richard Crandall, Karl Schiffmann
  • Patent number: 8688291
    Abstract: A vehicle control system for data exchange in a transport system, where a control unit is configured to transfer control commands to a vehicle configured to transfer status messages to the control unit, where a signal generator is connected to a first data line and a second data line and provides a changeover signal, a first switching means is arranged in the control unit and is configured to change positive half-waves of the changeover signal, and a second switching means is arranged in the vehicle and is configured to change negative half-waves of the changeover signal, in a circuit formed by the first and second data lines to transfer binary values back-and-forth between the control unit and the vehicle.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 1, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventors: Stephan Rupf, Horst Wolf
  • Patent number: 8554823
    Abstract: The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2?b2+c2) with (x2+y2+z2); and (a3+b3?c3) with (x3+y3+z3); implementing an efficient method of computing (a4?b4?c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy D. Anderson, Shriram D. Moharil
  • Patent number: 8487772
    Abstract: A system and method for effectively communicating information using at least one mode of communication is described, in which information recipients proximate to a communications device within a pre-determined space and during a pre-determined time period are identified, from whom physiological state information is obtained that, when coupled with other characteristics information, is used to select from a plurality of information elements at least one information element to better target the information elements. The information element is then provided to the communications device so that it may be provided to the information recipients in the pre-determined space in a manner that is sensed by the information recipients.
    Type: Grant
    Filed: December 12, 2009
    Date of Patent: July 16, 2013
    Inventor: Brian William Higgins
  • Patent number: 8384522
    Abstract: Methods of determining patch cord connectivity information include receiving, at each of a plurality of RFID readers, a signal from an RFID tag that is associated with a first patch cord and then, identifying the one of a plurality of connector ports that the first patch cord is connected to based at least in part on respective strengths of the signals received at each of the plurality of RFID readers. RFID triangulation systems and methods of calibrating such systems are also provided.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: February 26, 2013
    Assignee: CommScope, Inc. of North Carolina
    Inventors: Daniel W. Macauley, Peter T. Tucker
  • Patent number: 8271162
    Abstract: A management system using Global Positioning System receivers for tracking remote units from a central office and quickly and conveniently determining if those remote units have varied from a set of predetermined parameters of operation. The system also includes provisions that allows information to be sent from the remote units to the central office and vice versa. The system also has safety features that promote the rapid dispatch of law enforcement personnel when requests for emergency assistance have been made from the remote units.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: September 18, 2012
    Assignee: AT&T Intellectual Property I, LP
    Inventors: Marvin R. Hamrick, R. T. Mitchell Ingman
  • Patent number: 8253546
    Abstract: A magnitude comparator for comparing magnitude of a first data and a second data is disclosed. The first data and the second data are both binary data. The magnitude comparator includes many non-least comparator cells and a P-channel transistor. Each of the non-least comparator cells includes a first transistor, a second transistor, a third transistor and a fourth transistor. The drain of the second transistor is electrically connected to the source of the first transistor, and the source of the second transistor is electrically connected to a ground terminal. The third transistor electrically connects the first transistor, and the fourth transistor electrically connects the first transistor and the third transistor. The source of the P-channel transistor electrically connects a supply terminal, the gate of the P-channel transistor electrically connects the ground terminal, and the drain of the P-channel transistor electrically connects the third transistor of the first comparator cell.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: August 28, 2012
    Assignee: National Changhua University of Education
    Inventor: Tsung-Chu Huang
  • Patent number: 8073893
    Abstract: Embodiments of methods, apparatuses, devices and/or systems for manipulating character expressions to determine relationships among such character expressions.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: December 6, 2011
    Inventors: Richard Crandall, Karl Schiffmann
  • Patent number: 7991987
    Abstract: A shorter and a longer text string may be compared. Instead of simply comparing the characters only one character at a time, more than one character can be compared at a time. In addition, a null terminated string may be detected. The shorter strings may be handled differently than longer strings.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventor: Mason Cabot
  • Patent number: 7970504
    Abstract: A system which operates a digitally controlled model railroad transmitting a first command from a first client program to a resident external controlling interface through a first communications transport. A second command is transmitted from a second client program to the resident external controlling interface through a second communications transport. The first command and the second command are received by the resident external controlling interface which queues the first and second commands. The resident external controlling interface sends third and fourth commands representative of the first and second commands, respectively, to a digital command station for execution on the digitally controlled model railroad.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: June 28, 2011
    Inventor: Matthew A. Katzer
  • Publication number: 20110148605
    Abstract: A magnitude comparator for comparing magnitude of a first data and a second data is disclosed. The first data and the second data are both binary data. The magnitude comparator includes many non-least comparator cells and a P-channel transistor. Each of the non-least comparator cells includes a first transistor, a second transistor, a third transistor and a fourth transistor. The drain of the second transistor is electrically connected to the source of the first transistor, and the source of the second transistor is electrically connected to a ground terminal. The third transistor electrically connects the first transistor, and the fourth transistor electrically connects the first transistor and the third transistor. The source of the P-channel transistor electrically connects a supply terminal, the gate of the P-channel transistor electrically connects the ground terminal, and the drain of the P-channel transistor electrically connects the third transistor of the first comparator cell.
    Type: Application
    Filed: November 25, 2010
    Publication date: June 23, 2011
    Applicant: NATIONAL CHANGHUA UNIVERSITY OF EDUCATION
    Inventor: Tsung-Chu HUANG
  • Patent number: 7960927
    Abstract: An electric motor control device includes a power supply unit that supplies power to a three-phase electric motor; a three-phase current sensor that individually detects three respective phase currents of the three-phase electric motor; a summing unit that calculates a three-phase sum by adding the three phase currents detected by the three-phase current sensor; a detected current correction unit that calculates correction amounts for at least two of the three phase currents based on a phase and an amplitude of the three-phase sum and then corrects phase current detection values by the calculated correction amounts; and a motor control unit that controls a power supply by the power supply unit to the three-phase electric motor by feedback control based on the three phase currents after correction by the detected current correction unit and on target currents.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: June 14, 2011
    Assignee: Aisin AW Co., Ltd.
    Inventor: Zhiqian Chen
  • Patent number: 7958181
    Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on the first and second data. The logical comparisons may be performed on each bit of the first and second data, or may be performed only on certain bits. For at least one embodiment, at least the first data includes packed data elements, and the logical comparisons are performed on the most significant bits of the packed data elements. The logical comparisons may include comparison of the same respective bits of the first and second data, and also includes logical comparisons of bits of the first data with the complement of the corresponding bits of the second data. Based on these comparisons, branch support actions are taken.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: June 7, 2011
    Assignee: Intel Corporation
    Inventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
  • Patent number: 7825777
    Abstract: An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n?1, . . . , 0]) and a second n-bit operand (e.g., B[n?1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal Co (or its complement), where: C o = ( … ? ( ( C i ? ( A 0 + B 0 _ ) + A 0 ? B 0 _ ) ? ( A 1 + B 1 _ ) + A 1 ? B 1 _ ) ? … ? ( A n - 2 + B n - 2 _ ) + A n - 2 ? B n - 2 _ ) ? ( A n - 1 + B n - 1 _ ) + A n - 1 ? B n - 1 _ , “n” is a positive integer greater than one and Ci is a control input signal that specifies an interpretation to be given to the control output signal Co.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: November 2, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventors: Tingjun Wen, David Walter Carr, Tadeusz Kwasniewski
  • Patent number: 7602534
    Abstract: A CPU and an image memory are provided in a printing apparatus. An interface circuit device for inputting/outputting signals representing image data is interposed between the CPU and the image memory. The interface circuit device constitutes of a plurality of SSTL circuits. One of two adjoining pixels in image data is changed into a non-inverted pixel, and the other is changed into an inverted pixel. In the SSTL circuits, to which inputted is a signal representing the one pixel, an input signal is inputted so as not to invert an input signal. In the SSTL circuits, to which inputted is a signal representing the other pixel as an inverted element, an input signal is inputted to the inverted element so as to invert an input signal. This suppresses an increase in cost and an increase in the size of a device, while reducing the current in impedance matching.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: October 13, 2009
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventor: Keiichi Tanii
  • Publication number: 20090240393
    Abstract: A method for controlling for improper installation of sensors of a vehicle is provided. The method comprises the steps of determining a first indication of direction based at least in part on a yaw value, determining a second indication of direction based at least in part on a steering angle value, and changing the second indication of direction, if the first indication of direction and the second indication of direction are inconsistent with one another.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 24, 2009
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, INC.
    Inventors: Thomas H. Tu, Steven R. Abram, Paul S. Shaub
  • Patent number: 7561023
    Abstract: An electrical circuit for comparing contents of counter circuits. The electrical circuit comprises a first counter circuit and a second counter circuit electrically connected to a flip-flop circuit through a logic circuit and OR gates connected to the flip flop circuit. The first counter circuit is for receiving a first enable signal and generating a first output signal. The second counter circuit is for receiving a second enable signal and generating a second output signal. The first enable signal and the second enable signal are for comparing the first output signal to the second output signal. The flip-flop circuit is for generating a first status signal defining a first relationship between the first output signal and the second output signal. The logic circuit is for generating a second status signal defining a second relationship between the first output signal and the second output signal.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: July 14, 2009
    Assignee: International Business Machines Corporation
    Inventors: Shridhar N. Ambilkar, Girish G. Kurup