Plural Stages Patents (Class 340/2.21)
  • Patent number: 11706041
    Abstract: This disclosure describes techniques for improved multicast network telemetry implemented over multilayer switches in a PIM domain. The multilayer switches may be configured to collectively certify end-to-end flow provisioning, and to publish telemetry data certifying flow provisioning from a single notifier to an external controller host. Computational workload and network traffic for streaming data related to certifying path provisioning is kept to a minimum for each flow that needs to be certified, which also keeps compounding of network traffic for many different flows to a minimum. Moreover, since controller hosts are notified upon successful provisioning but not at other times, controller hosts can trust that the telemetric data is minimally latent, and may be relied upon to enact timely actions which produce desired outcomes.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: July 18, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Rishi Chhibber, Roshan Lal, Padmanab Pathikonda, Francesco Meo, Ramakrishnan Chokkanathapuram Sundaram
  • Patent number: 10979366
    Abstract: Significantly optimized multi-stage networks, useful in wide target applications, with VLSI layouts using only horizontal and vertical hop wires to route large scale computational blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of partial multi-stage hierarchical networks are presented. The optimized multi-stage networks comprising partial multi-stage hierarchical networks employ one or more rings of stages of switches with inlet and outlet links of computational blocks connecting to rings from either left-hand side, or from right-hand side, or from both left-hand side and right-hand side and employ hop wires from outlet links of switches of a first stage of a first ring of a first partial multi-stage hierarchical network are connected to either inlet links of switches of the first or a second stage of the first or a second ring of the first or a second partial multi-stage hierarchical network.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: April 13, 2021
    Assignee: Konda Technologies Inc.
    Inventor: Venkat Konda
  • Patent number: 10887419
    Abstract: Processing a purge request is disclosed. In an embodiment, the purge request is received from a node, where the purge request is for a next purge instruction and the node has an associated queue of purge instruction(s) with associated timestamps. In response to receiving the purge request, providing an unprocessed purge instruction having a time stamp before a threshold time. After processing the purge instruction having a timestamp before the threshold time, processing the remaining purge instructions as follows: indicating an availability state of the node as transitional, storing a current time value as a reference time value, processing in chronological order those remaining purge instructions in the queue with a time value chronologically before the reference time value, and indicating an availability state of the node as available.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 5, 2021
    Assignee: Akamai Technologies, Inc.
    Inventors: Ashok Anand, Manjunath Bharadwaj Subramanya
  • Patent number: 10594500
    Abstract: A method and a device are provided for managing, in a receiving entity, data packets received from a transport layer connection established with a transmitting entity. The connection includes at least one stream in connected mode and at least one stream in non-connected mode. The management method includes transmitting, by the receiving entity, a so-called return message, relating to at least one data packet from one of the two streams in connected mode or in non-connected mode of the connection, the return message being transmitted to the transmitting entity on the other stream of the connection.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: March 17, 2020
    Assignee: ORANGE
    Inventors: Emile Stephan, Arnaud Braud, Joel Penhoat
  • Patent number: 10312969
    Abstract: A system for controlling a subsea device comprises a complimentary set of data communication interfaces operatively coupled to an electronically interrogatable component of a subsea device and a remotely disposed device controller via a power conductor which defined data pathway between the subsea device and the remotely disposed device controller. A data transceiver is operatively coupled to the electronically interrogatable component and the remotely disposed device controller via the complimentary set of data communication interfaces over the power conductor. In configurations, control and/or telemetry or other data may be unidirectionally and/or bidirectionally transmitted between the electronically interrogatable component of a subsea device and a remotely disposed device controller.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: June 4, 2019
    Assignee: Oceaneering International, Inc.
    Inventors: Kevin Frances Kerins, Mark Charles Philip
  • Patent number: 10313473
    Abstract: A system for processing a purge request is disclosed. The purge request is received. An availability state for each content distribution node in a group of content distribution nodes is stored. Based on the purge request, one or more purge instructions are generated for one or more available state content distribution nodes of the group. Based on the purge request, one or more delayed purge instructions are queued for one or more unavailable state content distribution nodes of the group. It is determined that the one or more available state content distribution nodes of the group have completed processing the one or more purge instructions generated for the one or more available state content distribution nodes. Based at least in part on the queuing of the one or more delayed purge instructions for the one or more unavailable state nodes, it is confirmed that the purge request has been completed.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: June 4, 2019
    Assignee: Instart Logic, Inc.
    Inventors: Ashok Anand, Manjunath Bharadwaj Subramanya
  • Patent number: 10146716
    Abstract: A method for using a shared device and a resource sharing system are provided. An arbitrator node sets an initial weight of each of processors based on identification information. The arbitrator node calculates a priority score for each processor based on an initial weight of each of the processors and state diagnostic codes recorded by each processor to establish a priority sequence. When the arbitrator node simultaneously receives a request for requesting an access right of the shared device transmitted by each of two or more processors, the arbitrator node determines one of the processors having the access right of the shared device based on the priority sequence.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: December 4, 2018
    Assignee: Wiwynn Corporation
    Inventors: Min-Chien Chang, Chih-Yuan Hung
  • Patent number: 9755749
    Abstract: Disclosed are an ONU, a communication system and a communication method for an ONU. The ONU provided in the present disclosure includes a processing module and at least two user interface modules. At least two ONU sub-modules are disposed in the processing module. The disposed ONU sub-modules are corresponding to the user interface modules in a one-to-one manner. Each ONU sub-module processes the user side data from a corresponding user interface module.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: September 5, 2017
    Assignee: ZTE CORPORATION
    Inventor: Rihong Wang
  • Patent number: 9706274
    Abstract: A large-scale switching system configured as a global network or a large-scale data center employs switches arranged in a matrix having multiple rows and multiple columns. The switching system supports a large number of access nodes (edge nodes). Each access node has a channel to each switch in a respective row and a channel from each switch of a respective column. Thus, an access node connects to input ports of a set of switches and output ports of a different set of switches. Each access node has a path to each other access node traversing only one of the switches. Controllers of switches of each diagonal pair of switches are integrated or mutually coupled to provide a return control path for each access node. The switches may be arranged into constellations of collocated switches to facilitate edge-node access to switches using wavelength-division-multiplexed links. The switches are preferably fast optical switches.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: July 11, 2017
    Inventor: Maged E. Beshai
  • Patent number: 9596524
    Abstract: A network of global coverage, scalable to an access capacity of hundreds of petabits per second, is configured as independent bufferless switches with spectral routers connecting edge nodes to the switches. The switches are logically arranged in at least one matrix, the spectral routers are logically arranged into a matrix of upstream spectral routers and a matrix of downstream spectral routers. Each edge node has a link to an upstream spectral router in each column of the matrix of upstream spectral routers and a link from a downstream spectral router in each row of the matrix of downstream spectral routers. Preferably, all sets of edge nodes connecting to the upstream spectral routers are selected to be mutually orthogonal. Each switch is coupled to a respective switch controller and a respective time indicator. Each switch controller entrains time indicators of a set of subtending edge nodes to enable coherent switching.
    Type: Grant
    Filed: October 20, 2012
    Date of Patent: March 14, 2017
    Inventor: Maged E. Beshai
  • Patent number: 9549040
    Abstract: Processing a purge request is disclosed. The purge request is received. Based on the purge request, a purge instruction is generated for each content distribution node of a group of one or more content distribution nodes. Each content distribution node of the group is verified has either completed processing the purge instruction or is determined to be unavailable. Despite at least one content distribution node of the group determined to be unavailable having not completed processing the purge instruction, an indication is authorized that the purge request has been completed.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: January 17, 2017
    Assignee: Instart Logic, Inc.
    Inventors: Ashok Anand, Manjunath Bharadwaj Subramanya
  • Patent number: 9548778
    Abstract: A device for switchably routing down-converted radio frequency (RF) signals from a plurality of inputs to a plurality of outputs, and a method of operating the same. The device includes a respective switch for each output. The device also includes an interconnect arrangement. The interconnect arrangement includes a respective transmission line for each input. Each transmission line includes a plurality of branches for routing a down-converted RF signal received at the input of that transmission line to the switch of each output. The switch of each output is operable selectively to connect one of the transmission lines to its output. The interconnect arrangement also includes a plurality of cross-over points at which two of the branches cross over each other.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: January 17, 2017
    Assignee: NXP B.V.
    Inventor: Serge Bardy
  • Patent number: 8897133
    Abstract: A multi-stage switch fabric (SF) is provided. The multi-stage SF includes a line card chassis (LCC) and a fabric card chassis (FCC). The FCC includes a stage-1 switch element (S1), a stage-2 switch element (S2), and a stage-3 switch element (S3), where the S3 corresponds to the S1, and the S2 is coupled to the S1 and S3 respectively. The LCC includes an interface component and a line card (LC) coupled to the interface component, where the interface component is coupled to the S1 and S3 in the FCC respectively. Through the technical solution under the present invention, when a switch element generates flow control information and requires another switch element or an LC to respond to the flow control information, a timely response can be received.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: November 25, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Yun Lin
  • Patent number: 8300650
    Abstract: Examples of are disclosed for configuring one or more routes through a three-stage Clos-network packet switch.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: October 30, 2012
    Assignee: New Jersey Institute of Technology
    Inventors: Roberto Rojas-Cessa, Chuan-Bi Lin
  • Patent number: 7835357
    Abstract: In one embodiment, a method, comprising producing a first policy vector based on a first portion of a data packet received at a multi-stage switch. The method also includes producing a second policy vector based on a second portion of the data packet different than the first portion of the data packet. A third policy vector is produced based on a combination of at least the first policy vector and at least the second policy vector. The third policy vector including a combination of bit values configured to trigger an element at the multi-stage switch to process the data packet.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: November 16, 2010
    Assignee: Juniper Networks, Inc.
    Inventors: Ramesh Panwar, Deepak Goel, Srinivasan Jagannadhan, Jean-Marc Frailong
  • Patent number: 7719405
    Abstract: A method of operating a circuit for processing a digital signal is disclosed. The circuit includes various circuit stages having respective enabled states. A present signal path is established which includes circuit stages in their respective enabled states. Power is disabled to selected circuit stages not used in the present signal path so as to minimize power consumption in the disabled circuit stages. A data signal is then processed through the circuit stages in the present signal path. Before a next signal path is needed, power is re-enabled to selected disabled circuit stages in the next signal path to allow the enabled circuit stages to approach their respective enabled states. Then the next signal path can be established including the enabled circuit stages in their respective enabled states. The data signal can then be processed through the circuit stages in the next signal path.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: May 18, 2010
    Assignee: Analog Devices, Inc.
    Inventors: Daniel J. Mulcahy, Kimo Y. F. Tam
  • Patent number: 7592894
    Abstract: A data-communications switch having at least two modes of operation is provided. The data communications switch includes a first Clos switch having a first mode of operation and a second Clos switch, which is combined with the first Clos switch, for providing a second mode of operation. The first Clos switch and second Clos switch are interconnected in an overlapping manner to form a switch fabric, which is essentially a superset of both the first Clos switch and the second Clos switch and can be configured to operate in either mode depending on system requirements.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: September 22, 2009
    Assignee: Ciena Corporation
    Inventor: Anthony Torza
  • Publication number: 20080315985
    Abstract: In a switch system L groups of the line switch elements are connectable to cables that include L links such that each of the L links within a cable connect to a switch element of a respective one of the L groups. Fabric switch elements are connected such that a fabric switch element is connected to the line switch elements of one of the group of line switch elements.
    Type: Application
    Filed: January 17, 2008
    Publication date: December 25, 2008
    Applicant: Sun Microsystems, Inc.
    Inventors: Bjorn Dag Johnsen, Ola Torudbakken, Andreas Bechtolsheim
  • Patent number: 7424011
    Abstract: A rearrangeably nonblocking multicast network includes an input stage having r1 switches and n1 inlet links for each of r1 switches, an output stage having r2 switches and n2 outlet links for each of r2 switches. The network also has a middle stage of m switches, and each middle switch has at least one link connected to each input switch for a total of at least r1 first internal links and at least one link connected to each output switch for a total of at least r2 second internal links, where m?n1+n2. The network has all multicast connections set up such that each multicast connection passes through at most two middle switches to be connected to the destination outlet links.
    Type: Grant
    Filed: November 27, 2004
    Date of Patent: September 9, 2008
    Assignee: Teak Technologies, Inc.
    Inventor: Venkat Konda
  • Patent number: 7277428
    Abstract: A cross connect switch has a plurality of stages. Each stage has a plurality of packers, a plurality of memory portions and a plurality of multiplexers. Each packer receives input data and provides the input data as a set of contiguous valid data. The multiplexers divide the valid data from one of the packers into a plurality of data subsets and route each data subset to a respective memory portion of that stage. Each stage except the final stage provides the data in the memory portions of that stage as a respective set of inputs to a next one of the stages. The final stage includes a plurality of multiplexers for selecting a respective subset of the data from each of the memory portions of the final stage and provides the selected data at a plurality of respective selected output ports.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: October 2, 2007
    Assignee: Lucent Technologies Inc.
    Inventor: Michael B. Libeskind
  • Patent number: 7205881
    Abstract: An interconnection network has a first stage network and a second stage network and a collection of devices outside the network so that a first device is capable of sending data to a second device. The first stage network is connected to inputs of the second stage network. The first and second stage networks each have more outputs than inputs. The data is first sent from the first device to the first stage network and then from the first stage network to the second stage network. The data is sent to the second device from the second stage network. The number of inputs to a device from the second stage network exceeds the number of outputs from a device into the first stage network. The latency through the entire system may be a fixed constant.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: April 17, 2007
    Assignee: Interactic Holdings, LLC
    Inventors: Coke S. Reed, David Murphy
  • Patent number: 7184432
    Abstract: A switch is provided that receives user information through a plurality of framer circuits, which group the user information into frames. The frames are fed to a switch fabric including an array of switch elements, each having a switch matrix for routing each frame to a desired output in accordance with configuration data stored in a first table coupled to the switch matrix. If different outputs are desired, i.e., the switch matrix is to be reconfigured, a switch control circuit supplies additional switch configuration data to the frames through the inputs along with additional user information to be routed through the switch. While the additional switch configuration data is stored in a second table, data flow remains uninterrupted through the switch matrix.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: February 27, 2007
    Assignee: CIENA Corporation
    Inventors: Joel F. Adam, Darren Engelkemier, Daniel E. Klausmeier
  • Patent number: 7065076
    Abstract: An embodiment of the present invention is disclosed to include a three stage scalable switching network that can be built from a common module. Further disclosed are methods for building switching network v(k, n, m) from a common module comprising a (n×k) input switch, a (k?×k?) middle switch, and a (k×n) output switch.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: June 20, 2006
    Assignee: Promise Technology, Inc.
    Inventor: Siamack Nemazie
  • Patent number: 7035254
    Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: April 25, 2006
    Assignee: Industrial Technology Research Institute
    Inventor: Shuo-Yen Robert Li
  • Patent number: 7020135
    Abstract: A switch is provided that includes three stages. The first stages has a plurality of switch circuits. The second stage has a plurality of switch circuits equal to N, where N is any integer other than a power of 2 and where the switch circuits can be logically configured into a logical configuration of a power of 2. The third stages includes a plurality of switch circuits.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: March 28, 2006
    Assignee: CIENA Corporation
    Inventors: Daniel E. Klausmeier, Jeffrey T. Gullicksen
  • Patent number: 6982975
    Abstract: In a packet switch structured by connecting unit switches in multi-stages which is capable of transmitting packets without delay and accommodating high-speed lines, unit switches at the first stage assign, to an input packet, a sequence number according to a destination of the packet and distribute and send out the packet to a unit switch at the succeeding stage and unit switches at the final stage sequence and output packets according to sequence numbers assigned to packets received from a unit switch at the preceding stage.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: January 3, 2006
    Assignee: NEC Corporation
    Inventors: Toshiya Aramaki, Kazuhiko Isoyama
  • Patent number: 6885663
    Abstract: A time/space switching component is provided with multiple functionality that includes a time switching unit, of a space switching unit of a data channel sequence correction unit and of a control unit. As a result of corresponding mode selection, the different functionalities for a switching network are obtained with a single component, resulting in a significant reduction in an overall expenditure for development and manufacture.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: April 26, 2005
    Assignee: Siemens Aktiengesellschaft
    Inventors: Karsten Laubner, Marcel-Abraham Troost
  • Patent number: 6816486
    Abstract: A chassis for holding modules including a set of first modules oriented horizontally in the chassis and a set of second modules oriented vertically in the chassis. A midplane is oriented orthogonally to the sets of first and second modules. The midplane has connector pins extending from its first side through its second side. Each of the first modules has a first connector for mating with the connector pins extending from the first side, and each of the second modules has a second connector for mating with the connector pins extending from the second side.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: November 9, 2004
    Assignee: Inrange Technologies Corporation
    Inventor: William Paul Rogers
  • Patent number: 6714537
    Abstract: A switch is provided that receives user information through a plurality of framer circuits, which group the user information into frames. The frames are fed to a switch fabric including an array of switch elements, each having a switch matrix for routing each frame to a desired output in accordance with configuration data stored in a first table coupled to the switch matrix. If different outputs are desired, i.e., the switch matrix is to be reconfigured, a switch control circuit supplies additional switch configuration data to the frames through the inputs along with additional user information to be routed through the switch. While the additional switch configuration data is stored in a second table, data flow remains uninterrupted through the switch matrix.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: March 30, 2004
    Assignee: Ciena Corp.
    Inventors: Joel F. Adam, Darren Engelkemier, Daniel E. Klausmeier
  • Patent number: 6696917
    Abstract: A novel folded Clos switch apparatus and method therefore for reducing the number of unemployed I/O terminals of a multistage Clos switching network by partitioning a crossbar switch to provide both the first (yth) and last (x−y+1th) stage of a multistage Clos switch where x is the total number of stages in the general case.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: February 24, 2004
    Assignee: Nortel Networks Limited
    Inventors: Michael L. Heitner, Jian J. Song, Rudy Vianna
  • Patent number: 6531953
    Abstract: A method of controlling detouring in an integrated network which includes communication devices includes the steps of registering routes at a communication device connected to terminal devices of respective media types such that the routes include a main route and a detour route with respect to each of the media types, and establishing a connection along the detour route registered for a media type upon finding unavailability of the main route registered for the media type when a call of the media type is requested from one of the terminal devices.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: March 11, 2003
    Assignee: Fujitsu Limited
    Inventor: Shinichiro Matsuo
  • Patent number: 6525650
    Abstract: A high density electronic switching matrix (ESM) includes several splitting modules (200) arranged along a first axis, each including a signal input (202) and several splitter outputs (204). The ESM (500, 600) further includes several switching modules (400) arranged along a second axis perpendicular to the first axis. Each switching module (400) includes switching inputs (402) coupled individually to an output of each of the splitting modules (200). The ESM (500, 600) is further characterized by couplings between the splitter modules and the switching modules. The couplings are formed by mating male and female connectors (300) integrated into the splitting modules and the switching modules. The couplings support extremely high frequency operation. The splitting modules (200) and the switching modules (400) may thus be coupled closely together to form a dense, high frequency, switching matrix, and may be stacked upon one another.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: February 25, 2003
    Assignee: TRW Inc.
    Inventors: Steven S. Chan, George M. Hayashibara, Chun-Hong Harry Chen, Davie C. Liu
  • Patent number: 6430179
    Abstract: A multi-stage signal router includes a clocked storage element connected to each output of each stage of the router. Each clocked storage element is responsive to a trigger event of a clock signal to capture a signal level present at the output to which it is connected and hold the signal level at its own output until a subsequent trigger event of the clock signal.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: August 6, 2002
    Assignee: ADC Telecommunications, Inc.
    Inventor: Charles S. Meyer
  • Publication number: 20020031118
    Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.
    Type: Application
    Filed: June 15, 2001
    Publication date: March 14, 2002
    Inventors: Shuo-Yen Robert Li, Lu Wa Chiang
  • Patent number: 6343075
    Abstract: A switch is provided that includes three stages. The first stages has a plurality of switch circuits. The second stage has a plurality of switch circuits equal to N, where N is any integer other than a power of 2 and where the switch circuits can be logically configured into a logical configuration of a power of 2. The third stages includes a plurality of switch circuits.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: January 29, 2002
    Assignee: CIENA Corporation
    Inventors: Daniel E. Klausmeier, Jeffrey T. Gullicksen