Abstract: System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.

Abstract: A first protocol stack for communication on a first physical line is implemented. At least parts of a second protocol stack for communication on a second physical line are implemented. The first protocol stack and the second protocol stack are bonded at the Physical Medium Dependent layer of the first protocol stack and the Physical Medium Dependent layer of the second protocol stack (172). In some scenarios, the bonding may be at an upper edge of the Physical Medium Dependent layer, i.e., at the ? interface.

Abstract: A facility is provided for automatically generating design data for a semiconductor circuit including a crossbar switch. The method includes synthesizing the crossbar switch using predefined multiplexer building blocks, where the predefined multiplexer building blocks include at least a multiplexer, an input driver and a select driver. In addition, the method includes regularly placing the predefined multiplexer building blocks to define a crossbar switch arrangement, testing the crossbar switch arrangement for timing constraints and re-synthesizing the crossbar switch and/or replacing the predefined multiplexer building blocks based on the testing.

Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

Abstract: According to an example, a multi-mode agent may include a processor interconnect (PI) interface to receive data from a processor and to selectively route the data to a node controller logic block, a central switch, or an optical interface based on one of a plurality of modes of operation of the multi-mode agent. The modes of operation may include a glueless mode where the PI interface is to route the data directly to the optical interface and bypass the node controller logic block and the central switch, a switched glueless mode where the PI interface is to route the data directly to the central switch for routing to the optical interface, and bypass the node controller logic block, and a glued mode where the PI interface is to route the data directly to the node controller logic block for routing to the central switch and further to the optical interface.

Abstract: Techniques are generally described related to a multi-channel storage system. One example multi-channel storage system may include a plurality of memory-controllers, each memory-controller configured to control one or more storage units. The multi-channel storage system may further include a multi-channel interface having a plurality of input-output (IO) channels; and a channel-controller switch configured to support data communications between any one of the plurality of IO channels and any one of the plurality of memory-controllers. Upon receiving a request instructing using at least two of the plurality of IO channels and at least two of the plurality of memory-controllers, the multi-channel interface of the multi-channel storage system is configured to utilize the channel-controller switch to concurrently transfer data via the at least two of the plurality of IO channels or the at least two of the plurality of memory-controllers.

Abstract: A multi-stage switch fabric (SF) is provided. The multi-stage SF includes a line card chassis (LCC) and a fabric card chassis (FCC). The FCC includes a stage-1 switch element (S1), a stage-2 switch element (S2), and a stage-3 switch element (S3), where the S3 corresponds to the S1, and the S2 is coupled to the S1 and S3 respectively. The LCC includes an interface component and a line card (LC) coupled to the interface component, where the interface component is coupled to the S1 and S3 in the FCC respectively. Through the technical solution under the present invention, when a switch element generates flow control information and requires another switch element or an LC to respond to the flow control information, a timely response can be received.

Abstract: Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme.

Abstract: Intelligent resource state memory recall techniques, and associated apparatus and methods, are disclosed. States of one or more video switcher resources in a resource state memory may be recalled to the same or different resources, depending on resource availability at the time of memory recall. A memory recall need not affect an on air signal. The memory may be recalled to recreate a desired program output, as defined in the memory, on a preview output of the video switcher, which leaves a current program output of the video switcher undisturbed when the memory is recalled.

Abstract: Distributively associated with each output row of point cells or each subset of point cells in each output row is one or more of a: memory device for storing an address identifying a cell in its associated output row and a decoder device responsive to the memory device for actuating the associated enable circuit to operate the transconductance device of the identified cell; a bias device, and an output cascode device; and also disclosed as switching systems having a bias device including a current mirror with an input reference portion responsive to a reference current and a co-located output local portion for reproducing that current as the bias current.

Abstract: A switch matrix module (600) includes programmable stub breakers (508-512, 514-518) which can break off the bus and isolate unused portion of the switch matrix. Using three-way stub breakers (508-512, 514-518) at the matrix front-ends that can either completely isolate a middle matrix or cut off stubs left or right of the destination and source matrices, allows for the formation of very large matrices which have improved operational performance.

Abstract: In a key scanning circuit, a key input unit has a parallel connection of a plurality of circuits having a series connection of resistors and switches between a power supply input terminal and a key scanning terminal. The resistors connected in parallel have different resistances. A current mirror has a first terminal connected to the key scanning terminal. A reference current source is connected between a second terminal of the current mirror and the power supply input terminal.

Abstract: A key system utilizes two operation nodes to detect the status of a plurality of keys, and each operation node can output and read a high, a low, and a clock signal. When an operation node outputs a high signal and reads a return signal and then outputs a low signal and reads a return signal, the other operation node outputs a clock signal. Therefore, the two operation nodes can detect the status of six keys.

Abstract: A data-communications switch having at least two modes of operation is provided. The data communications switch includes a first Clos switch having a first mode of operation and a second Clos switch, which is combined with the first Clos switch, for providing a second mode of operation. The first Clos switch and second Clos switch are interconnected in an overlapping manner to form a switch fabric, which is essentially a superset of both the first Clos switch and the second Clos switch and can be configured to operate in either mode depending on system requirements.

Abstract: The invention relates to a distribution device (1) in the subscriber access area, comprising two changeover devices (2, 3), two switching matrices (4, 5), a DSLAM (6) having associated splitter modules (7), and at least one controller (14), in which the first changeover device (2) comprises m inputs (8), m first outputs (9) and m second outputs (10), with a first and a second output (9, 10) having one associated changeover element (13) by means of which an associated input (8) can be selectively connected to the first or to the second output (9, 10), the second changeover device (3) comprises m first inputs (11), m second inputs (21) and m outputs (23), with a first input (11) and a second input (21) having one associated changeover element (22) by means of which an associated output (23) can be selectively connected to the first or to the second input (11, 21), the first switching matrix (4) has m inputs (12) and n outputs (15), and the second switching matrix (5) has n inputs (19) and m outputs (20), where

Abstract: Method and apparatus are provided for improved connection of devices and lower latency of communications between devices of a massively parallel network. In particular, method and apparatus are provided for cross-bar switches, a multiple protocol interface device, a low latency upper communication protocol layer, addressing and remote direct memory access over a massively parallel network.

Abstract: An apparatus (100), network and a method for switching-in and switching-off telecommunications or data services in a telecommunications or data network to a plurality of subscribers (102, 120, 122), the apparatus (100) comprising a first distribution matrix (104) connected to a crossover matrix (108) and a second distribution matrix (106) connected to said crossover matrix (108), wherein the crossover matrix (108) is adapted to be connected to a main cable (110) and to a distribution cable (112) and crossover switching elements for switching of connections within said crossover matrix (108) and distribution switching elements for switching of connections within said distribution matrices (104, 106) are controlled from a remote location, wherein the first distribution matrix (104) and the second distribution matrix (106) are adapted to be connected to a node for providing plurality of telecommunications or data services (114).

Abstract: A rearrangeably nonblocking multicast network includes an input stage having r1 switches and n1 inlet links for each of r1 switches, an output stage having r2 switches and n2 outlet links for each of r2 switches. The network also has a middle stage of m switches, and each middle switch has at least one link connected to each input switch for a total of at least r1 first internal links and at least one link connected to each output switch for a total of at least r2 second internal links, where m?n1+n2. The network has all multicast connections set up such that each multicast connection passes through at most two middle switches to be connected to the destination outlet links.

Abstract: Distributively associated with each output row of point cells or each subset of point cells in each output row is one or more of a: memory device for storing an address identifying a cell in its associated output row and a decoder device responsive to the memory device for actuating the associated enable circuit to operate the transconductance device of the identified cell; a bias device, and an output cascode device; and also disclosed as switching systems having a bias device including a current mirror with an input reference portion responsive to a reference current and a co-located output local portion for reproducing that current as the bias current.

Abstract: Software is employed to create an array of switch identifiers based on a known switching system architecture. A switch identifier array is preferably determined and stored in the system as part of the system manufacturing process prior to deployment of the system at an end user site. A relatively straight forward indexing operation may then be used to determine those sets of switches which are available to establish a desired interconnection, greatly simplifying selection of appropriate switches to create a desired path during real time operation of a deployed system.

Abstract: A plurality of inter-nodal control means are provided at a connection part between an inter-nodal crossbar switch for an inter-nodal data transfer and each node so as to process one inter-nodal transfer command, and an inter-nodal transfer capacity can be variably set in accordance with a capacity within a node. In this case, in the data transfer apparatus, at a connection part between an inter-nodal crossbar switch 11 for the inter-nodal data transfer and each node 12, 13, a plurality of inter-nodal control devices (RCUs) 123, 124; 133, 134 for processing one inter-nodal transfer command are provided.

Abstract: A cross connect switch has a plurality of stages. Each stage has a plurality of packers, a plurality of memory portions and a plurality of multiplexers. Each packer receives input data and provides the input data as a set of contiguous valid data. The multiplexers divide the valid data from one of the packers into a plurality of data subsets and route each data subset to a respective memory portion of that stage. Each stage except the final stage provides the data in the memory portions of that stage as a respective set of inputs to a next one of the stages. The final stage includes a plurality of multiplexers for selecting a respective subset of the data from each of the memory portions of the final stage and provides the selected data at a plurality of respective selected output ports.

Abstract: A crosspoint switch including a switch matrix modules and programming features. A switch matrix modules include input lines tied to inputs of the switch through precompensation networks. The programming features include user initialization states and reduced and grouping command configuration operations.

Abstract: Systems and methods for performing video switching between multiple inputs and outputs are disclosed. In one embodiment, a system includes a video box coupled to one or more user interfaces, a plurality of video inputs, and a plurality of video outputs. The video box includes a video controller coupled to the one or more user interfaces and a video switch coupled to the plurality of video inputs and the plurality of video outputs. Activation of the user interface generates a video control signal that is sent to the generated video control signal. The video controller generates a video switching signal based on the received video control signal. The video switch connects one or more of the plurality of video inputs to one or more of the plurality of video outputs based on the generated video control signal.

Abstract: A method of providing multiple test access for test equipment in a communication network is provided. The method comprises the step of coupling test apparatus to a first communication line via a first communication circuit in the test apparatus wherein the first communication line has a first quantity of equal bandwidth communication pathways that are dedicated for test access. The first communication line is coupled to a first cross connect apparatus. The test apparatus also has a second communication circuit that is coupled to the first communication circuit. The method further comprises the step of utilizing a second communication line having a second quantity of equal bandwidth communication pathways that are dedicated for test access. The second communication line is coupled between the first cross connect apparatus and a second cross connect apparatus. The second quantity is less than the first quantity.

Abstract: A processor is programmed to reduce a problem of adding a new connection to a time-space-time (TST) switch of a communication network into a problem of graph theory, and to solve the problem using a heuristic instead of an exact algorithm. A solution, if provided by the heuristic, is used to rearrange the connections in the TST switch. Several embodiments of such a programmed processor reduce a connection rearrangement problem of a TST switch into any one of the NP-complete problems (such as the vertex coloring problem or the boolean satisfiability (SAT) problem). In some such embodiments, the processor is programmed based on the Brélaz heuristic to find a solution to the vertex coloring problem. In other embodiments, other heuristics, such as a genetic algorithm, may be used.

Abstract: Aspects of a switch matrix circuit are provided. In accordance with a circuit aspect, a plurality of switches are organized in a row and column configuration. Coupled to the plurality of switches is a current sensing circuit. The current sensing circuit includes a transistor and at least one resistor per column of the plurality of switches. Current amplified by the transistor and converted by the at least one resistor in a column is sensed as a logic level indicative of a switch status within the column for a selected row. The current sensing arrangement may also be used in an embodiment utilizing bi-directional signal control to minimize the number of I/O lines required to scan the switch matrix. The bi-directional signal scanning may also be implemented in another embodiment that senses voltage levels to determine switch closures.

Abstract: The invention relates to a switching device comprising a plurality of inputs and outputs which are interconnected by a matrix of interconnection points for transmitting electric signals supplied from the inputs to the outputs via transmission lines in accordance with a predefined switching plan. The device comprises a control member for controlling the operation of the matrix with control signals and local decoding for locally decoding the control signals and for deducing the switching state of the interconnection points. Application: packet switching in optical transmissions.

Abstract: In a crosspoint switch, both input buses and output buses are driven at low swing. Self-timed, differential, push-pull, low swing driver circuits drive the input buses and are provided in the crosspoints to drive the output buses. Clocked, regenerative sense amplifiers are provided in crosspoints and at outputs of the data buses.

Abstract: A switching topology for communicating signals in an automatic test system includes a plurality of switching circuits each for selectively passing signals or crossing signals. Switching circuits are connected together such that each node of any switching circuit connects to no more than one node of any other switching circuit. This topology offers improved signal integrity, reduced cost, and reduced space as compared with conventional, matrix-style switching topologies.

Abstract: A crosspoint switch including a switch matrix modules and programming features. A switch matrix modules include input lines tied to inputs of the switch through precompensation networks. The programming features include user initialization states and reduced and grouping command configuration operations.

Abstract: An arbitration process sets the connections to be made between ingress and egress ports of a crossbar switch of a data switching system. A weight parameter is used for each pair of ingress and egress ports. Connection requests are generated indicating ingress ports to be connected to egress ports. A selection is made among conflicting connection requests, to produce a connection proposal for each egress port. Any connection request for which respective weighting parameter is zero is not selected. When one of the connection requests is realised, the weight parameter corresponding to this connection is decreased by one. All the weight parameters for a given egress port are re-set to default values in the case that there are no connection requests for that egress port with non-zero weights.

Abstract: One embodiment of the present invention provides a system that facilitates implementing a memory mechanism within an asynchronous switch fabric. The system includes a memory device, which does not preserve first-in, first-out semantics such as a random access memory or a stack. The system also includes a data destination horn, for routing data from a trunk line to a plurality of destinations. The memory device is one destination of the plurality of destinations. The system further includes a data source funnel, for routing data from a plurality of sources into the trunk line. The memory device is a source of the plurality of sources.

Abstract: A cross-bus switch apparatus which establishes simultaneously two or more pairs of connections between (i) a source bus arbitrarily selected from a plurality of source buses connected to one or more source apparatuses and (ii) a destination bus arbitrarily selected from a plurality of destination buses connected to one or more destination apparatuses. The cross-bus switch apparatus includes: a plurality of cross-bus switch units. The plurality of source buses are grouped into a plurality of source bus groups which are each connected to one of the plurality of cross-bus switch units. The plurality of destination buses are grouped into a plurality of destination bus groups which are each connected to one of the plurality of cross-bus switch units. Each cross-bus switch unit is connected to either (i) a source bus group or a destination bus group, or (ii) a source bus group and a destination bus group.

Abstract: A high-speed, low distortion N×M crosspoint switch selectively routes input signals arriving at any of N input terminals to one or more of M output terminals. The crosspoint switch includes a switch cell array having N rows and M columns of switch cells. Each of N input lines convey the input signal arriving at a separate one of the N input signals to each switch cell of a corresponding array row. Each of M output lines convey output signals generated by cells of a corresponding array column to a separate switch output terminal. Each switch cell contains a CMOS tristate buffer and a memory cell for storing data controlling whether the tristate buffer is active or inactive. When a tristate buffer is active, it buffers an input signal appearing on one of the input lines to generate an output signal on one of the output lines. When inactive, a tristate buffer refrains from generating an output signal in response to its input signal.

Abstract: This invention provides for a system and method for upgrading an ATM network to a new release of a vendor's ATM platform, or for converting an ATM network to a different vendor's ATM platform, preferably without experiencing any service disruptions. The system and method upgrade involves first reorganizing an existing redundant-based ATM network by splitting the links, for example, fiber links, within the existing redundant-based ATM network among two parallel networks, Network A and Network B. Network A can be changed at this stage. Then the circuits from Network B are moved to Network A by using Bridge and Roll techniques. This hitless procedure allows for the migration of the customer traffic from Network B to Network A without customer traffic disruptions.

Abstract: A crosspoint switch architecture implements high-speed packet switches and incorporates a power-saving bias control circuit with each switch cell. Each switch cell is equipped with two memory cells and a bias control circuit. Power savings are obtained by controlling the bias current of the switch cell as a function of the switch state. Although the additional circuitry accompanying each switch cell adds complexity and a minimal additional power consumption, the power saving realized in the switch cell results in a crosspoint switch with much lower power consumption as compared to existing architectures. The presence of two bits of memory for each switch core allows for fast reconfiguration. The result is an overall power savings and lower cost design.

Abstract: A novel folded Clos switch apparatus and method therefore for reducing the number of unemployed I/O terminals of a multistage Clos switching network by partitioning a crossbar switch to provide both the first (yth) and last (x−y+1th) stage of a multistage Clos switch where x is the total number of stages in the general case.

Abstract: An arrangement of a plurality of status keys in a keyboard for entering information in an electronic device. The keyboard comprises a plurality of regular keys connected to a resistive strip at a plurality of locations for providing a first signal when one of the regular keys is pressed and the first signal is indicative of the location associated with the pressed regular key; a plurality of resistors, each having a different resistance, connected in series to the resistive strip, and separately connected in parallel to the status keys so that the resistors can be selectively by-passed by pressing one or more status keys, wherein a second signal is provided when one of the regular keys is pressed together with at least one status key, and wherein the second signal is indicative of the resistance the status key for identifying the pressed status key.

Abstract: An apparatus is disclosed for effecting a communication arrangement of a plurality of communication circuits between first connection loci of a first switch array and second connection loci of a second switch array. The apparatus comprises: (a) a first connection interface with the first switch array having first interconnection loci; (b) a second connection interface with the second switch array having second interconnection loci; (c) a plurality of communication paths at least equal in number to the plurality of communication circuits intermediate the first and second connection interfaces; (d) a first router connected with the first switch array and connection interface; and (e) a second router connected with the second switch array and connection interface. The first and second router interfaces cooperate to effect a plurality of routing connections among the first connection loci, the second connection loci and selected communication paths to establish the communication arrangement.

Abstract: Aspects of a switch matrix circuit are provided. In accordance with a circuit aspect, a plurality of switches are organized in a row and column configuration. Coupled to the plurality of switches is a current sensing circuit. The current sensing circuit includes a transistor and at least one resistor per column of the plurality of switches. Current amplified by the transistor and converted by the at least one resistor in a column is sensed as a logic level indicative of a switch status within the column for a selected row. The current sensing arrangement may also be used in an embodiment utilizing bi-directional signal control to minimize the number of I/O lines required to scan the switch matrix. The bi-directional signal scanning may also be implemented in another embodiment that senses voltage levels to determine switch closures.

Abstract: A matrix switcher with three-dimensional orientation of printed circuit boards is disclosed. The matrix switcher of the present invention has a number of input printed circuit boards each comprising a matrix input and a number of output printed circuit 5 boards each comprising a matrix output. Plains of the input printed circuit boards are substantially parallel to each other. Plains of the output printed circuit boards are also substantially parallel to each other and at the same time substantially perpendicular to the plains of the input printed circuit boards. Switches are located on either the input printed circuit boards or the output printed circuit boards. A signal can be sent from any matrix input to any matrix output by way of placing the corresponding switches in an “on” position.

Abstract: Bussing high frequency crosspoint switches is achieved by extending an output transmission line bus through an integrated circuit (IC) upon which the crosspoint switch is laid. The internal portion of the output transmission line bus is coupled to an output pad on the IC via a bond wire. This eliminates stubs from the output of the IC to the output transmission line as well as compensating for parasitic capacitance associated with the output pad.

Abstract: A line multiplier is formed of n upstream lines and m downstream lines where m>n by providing a micro-technology array of m×n crosspoints switches using, e.g., magnetic latching, wherein the latching magnets are heated to the Curie temperature to cause the state of a switch to change.

Abstract: The present invention relates to a cross connect switch which allows different protocols to be used. The switch is made up of two cross point modules, one for transmission and one for reception. I/O blocks corresponding to each station or network interface are connected to the cross point modules. Each I/O block includes four differential pairs. The I/O block permits selective activation for transmission or reception of any of the four pairs. In addition, half duplex control logic is used to implement protocols using a single differential pair for both transmission and reception. Also a token ring interface is included on the I/O blocks in order to allow detection and generation of phantom DC currents necessary for operation with token rings.

Abstract: The present invention switches an input/output route for each signal, even if types of signals are increased, without installing additional switchers.

Abstract: Several rotator switch architectures are provided that enhance performance of a basic rotator switch. The rotator switches having double buffered tandem nodes, multiplexing two or more sources onto each tandem node, partitioning the rotator into two or more parallel space switches, two or more rotator planes multiplexing front/to source and destination nodes to provide data path redundancy, priority queueing on source nodes scheduled locally or globally, or redundancy in the schedulers are shown.