Abstract: A computing apparatus triggered by input signal edges from a power supply line includes an edge-triggered computing device, a charging device, and an initialization device. The edge-triggered computing device is triggered to compute by the input signal edges from power supply line, and is used to output computing results; the charging device is configured to supply power to the edge-triggered computing device based on the input signals from the power supply line; the initialization device is configured to initialize the edge-triggered computing device based on the voltage of the power supplied by the charging device. An LED driver includes the computing apparatus is to configured to control a driving device according to the computing results, thereby achieving display of light from LEDs using the power supply line and ground line without extra control signal line, and facilitating on-chip implementation of LED driving circuits.

Abstract: One or more first signals and one or more second signals, wherein the second signal(s) are slowly varying or low frequency signals in comparison with the first signals and are converted from analog to digital by sampling the first signals and the second signals to produce samples thereof for analog-to-digital conversion, subjecting the samples of the first signals to conversion to digital at a certain conversion rate, subjecting the samples of the second signal to conversion to digital by segments so that these segments are subjected to conversion to digital along with the samples of the first signals at the respective conversion rate, and reconstructing digital converted samples of the second signal from the segments subjected to conversion to digital.

Abstract: A fixed-size codeword table is generated for decompressing GIF encoded data. The fixed-size codeword table is defined to store a codeword string and a codeword length for each of a number of codewords. The codeword string is defined by a codeword previously represented in the codeword table and a character. The codeword length represents a total number of characters in the codeword string. A current codeword in the GIF encoded data is translated according to the codeword table to generate a series of characters represented by the current codeword. The generated series of characters is stored in a computer memory space.

Abstract: A printing press comprises transport means for transporting a printed sheet to a delivery unit, face-side and reverse-side UV devices for drying an ultraviolet curing ink printed on the sheet transported by the transport means, and a printing quality checking apparatus for checking the printed surfaces of the sheet transported by the transport means. Face-side and reverse-side checking cameras of the printing quality checking apparatus are provided at positions where the face-side and reverse-side checking cameras are not affected by heat and/or light from the face-side and reverse-side UV devices. The printing quality checking apparatus can reliably prevent improper operation and wrong detection of the face-side and reverse-side checking cameras without being adversely affected by heat or light from the face-side and reverse-side UV devices.

Abstract: In an inkjet printer, the print head does not print images directly to the print medium. Rather, the print head prints the image to an intermediate transfer member, for example a transfer belt or drum. The transfer member then transfers the image to the print medium to produce the desired hard copy document. By printing to an intermediate transfer member and then transferring the image to the print medium, additional time is provided for the carrier fluid of the ink to evaporate or be absorbed by the transfer member before the image is transferred to the print medium. In this way, less carrier fluid is eventually deposited to the print medium than if the image had been printed directly on the print medium. Consequently, cockle formation is decreased.

Abstract: A circuit (100) for performing base 10 logarithmic calculations of a binary signal in a digital system that optimizes accuracy of the calculation. The circuit comprises a priority encoder (108) for determining a most significant bit position of the binary number, with the most significant bit representing a base 2 logarithmic integer component of the input binary signal. A decimal selector (120) selects a predetermined number of bits to follow the base 2 logarithmic integer component determined by the priority encoder, with the predetermined number of bits representing a base 2 logarithmic fractional component following the integer component of the input binary signal. An adder (116) combines the integer component with the fractional component to thereby output a base 2 logarithmic value of the input binary signal. A multiplier (132) divides the base 2 logarithmic value of the input binary signal by a base 2 logarithmic value of 10 to thereby output a base 10 logarithmic value of the input binary signal.

Abstract: A system for and method of transmitting and storing data using multidecimal encoding. A binary data stream is encoded into a multidecimal data stream. Distinct frequencies are then assigned to characters in the multidecimal data stream for transmitting the multidecimal character information. Individual frequencies, or combinations of frequencies, may be assigned to each multidecimal character to be transmitted, through various methods. The various multidecimal transmission schemes described herein may be employed in any of several transmission systems, such as fiber optics networks, analog transmission systems, DSL systems, cable modem systems, wireless communication systems, or any other suitable data transmission systems. Multidecimal data may also be stored in various storage media, such as CD-ROMs, DVDs, or RAM.

Abstract: A system and method are provided for encoding from decimal to binary and back again. The coding is based on representing 3 decimal digits as 10 binary bits and is a development of the Chen-Ho algorithm. This provides a storage efficiency of >99%, yet still allows decimal arithmetic to be readily performed. The decimal input is typically first converted to binary coded decimal (4 bits per decimal digit), before compression to 10 bits. Adopting the encoding of the present invention, if the leading (most significant) decimal digit is zero, then the first three bits of the binary output are zero; and if the first two decimal digits are zero, then the first six bits of the binary output are zero. Accordingly, the same coding can be flexibly used to code a decimal digit is binary bits and 1 decimal digit is 4 binary bits. This makes it particularly suitable for standard computer architectures which are based on a power of two (16-bit, 32-bit, 64-bit, etc), and therefore not directly divisible by 7 or by 10.

Abstract: A system and method are provided for encoding from decimal to binary and back again. The coding is based on representing 3 decimal digits as 10 binary bits and is a development of the Chen-Ho algorithm. This provides a storage efficiency of >99%, yet still allows decimal arithmetic to be readily performed. The decimal input is typically first converted to binary coded decimal (4 bits per decimal digit), before compression to 10 bits. Adopting the encoding of the present invention, if the leading (most significant) decimal digit is zero, then the first three bits of the binary output are zero; and if the first two decimal digits are zero, then the first six bits of the binary output are zero. Accordingly, the same coding can be flexibly used to code 2 decimal digits to 7 binary bits, and 1 decimal digit to 4 binary bits. This makes it particularly suitable for standard computer architectures which are based on a power of two (16-bit, 32-bit, 64-bit, etc), and therefore not directly divisible by 7 or by 10.

Abstract: An improved system for converting a binary floating-point number to a decimal representation within a table-based computer is disclosed. In accordance with a preferred embodiment of the present invention, a computer system is provided which includes a first table and a second table. Both of the tables have several entry locations, and each of these entry locations contains a number. The computer system also has an extraction routine for extracting a first index into the first table from a binary floating-point number, an acquiring routine for obtaining a second index into the second table from the number contained within an entry location of the first table referenced by the first index, and an identifying routine for identifying a selected entry location of the second table.

Abstract: A decoder has first and second decoder circuits for producing dual sets of outputs. The first decoder circuit is responsive to input lines B.sub.1 -B.sub.n representative of a binary value x and has first outputs Z.sub.1 -Z.sub.m where m=2.sup.n. In response to the value x applied to the first decoder, output line Z.sub.x+1 is set high while the remainder are set low. The second decoder circuit comprises m transmission gates serially connected between a first and a second potential. The transmission gates are each directly driven by a respective one of said first outputs Z.sub.1 -Z.sub.m. The second decoder circuit generates second outputs Y.sub.1 -Y.sub.m-1 at junctions of the transmission gates. In response to the value x applied to the first decoder, x number of the outputs Y.sub.1 -Y.sub.m-1 are set high beginning with the least significant output Y.sub.1 and continuing consecutively up to the output Y.sub.x with the remainder being set low.

Abstract: A numeric encoding method and apparatus for neural networks, encodes numeric input data into a form applicable to an input of a neural network by partitioning a binary input into N-bit input segments, each of which is replaced with a code having M adjacent logic ones and 2.sup.N -1 logic zeros, the bit position of the least significant of the M logic ones corresponding to the binary value of the input segment it replaces. The codes are concatenated to form an encoded input. A decoding method decodes an output from the neural network into a binary form by partitioning the output into output segments having 2.sup.N +M-1 bits each, each of which is replaced with an N-bit binary segment being a bracketed weighted average of the significances of logic ones present in the output segment. The binary segments are concatenated to form a decoded output.

Abstract: Dedicated convert hardware is disclosed for performing bidirectional conversions of numbers between binary and another base b (illustratively decimal) for use in a data processing system. The dedicated convert hardware comprises a special purpose multiply-and-add unit and a convert register. The output of the multiply-and-add unit is coupled to the input of the convert register, and the output of the convert register is recycled to the inputs of the multiply-and-add unit. The multiply-and-add unit is hardwired to multiply the input by b and concurrently add the value at a separate digit input. Means are also provided for initializing the convert register with zero or with any desired number.