Abstract: A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.

Abstract: A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.

Abstract: Certain aspects of the present disclosure provide a probabilistic analog to digital converter (ADC). The probabilistic ADC may be configured to convert an analog input to a variable-length or variable-amplitude pulse, apply the pulse to a plurality of memory elements as a switching pulse, and determine a digital value based on a number of memory elements that store a value after the switching pulse is applied.

Abstract: An analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal is described.

Abstract: A stochastic signal generation circuit includes a signal output circuit and a signal processing circuit connected with the signal output circuit. The signal output circuit includes two matching semiconductor components, wherein the signal output circuit detects a slight mismatch between the two matching semiconductor components, converts the detected slight mismatch into a corresponding electric signal, amplifies the electric signal, and outputs an analog voltage signal. The signal processing circuit converts the analog voltage signal into a stochastic digital signal. Also, a method for generating a stochastic signal is provided. The present invention decreases the cost of the integrated circuit, and better ensures the information security of the electronic products.

Abstract: Random sequences are generated based on a stochastic generative model having multiple random variates. Inputs representative of the stochastic generative model are received. The inputs include a first random variate having a finite set of alphabets, a second random variate having a set of alphabets, and a third random variate having a finite set of alphabets. Outputs representative of the random sequences are generated based on the stochastic generative model. The outputs include a first random sequence that is a finite-length random sequence of alphabets randomly selected from the first random variate, a second random sequence having a set of alphabets selected from the second random variate, and a third random sequence having a set of alphabets randomly selected from the third random variate.

Abstract: A stochastic signal generation circuit includes a signal output circuit and a signal processing circuit connected with the signal output circuit. The signal output circuit includes two matching semiconductor components, wherein the signal output circuit detects a slight mismatch between the two matching semiconductor components, converts the detected slight mismatch into a corresponding electric signal, amplifies the electric signal, and outputs an analog voltage signal. The signal processing circuit converts the analog voltage signal into a stochastic digital signal. Also, a method for generating a stochastic signal is provided. The present invention decreases the cost of the integrated circuit, and better ensures the information security of the electronic products.

Abstract: Detection of a process state change includes, in each of a number of filters having differing time constants, generating an estimated average process state from observed samples of the process. A number of state change decisions are generated by comparing each of the number of estimated process states with a respective one of a number of threshold values. It is then decided that the process has changed state if any one or more of the state change decisions indicates that the process has changed state.

Abstract: Techniques and tools for escape mode code resizing are described. For example, a video decoder receives encoded information (e.g., runs, levels) for transform coefficients of blocks. For at least some of the encoded information, the decoder decodes in an escape mode for which codes have sizes signaled on a sub-frame basis (e.g., on a per-interlaced field basis in a video frame, or on a per-slice basis in a video frame). A video encoder performs corresponding encoding and signaling.

Abstract: Apparatus for building a stochastic model of a time sequential data sequence, the data sequence comprising symbols selected from a finite symbol set, the apparatus comprising: an input for receiving said data sequence, a tree builder for expressing said symbols as a series of counters within nodes, each node having a counter for each symbol, each node having a position within said tree, said position expressing a symbol sequence and each counter indicating a number of its corresponding symbol which follows a symbol sequence of its respective node, and a tree reducer for reducing said tree to an irreducible set of conditional probabilities of relationships between symbols in said input data sequence. The tree may then be used to carry out a comparison with a new data sequence to determine a statistical distance between the old and the new data sequence.

Abstract: In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.

Abstract: To achieve economy of a transmission path with good quality of transmission and low expenditure compared to previous codes such as 4PSK-64PSK, the invention provides higher-value pulse duration encoding, such that there is provided only an alternating current of a frequency and phase position, with code elements of different pulse durations which are encoded by a different number of periods or half-periods. The following duration pulse is marked by an amplitude change.

Abstract: The present invention relates to process for encoding and transmitting information wherein data, digitalized speech, image, or documents, optionally in colour, are encoded by multilevel combination code with multilevel code elements into a signal, in particular represented by period duration of said signal and/or by a different number of periods in connection with amplitude levels of said signal whereby an amplitude level is used as redundance or quasi level for an identification of code combinations. In the case of digital encoding of the information of a sequence of similar code elements, similar code words, similar lines with associated code words in the sequence are combined in such a way that the number of the sequences are provided in code.

Abstract: The method is founded on the GUAZZO algorithm and is adaptive as it does not require any prior statistical knowledge of source of message to be coded. The message is comprised of a sequence of symbols of the source which are represented by the indication of the direction "0" or "1" chosen at each node of a binary tree. According to the invention, the adaptiveness is obtained by associating with each node two finite-sized counters that count the "0"s and "1"s according to the routing of the tree. The contents of these counters enable the conditional probability of each of the elements "0" and "1" to be estimated at the node.

Abstract: A method for substituting interpolated values for ambiguous symbols in an arithmetically encoded symbol string, symbols in the unencoded original string being drawn from a Markov source and a finite alphabet. Ambiguity of a symbol is defined as where its symbol occurrence statistic lies outside of a predetermined range. Interpolation involves selectively combining the occurrence statistics of symbols adjacent the ambiguous symbol and recursively and arithmetically encoding the combined statistics. The method otherwise encodes unambiguous symbols in a conventional arithmetic manner. The decoding duals are also described.

Abstract: A circuit for randomizing data or de-randomzing previously randomized data according to a randomization scheme utilizing an irreducible generator polynomial which operates on a serial bit stream of words of data which is supplied to said circuit in a format, either LSB or MSB first, different from the format according to which the data was previously randomized or will be subsequently de-randomized. The circuit includes means for generating said irreducible generator polynomial; means for triggering said generating means in a given direction in response to a clock signal; means for exclusively ORing the contents of a bit in said generating means with a bit in said bit stream; and means for periodically interrupting said triggering means and instead setting the state of said generating means a predetermined number of states in a direction effectively the opposite to which said generating means normally generates data.