Abstract: The application discloses a time-to-digital conversion circuit (100) including a first oscillator (110), a second oscillator (120), a first counting circuit (130), a second counting circuit (140), a first conversion circuit (150) and a processing circuit (160). The first oscillator is activated by a first signal and includes oscillating units having a first delay amount, wherein the first counting circuit is configured to count a number of times that the first tail end output signal of the first oscillator changes and store the same as a first counting result; the second counting circuit counts a number of oscillating units with an output change, other than the first tail end oscillating unit and stores the same as a second counting result; the first conversion circuit generates a first conversion signal according to the first counting result and the second counting result; the processing circuit generates the output signal at least according to the first conversion signal.

Abstract: A method of regulating the operation of an electrical system, the electrical system including, a contactor unit including a contactor and a conductive element, sensing circuitry including at least two Hall Effect sensors, and a control unit including at least a trip circuit, an I2t unit, and a one coil current monitor. The method includes receiving, by the control unit, one or more first measurements, from the sensing circuitry and determining, by the control unit, a current corresponding to a current in the at least one conductive element based on the one or more first measurements. The control unit also determines an instantaneous power generated by a load based on the current and regulates the operation of the contactor unit based on the power generated by the load.

Abstract: The present invention discloses an image sensor circuit and a ramp signal generator thereof. The image sensor circuit includes: an active pixel sensor (APS) array which includes plural pixel circuits arranged in an array of columns and rows; plural slope analog-to-digital converter (ADC), wherein each of the slope ADC is coupled to the corresponding column, and generates a digital sampling signal according to a ramp signal together with a pixel signal including a reset signal and a image signal which are generated by the pixel circuit located in the selected row and in the column corresponding to the slope ADC; and the ramp signal generator, which generates the ramp signal, wherein the ramp signal generator includes an active integrator, and the active integrator generates the ramp signal by charging an integration capacitor with a gain current.

Abstract: An output module includes multiple outputs, each output having switches, wherein the switches are configured such that a load is connectable between the switches, and a calibration unit configured to disconnect the load from the switches for a calibration period, monitor a behavior of the load while disconnected, and store samples of the behavior of the load. Further aspects of the present disclosure relate to a control system and a method for testing an output module connected to a complex load.

Abstract: Intelligent load balancing is conducted by monitoring loads in phases at nodes and commanding phase switches of a plurality of nodes to rotate phases. Preferred embodiments identify load balancing problems among phases in three-phase systems and utilize a modified legacy network of power meters or an existing smart network of power meters to implement a control algorithm that achieves dynamic, intelligent load balancing.

Abstract: The invention relates to a system comprising a probe and a measuring device, wherein the probe is connected to an input of the measuring device, and wherein an analog-digital converter is connected downstream of the input of the measuring device. The probe provides an analog-digital converter for the generation of a value-discrete and/or time-discrete signal from an analog input signal, wherein the value-discrete and/or time-discrete signal is supplied to the analog-digital converter of the measuring device. The invention further relates to a method for the registration of an analog signal by means of a system comprising a probe and a measuring device.

Abstract: [Problem] To shorten the measurement time, while maintaining the measurement precision, for a data converter of delta-sigma system. [Solution] A measurement method of the present embodiment is a measurement method for a delta-sigma type of data converter that performs a data conversion between an analog signal and a digital signal.

Abstract: Provided is an image sensor including a pixel array including a plurality of pixels and an analog-to-digital converter (ADC) configured to compare a reference voltage with an analog voltage output by the pixel array and latch and decode a comparison result. The ADC is controlled in response to clock information and a counter clock, which are obtained by expanding and encoding a master clock.

Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Abstract: Correcting phase error in a two-channel TIADC system in a manner that is independent of the Nyquist zone(s) occupied by the input signal. In the preferred approach this is done using the gradient of a phase error estimate. The gradient may be determined from a simplified expression of linear regression; the direction of the adaptation is then controlled by the sign of the gradient. The adaptive algorithm converges to the optimal value regardless of the Nyquist zone occupied by the input signal.

Abstract: Embodiments of the present invention provide systems, devices and methods for modeling and correcting amplitude and quadrature phase errors generated within analog components of a receiver. A frequency-dependent correction method is employed that closely tracks the frequency dependent nature of the mismatch between the I and Q polyphase filter responses. In particular, digital correction is performed on a signal based on a modeled error function generated during a calibration of the receiver.

Abstract: An analog-to-digital converter in an image sensor is implemented with a plurality of comparator units. Each comparator unit has a respective capacitor array and respective switches integrated therein. Such capacitors and switches across the comparator units are operated for generating ramp voltages for such comparator units for performing analog-to-digital conversion with correlated double sampling. Thus, circuit area and power consumption of the CMOS image sensor may be minimized.

Abstract: A microcontroller has an integrating analog-to-digital converter (IADC) with an in-situ autocalibrating functionality. On-chip autocalibrating circuitry supplies a first predetermined analog input voltage to the IADC and obtains a first data value from the IADC. The autocalibrating circuitry supplies a second predetermined analog input voltage to the IADC and obtains a second data value. The first and second data values are used to calibrate the IADC such that if the first input voltage is later supplied to the IADC, then the IADC will output a first predetermined desired digital output value and such that if the second input voltage is later supplied to the IADC, then the IADC will output a second predetermined desired digital output value. The first and second analog input voltages are generated on-chip so the calibration is performed automatically without having to supply external calibrating signals to the microcontroller. Other related methods and circuitry is disclosed.

Abstract: A measuring device is disclosed for capacitive pressure and/or temperature measurement, particularly for tire pressure control systems, having at least one sensor, which has a capacitive measuring element to detect a state value, which is applied at an output-side measuring node of the measuring element, with at least one A/D converter operating according to the dual-slope method, with a charging/discharging circuit, for mutual charging and discharging of the measuring element and for generating a sawtooth-shaped measuring potential at the measuring node as a measure for the capacitance of the measuring element, with a period counter, which determines the periods of the measuring potential, and with a clock counter, which determines the cycles of a clock signal, which lie within the duration of at least one period of the measuring potential. The invention relates to a measuring method for capacitive pressure and/or temperature measurement.

Abstract: A microcontroller has an integrating analog-to-digital converter (IADC) with an in-situ autocalibrating functionality. On-chip autocalibrating circuitry supplies a first predetermined analog input voltage to the IADC and obtains a first data value from the IADC. The autocalibrating circuitry supplies a second predetermined analog input voltage to the IADC and obtains a second data value. The first and second data values are used to calibrate the IADC such that if the first input voltage is later supplied to the IADC, then the IADC will output a first predetermined desired digital output value and such that if the second input voltage is later supplied to the IADC, then the IADC will output a second predetermined desired digital output value. The first and second analog input voltages are generated on-chip so the calibration is performed automatically without having to supply external calibrating signals to the microcontroller. Other related methods and circuitry is disclosed.

Abstract: An image sensor comprises an active pixel sensor (APS) array, a first analog-to-digital converter (ADC), and a ramp signal generator. The APS array has includes a plurality of pixels of arranged in a second order two-dimensional matrix, and wherein the APS array generates a reset signal and an image signal for each pixel of selected columns. The first ADC has includes correlated double sampling (CDS) circuits for each column of the APS array, and wherein the first ADC generates a digital code corresponding to the difference between the reset signal and the image signal using an output ramp signal that is applied to the CDS circuits for each column. The ramp generator generates the output ramp signal in which a low illumination portion and a high illumination portion have different slopes.

Abstract: An analog-to-digital converting apparatus for rapidly processing a plurality of analog input signals at a high rate and a display device using the same. The apparatus includes a clock signal generator that generates a clock signal with a predetermined frequency; a control signal generator that generates a switching control signal using the clock signal; a multiplexer (MUX) that receives and selectively outputs signals of the plurality of analog input signals according to the switching control signal; and an analog-to-digital converter (ADC) that converts an analog signal selected and output by the MUX to a digital signal.

Abstract: A dual path analog-to-digital conversion method and system. The system includes a first and second circuits. The first and second circuits each convert an input analog signal into digital signals at differing sample rates. The circuit having the slower sampling rate aliases frequency components of the input analog signal that are higher than half that sampling rate. Frequency components causing the aliasing in the slower sampling circuit are replicated from the faster sampling circuit at the appropriate amplitude, folded into the aliased frequency, and subtracted from the output of the slower sampling circuit. The outputs of both sampling circuits are then merged. These techniques extend the bandwidth of the slower conversion system without degrading the low-frequency accuracy of the slower conversion system.

Abstract: A rail to rail dual slope analog to digital converter (ADC) is provided in the present invention. The circuit scheme has an input stage, an integrator stage, and a comparator stage, where an operational amplifier (OPAMP) can be comprised of each stage respectively. The positive input of the integrator OPAMP coupling to an analog ground, and switching the negative feedback loop of the input stage between an input voltage, a reference voltage, and a short circuit, controlling a plurality of switches among circuit connections results in different phases of the dual slope ADC. A finer resolution is thus obtained according to rail to rail input voltage range. Also, the integrator OPAMP can be eliminated from the circuit of the present invention in order to reduce pins, with connecting an end of the external integrator capacitor to ground.

Abstract: A dual path analog-to-digital conversion method and system. The system includes a first and second circuits. The first and second circuits each convert an input analog signal into digital signals at differing sample rates. The circuit having the slower sampling rate aliases frequency components of the input analog signal that are higher than half that sampling rate. Frequency components causing the aliasing in the slower sampling circuit are replicated from the faster sampling circuit at the appropriate amplitude, folded into the aliased frequency, and subtracted from the output of the slower sampling circuit. The outputs of both sampling circuits are then merged. These techniques extend the bandwidth of the slower conversion system without degrading the low-frequency accuracy of the slower conversion system.

Abstract: A controlled drive circuit for an analog controlled power semiconductor includes a digitally operating logic module, which has a control input receiving control signals from an A/D converter and a control output supplying processed control signals to a D/A module that converts the processed digital control signals signal to an analog or quasi-analog control variable that controls the power semiconductor.

Abstract: A dual-slope analog-to-digital converter and a comparison circuit for the dual-slope analog-to-digital converter. The dual-slope analog-to-digital converter includes a buffer, an integrator coupled to the buffer and the comparison circuit. The comparison circuit includes a differential output comparator and a comparison unit. The differential output comparator is coupled to the integrator and produces a pair of differential signals to output. The comparison unit receives the differential signals and chooses a signal, whose voltage is from a first level to a second level, from the differential signals to produce an output signal.

Abstract: A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb2. The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb2. The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb2. enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb2.

Abstract: An analogue to digital converter generating at least two threshold levels and a comparator for comparing each of the levels with the input signal and generating a primary digital output signal to provide an indication that the input signal has crossed one of the threshold levels. The converter comprises a timer for determining the elapsed period of time between the input signal crossing a first level and the input signal crossing a second level and for generating a secondary output signal representing the elapsed time, whereby the secondary digital output signal and the corresponding primary output signal are used to provide a digital representation of the analogue input signal. The converter may also comprise a receiver of the primary digital output signal from the comparator and for providing an UP/DOWN digital output signal to indicate in which direction the input signal crossed the threshold level.

Abstract: It is object to provide a digital-to-analog converter capable of generating an output waveform having less distortion without increasing the operating speed of components. A D/A converter comprises a multiplying section 1, four data holding sections 2-1 through 2-4, four data selectors 3-1 through 3-4, an adding section 4, a D/A converter 5, and two integrating circuits 6-1 and 6-2. Input data is multiplied by four multiplicators by the multiplying section 1, and the four multiplication results are held, as one set, in the data holding sections. The data selectors read out the data held in the four data holding sections in a predetermined order and generate step function data. The adding section adds the values of the step functions outputted from the four data selectors. Furthermore, a stepwise analog voltage corresponding to the sum is generated by the D/A converter 5 and integrated twice by means of the two integrating circuits 6-1 and 6-2.

Abstract: A multislope, continuously integrating analog-to-digital converter includes a first switch coupled to a first reference voltage, a second switch coupled to a second reference voltage, a third switch coupled to an input voltage, and an integrator operably coupled to the first, second, and third switches. The analog-to-digital converter utilizes a primary discharge current of opposite polarity to a secondary discharge current. The analog-to-digital converter has a high resolution due to a small reference voltage, and a high dynamic range due to a large reference voltage. The analog-to-digital converter can operate in either a conversion mode or a calibration mode. During the calibration mode, a calibration factor is calculated for use during the conversion mode. When applied to the conversion mode, the calibration factor corrects for errors in the conversion process.

Abstract: An analog/digital converter including an amplifier (1) wired as an integrator, a comparator (2) electrically downstream from the integrator, a time counter (6) which continually counts the pulses of a pulse generator (5), a bistable element (4), and additional circuitry. The bistable element (4) drives the input network of the amplifier (1) with at least one switch (3) in such a way that in one of its two positions (“off” condition) a current Ix proportional to the analog measured value is integrated, and in the other position (“on” condition) a constant reference current Iref with opposite polarity to the current Ix is integrated in addition to current Ix.

Abstract: A process for the analog/digital conversion of an electric signal as well as a device for implementing the process is described. The process according to the invention provides that the time (T.sub.H, T.sub.L) be determined, which, starting from a voltage (U.sub.X) to be converted is necessary to charge up a RC component (10, 12) to a predetermined reference voltage, for example a switching threshold (S.sub.H, S.sub.L) of a comparator (14) or to discharge it. The device according to the invention provides that a selector switch (13), the comparator (14) as well as a time detector (15) are components of a microprocessor (17), which is wired with the RC component (10, 12) as well as with an input resistor (11) if necessary. The process according to the invention as well as the device according to the invention are particularly easy to realize and are suitable for use especially with a microprocessor (17) which does not have an integrated analog/digital converter.

Abstract: In a measurement device, a detector output signal indicative of a condition magnitude, e.g., radiation, pressure, temperature, etc, and a ramp signal are added, and the resulting analog summation signal is converted to a digital signal. The digital signal is sampled, integrated, and averaged over a sampling time corresponding to a predetermined sampling number, such as to achieve a condition measurement signal having reduced analog-digital conversion error.

Abstract: A motor starter includes separable contacts interconnected between an alternating current (AC) power source and an AC motor for switching an AC load current which flows from the power source and through the separable contacts; a dual-slope analog-to-digital (A/D) conversion circuit for sensing the load current and generating a current value; and a microcomputer with a coil drive circuit for selectively opening the separable contacts as a predetermined function of the current value. The dual-slope A/D conversion circuit includes current transformers for sensing the AC load current and for selectively providing a received current therefrom, a current reference for selectively providing a reference current, a multiplexer for multiplexing the currents, and a class B preamplifier for amplifying and rectifying the multiplexed AC current.

Abstract: A measuring probe measures a parameter with a sensor. The sensor provides a sensor output signal related to a measured value. An amplifier section receives the sensor output signal and provides an amplifier output signal. An integrator has an input and an integrator output related to an integration of the input. Switching circuitry receives the amplifier output signal and a reference signal and has an output connected to the input of the integrator. Controller circuitry coupled to the switching circuitry connects the amplifier output to the integrator input during a sampling time, and the reference signal to the integrator input during a conversion time. The conversion time is related to the sensor output signal and is measured to obtain a digital representation of the sensor output.

Abstract: An analog-to-digital converter converts multiple analog signals to multiple digital signals during a single conversion period. The converter comprises a multiple input integrator stage which provides an output voltage that is selectively compared to a multiplicity of voltages. The comparison voltages include reference voltages and additional signal inputs. A plurality of UP counters measure the number of clock pulses generated by a clock generator and enable the calculation of the output function.

Abstract: An analog-to-digital converter (ADC) includes a capacitor array coupled to switches, an integrator stage connected to the switchable capacitors and a comparator stage connected to the output of the integrator stage. Means coupled to the comparator stage include a feedback loop to effectuate switching reference signals of opposite polarity for use during respective phases of operation of the ADC. The values of the capacitors can be programmed by the user of the ADC and switched to provide a desired total capacitance. For any fixed ratio of the input voltage to reference voltage, the duty cycle remains constant over a wide range of temperatures. Multiple stages afford large effective capacitor ratios with a small range of actual capacitance values and enable a reduction in silicon chip area for an ADC integrated circuit.

Abstract: An improved integrating type A/D converter has a set of analog switches and a control logic unit for selectively connecting a pair of input terminals for an unknown analog input voltage signal with a pair of input leads across a buffer and integrator in order to apply, first in an integrate phase, the analog input signal in a polarity direction that causes the integrator to ramp up in the same direction regardless of the polarity of the analog input signal, and then in a deintegrate phase, reference voltages are applied across the input leads in a fixed direction opposite to the applied input voltage such that a zero crossing signal is output by the comparator. The ramping-up and ramping-down of the integrator in the same direction eliminates rollover error in the A/D reading of inputs of different polarities but of the same magnitude. The invention is particularly useful for monolithic A/D converters using BiMOS technology.

Abstract: A multichannel ADC is fabricated on a single IC with each analog channel for concurrently processing input analogue signal in a pipelined manner and including a dual purpose intermediate amplifier for amplifying an input voltage to be converted and providing a reference voltage for use during conversion. A unique capacitor array reduces the area required to implement the convertors.

Abstract: The present invention provides an analog to digital converter, including an integrator for producing an output signal and having an input, a connection for an input signal to the integrator input, and a controller for periodically applying a reference signal to the integrator input for causing the integrator output signal to have a predetermined average value, for measuring the amount of time that the reference is applied to the integrator input, and for calculating a digital representation of the analog signal.

Abstract: Apparatus for control of the range of input voltage values to be measured and for compensation of the changes in the supply voltage of an analog to digital dual slope converter circuit is described. The selection of a range for input voltage measurements in the analog to digital converter circuit permits the conversion to take place over a relatively long time period, thereby increasing the resolution of the resulting conversion. Changes in the supply voltage are combined with the input analog signal (during the capacitance charging period) and with the reference voltage (during the capacitance discharge cycle) providing compensation for the effects of time, temperature and the tolerance of the supply voltage.

Abstract: An analog-to-digital converter suitable for digitalizing signals used in an automatic track finding mechanism of a digital audio tape-recorder. The A/D converter comprises a sampling clock generation circuit for generating a sample clock in synchronism with an input signal and an analog-to-digital conversion circuit for analog-to-digital converting an amplitude peak value of the input signal at a timing of the sampling clock. The A/D converter is samplified in structure, for the sampling clock for sample holding does not have to be quartz oscillated but only needs to be a signal synchronous to the input signals.

Abstract: An analogue to digital multi-slope converter has an integrator 10 to which an analogue input signal 30 is continuously applied. A reference voltage 36, 37 is superimposed onto the integrator input 30 in pulse form, being switched on and off according to a predetermined program controlled by a clock and modified by a comparator 11 such that reference voltage pulses occur in pairs of opposite polarity. The sequence of pulses is applied in such a manner that the final pulse of a sequence causes the integrator output to move towards a comparator 11 reference level, the reference voltage then being maintained until the reference level is reached after which a new cycle is started.

Abstract: An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The A-to-D and D-to-A conversion rates are selected by the system control, responsive to data received from the signal processor.

Abstract: A single chip monolithic integrated successive approximation analog-to-digital converter includes a test mode terminal for receiving shift register test mode control signals and successive approximation mode control signals. Digital test data signals are applied to a test data terminal. A trimmable digital-to-analog converter (DAC) is connected to receive digital signals and converts these signals to analog signals of corresponding values. A successive approximation and shift register is coupled to the test mode terminal and the test data terminal. During post-fabrication processing, the successive approximation and shift register operates in a shift register test mode in response to the test mode control signals. Test signals of a known value are serially received and applied in parallel to the DAC. The DAC can then be trimmed to required specifications. The successive approximation and shift register operates in a successive approximation mode in response to successive approximation mode control signals.

Abstract: An analog-to-digital converter is provided based on supplying various multiplexed inputs, including analog input signal samples, to a voltage-to-current converter charging and discharging an integrated capacitor. A comparator determines the status of this capacitor to a control counter to provide digital representations.

Abstract: A clock-controlled voltage-to-frequency converter comprising a reference voltage source, an integrator for receiving the reference voltage and a variable input voltage and producing an output having a triangular waveform, the integrator including a capacitor which is charged at a rate proportional to the input voltage and discharged at a rate proportional to the difference between the reference voltage and the input voltage, the charging and discharging occurring during a time interval T.sub.

Abstract: An adaptive single-bit encoder and decoder has its adaptive function determined by dynamically dividing the message frequency band into delta-sigma and delta modulation regimes of operation. IN a practical embodiment this is accomplished by varying the corner frequency of a variable-frequency low-pass filter in a leaky integrator so that below the corner frequency the operation is that of delta-sigma modulation and above the corner frequency the operation is that of delta modulation. An adaptation control circuit removes the clock signal component from the encoded bit stream to provide an analog signal representative of bit stream information or loading for use in generating the control signal. The analog signal is peak rectified, smoothed, and (optionally) non-linearly processed to provide the control signal.