Abstract: A circuit for analog-digital conversion, which includes a first connection and a second connection and a third connection and a fourth connection for connecting a sensor, an analog-digital converter (ADC), whose first input is connected to the first connection and whose second input is connected to the second connection, a first current source circuit for outputting a first output current, a first switching device for the switchable connection of the first current source circuit to the first connection or to the third connection, a current source/sink circuit for outputting a second output current, a second switching device for the switchable connection of the current source/sink circuit to a reference potential or to the second connection, and a third switching device for the switchable connection of the reference potential to the second connection or to the fourth connection.

Abstract: A tracking ADC with adaptive slew rate boosting can dynamically adjust one or more of its operational parameters in response to detecting a slew rate limit condition. In some embodiments, slew rate boosting can include increasing the value of a digital error signal in response to detection of a slew rate limit condition. In other embodiments, slew rate boosting can include increasing a clock frequency of the tracking ADC in response to detection of a slew rate limit condition.

Abstract: A device includes a resistor string that includes a plurality resistors with voltage taps disposed therebetween. The device may select one particular voltage tap of the plurality of voltage taps based on received gray level data for a pixel of a display. The device also includes a first amplifier that may be coupled to a first terminal end of the resistor string. The device additionally includes a second amplifier that may be coupled to a second terminal end of the resistor string, wherein the plurality of voltage taps may each supply a tap voltage derived from a voltage between the first amplifier and the second amplifier, wherein any tap amplifier of the device coupled to a voltage tap of the plurality of voltage taps provides a reference voltage thereto.

Abstract: To suppress detection accuracy of a measurement resistance from decreasing by an on-resistance of a selector switch. The selector switch is provided between a first node coupled to a first voltage through a reference resistance and multiple second nodes coupled to the second voltage through measurement resistances, and selects the second node to be coupled to the first node with the selector switch. A correction circuit generates a voltage obtained by adding the second voltage to a voltage between the second node and the first node as a correction voltage. A double integral ADC finds a first integral time elapsed when a difference voltage of the correction voltage to a voltage of the first node is integrated to the first voltage and a second integral time elapsed when the difference voltage of the first voltage to the voltage of the first node is integrated to the correction voltage.

Abstract: An analog to digital converter (ADC) circuit includes an input stage for supplying an input signal to an ADC for conversion to a digital signal and a control unit of the ADC. The ADC circuit further includes an operational parameter setting device configured to receive an operational parameter setting signal indicative of an operating parameter for the input stage from the control unit. The operational parameter setting device is configured to set an operating parameter for the input stage based on the operational parameter setting signal.

Abstract: A method and apparatus for detecting the presence of a signal in a frequency band using non-uniform sampling includes an analog to digital converter (ADC) (110) for sampling an analog input signal (105) to create discrete signal samples (115), an ADC exciter (120) for exciting the ADC to sample at non-uniform time periods, a digital filter (130) for converting the discrete signal samples into an energy versus frequency spectrum (300), and an energy comparator (140) coupled to an output of the digital filter. The energy comparator (140) detects the presence of any frequency bands exceeding an energy setpoint.

Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Abstract: An analog to digital converter with increased sub-range resolution. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a full-range ADC having a first quantization accuracy configured to sample the analog communication signal across the full-range and a central sub-range ADC having a second quantization accuracy greater than the first quantization accuracy and configured to sample the analog communication signal across a central sub-range of the full-range. The ADC also includes signal combining circuitry configured to process outputs of the full-range ADC and the central sub-range ADC to create the digital communication signal.

Abstract: The present invention relates to the field of mobile terminal technology and describes a calibration device for a mobile terminal and an ADC module thereof, the ADC module being disposed inside a baseband chip. The calibration device includes a bandgap voltage reference inside the mobile terminal platform for generating a reference voltage; the device further includes a circuit for connecting the bandgap voltage reference, the circuit being connected with the ADC module for providing the reference voltage generated by the bandgap voltage reference to the ADC module. The present invention uses a bandgap voltage reference inside a mobile terminal platform to provide voltage to an ADC module, which, during the ADC module calibration, does not require an external reference voltage source to perform the ADC calibration, and therefore greatly reduces calibration errors and improves calibration efficiency.

Abstract: An analog to digital converter with increased sub-range resolution and method for using the analog to digital converter is described herein. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a plurality of sub-range ADCs, each sub-range ADC measuring the analog communication signal across at least one respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having greater quantization accuracy than at least one other sub-range ADC. The ADC also includes signal combining circuitry operable to process outputs of the plurality of sub-range ADCs to create the digital communication signal.

Abstract: For analog to digital conversion with correlated double sampling in an image sensor, a pixel signal from a given pixel is sampled to generate a respective sampled signal N-times, with N>1 within a horizontal scan time period. A ramp signal is generated with a respective ramping portion for each respective sampled signal. Each respective sampled signal is compared with a respective ramping portion to generate a respective comparison signal that determines a respective digital code. The N respective digital codes are summed to generate a final digital code with reduced random noise.

Abstract: An analog-to-digital converter in an image sensor is implemented with a plurality of comparator units. Each comparator unit has a respective capacitor array and respective switches integrated therein. Such capacitors and switches across the comparator units are operated for generating ramp voltages for such comparator units for performing analog-to-digital conversion with correlated double sampling. Thus, circuit area and power consumption of the CMOS image sensor may be minimized.

Abstract: A microcontroller has an integrating analog-to-digital converter (IADC) with an in-situ autocalibrating functionality. On-chip autocalibrating circuitry supplies a first predetermined analog input voltage to the IADC and obtains a first data value from the IADC. The autocalibrating circuitry supplies a second predetermined analog input voltage to the IADC and obtains a second data value. The first and second data values are used to calibrate the IADC such that if the first input voltage is later supplied to the IADC, then the IADC will output a first predetermined desired digital output value and such that if the second input voltage is later supplied to the IADC, then the IADC will output a second predetermined desired digital output value. The first and second analog input voltages are generated on-chip so the calibration is performed automatically without having to supply external calibrating signals to the microcontroller. Other related methods and circuitry is disclosed.

Abstract: A first control circuit portion carries out input/output control in cooperation with a microprocessor, a program memory, and a RAM memory. A second control circuit portion is in cooperation with the communication control circuit portion and the data memory to carry out serial communication with the first control circuit portion. A switch signal input to the second control circuit portion is stored in a first report packet, a digital conversion value for an analog signal input is stored in a second report packet, and the first and second packets are alternately periodically transmitted to the first control circuit portion. A multi-channel AD converter included in an analog signal input circuit starts to carry out AD conversion a prescribed time period after a first report packet is transmitted and finishes conversion before a second report packet is transmitted, so that up-to-date AD conversion data is transmitted.

Abstract: A microcontroller has an integrating analog-to-digital converter (IADC) with an in-situ autocalibrating functionality. On-chip autocalibrating circuitry supplies a first predetermined analog input voltage to the IADC and obtains a first data value from the IADC. The autocalibrating circuitry supplies a second predetermined analog input voltage to the IADC and obtains a second data value. The first and second data values are used to calibrate the IADC such that if the first input voltage is later supplied to the IADC, then the IADC will output a first predetermined desired digital output value and such that if the second input voltage is later supplied to the IADC, then the IADC will output a second predetermined desired digital output value. The first and second analog input voltages are generated on-chip so the calibration is performed automatically without having to supply external calibrating signals to the microcontroller. Other related methods and circuitry is disclosed.

Abstract: An image sensor comprises an active pixel sensor (APS) array, a first analog-to-digital converter (ADC), and a ramp signal generator. The APS array has includes a plurality of pixels of arranged in a second order two-dimensional matrix, and wherein the APS array generates a reset signal and an image signal for each pixel of selected columns. The first ADC has includes correlated double sampling (CDS) circuits for each column of the APS array, and wherein the first ADC generates a digital code corresponding to the difference between the reset signal and the image signal using an output ramp signal that is applied to the CDS circuits for each column. The ramp generator generates the output ramp signal in which a low illumination portion and a high illumination portion have different slopes.

Abstract: Time variant interleaving equalization of an interleaved analog to digital converter is disclosed. A high-frequency analog input signal is converted into a plurality of individual digital signals using a plurality of interleaved analog-to-digital converters. the plurality of individual digital signals are interleaved into a composite digital signal. The composite digital signal is processed in a time variant interleaving equalizer using a plurality of sets of equalizer coefficients.

Abstract: A multi-cycle, multi-slope analog to digital converter overlaps charge and discharge periods to reduce latency to the end of the measurement following a sampling window. Additionally, charging and discharging of an integration capacitor during the measurement cycle occurs between defined thresholds so as to avoid saturation within the analog to digital converter.

Abstract: An analog-to-digital conversion device is provided that uses pulse delay circuits to convert an input voltage into numerical data and offers a high resolution in analog-to-digital conversion or a high analog-to-digital conversion rate. The analog-to-digital conversion device includes an analog-to-digital conversion unit having a pulse delay circuit composed of a plurality of delay units. The delay units are driven with a voltage produced by amplifying or shifting an input voltage. The number of delay units through which a pulse signal has passed during a predetermined sampling cycle is adopted as a digitized value of the input voltage. Herein, delay units constituting another pulse delay circuit are driven with a voltage produced by inversely amplifying or shifting the input voltage.

Abstract: A device for generating synchronous numeric signals, including a reference generating device supplying a reference signal and a first timing signal, both having a reference frequency; and a timed generating device supplying a synchronized signal having the reference frequency. The device further includes a synchronization stage generating a second timing signal having a first controlled frequency correlated to the reference frequency, and phase synchronization pulses having the first frequency and a preset delay programmable with respect to the first timing signal.

Abstract: A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb2. The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb2. The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb2. enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb2.

Abstract: A method that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has a greater resolution than the course ADC. A decoder that correlates a course analog to digital converter (ADC) output value against a folded fine ADC transfer curve slope value to determine an ADC circuit region. The folded fine ADC has greater resolution than the course ADC.

Abstract: An analogue to digital converter generating at least two threshold levels and a comparator for comparing each of the levels with the input signal and generating a primary digital output signal to provide an indication that the input signal has crossed one of the threshold levels. The converter comprises a timer for determining the elapsed period of time between the input signal crossing a first level and the input signal crossing a second level and for generating a secondary output signal representing the elapsed time, whereby the secondary digital output signal and the corresponding primary output signal are used to provide a digital representation of the analogue input signal. The converter may also comprise a receiver of the primary digital output signal from the comparator and for providing an UP/DOWN digital output signal to indicate in which direction the input signal crossed the threshold level.

Abstract: It is object to provide a digital-to-analog converter capable of generating an output waveform having less distortion without increasing the operating speed of components. A D/A converter comprises a multiplying section 1, four data holding sections 2-1 through 2-4, four data selectors 3-1 through 3-4, an adding section 4, a D/A converter 5, and two integrating circuits 6-1 and 6-2. Input data is multiplied by four multiplicators by the multiplying section 1, and the four multiplication results are held, as one set, in the data holding sections. The data selectors read out the data held in the four data holding sections in a predetermined order and generate step function data. The adding section adds the values of the step functions outputted from the four data selectors. Furthermore, a stepwise analog voltage corresponding to the sum is generated by the D/A converter 5 and integrated twice by means of the two integrating circuits 6-1 and 6-2.

Abstract: An analog/digital converter including an amplifier (1) wired as an integrator, a comparator (2) electrically downstream from the integrator, a time counter (6) which continually counts the pulses of a pulse generator (5), a bistable element (4), and additional circuitry. The bistable element (4) drives the input network of the amplifier (1) with at least one switch (3) in such a way that in one of its two positions (“off” condition) a current Ix proportional to the analog measured value is integrated, and in the other position (“on” condition) a constant reference current Iref with opposite polarity to the current Ix is integrated in addition to current Ix.

Abstract: In a measurement device, a detector output signal indicative of a condition magnitude, e.g., radiation, pressure, temperature, etc, and a ramp signal are added, and the resulting analog summation signal is converted to a digital signal. The digital signal is sampled, integrated, and averaged over a sampling time corresponding to a predetermined sampling number, such as to achieve a condition measurement signal having reduced analog-digital conversion error.

Abstract: A multiple slope integrating analog-to-digital converter (ADC) includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to come as close as possible to nulling the voltage magnitude at the output of the integrator. A controller keeps track of the charge that has been added to and removed from the integrator during the integrate cycle, and provides a coarse conversion value. The residual voltage is de-integrated to provide a fine conversion value, which is added to the coarse conversion value to provide a final value.

Abstract: A system for transmitting an analog signal comprises converting the input analog signal to a binary signal by detecting the change in sign of the slope of the analog signal and generating a binary signal whose transition occurs at each change of sign of slope of the analog signal. In a preferred embodiment of the invention, the binary signal is transmitted as an amplitude modulation on a carrier frequency over a fiberoptic line to a receiver. The receiver converts the detected binary signal into an analog signal by binary signal gating of a clock signal into an up/down counter whose digital output is converted to an analog signal which is filtered to remove the clock frequency and harmonics of the highest desired input signal frequency thereby providing a replica of the input analog signal. Multiple input signals may be multiplexed and their digital outputs processed in a computer to extract information as in seismographic exploration.

Abstract: A multiple ramp analogue-to-digital converter comprises an integrator connected to receive and integrate an analogue input signal to be converted, and an opposing coarse reference signal. Instead of these signals being applied to the integrator sequentially, as is conventional, they are applied simultaneously. A flash converter is used to provide a rough initial estimate of the magnitude and polarity of the analogue input signal, so that the duration of application of the coarse reference signal can be estimated in advance. A fine reference signal is then applied to the integrator to restore its output to zero and improve the resolution of the conversion.

Abstract: A bipolar analog voltage is converted into a digital signal by sensing the polarity of the voltage and selectively supplying a bias voltage to an analog-to-digital converter, which can preferably be a charge balanced voltage to frequency converter, as a function of the sensed polarity. The voltage to frequency converter has a double valued variable frequency output with a discontinuity at zero volt such that the converter derives a maximum output frequency for a maximum positive voltage and also for a negative value slightly displaced from zero; the voltage to the frequency converter minimum output frequency is derived from positive voltages slightly greater than zero and for maximum negative voltages. The converter output frequency and the sensed polarity are supplied to a frequency to digital converter which derives an output signal having a bit representing the polarity of the analog voltage and additional bits indicative of the magnitude of the analog voltage.

Abstract: There is provided according to the invention a method and apparatus for eliminating or minimizing the error due to amplifier offset or drift error in an integrating dual slope analog-to-digital converter. The converter is provided with a switching and control arrangement whereby the integrating capacitor is charged for one-half of the predetermined charging time as a function of the sum of the levels of the unknown signal and the error signal. The integrating capacitor is charged for the remaining half of the predetermined time period as a function of the difference of the levels of the unknown signal and the error signal so that the capacitor reaches a level of charge which is a function of the level of the unknown signal substantially unaffected by the level of the error signal.

Abstract: There is provided according to the invention a method and apparatus for eliminating or minimizing the error due to amplifier offset or drift error in an integrating dual slope analog-to-digital converter. The converter is provided with a switching and control arrangement whereby the integrating capacitor is charged for one-half of the predetermined charging time as a function of the sum of the levels of the unknown signal and the error signal. The integrating capacitor is charged for the remaining half of the predetermined time period as a function of the difference of the levels of the unknown signal and the error signal so that the capacitor reaches a level of charge which is a function of the level of the unknown signal substantially unaffected by the level of the error signal.

Abstract: A bipolar analog voltage is converted into a digital signal by sensing the polarity of the voltage and selectively supplying a bias voltage to an analog-to-digital converter, which can preferably be a charge balanced voltage to frequency converter, as a function of the sensed polarity. The voltage to frequency converter has a double valued variable frequency output with a discontinuity at zero volt such that the converter derives a maximum output frequency for a maximum positive voltage and also for a negative value slightly displaced from zero; the voltage to the frequency converter minimum output frequency is derived from positive voltages slightly greater than zero and for maximum negative voltages. The converter output frequency and the sensed polarity are supplied to a frequency to digital converter which derives an output signal having a bit representing the polarity of the analog voltage and additional bits indicative of the magnitude of the analog voltage.