Abstract: A control method for fingerprint sensing includes following steps. First fingerprint brightness codes detected in reference with a ramp-counting variable varying in a full range are received during a pre-scanning phase. An initial code is generated according to a distribution of the first fingerprint brightness codes. The initial code is applied to the ramp-counting variable during a normal scanning phase for detecting second fingerprint brightness codes in reference with the ramp-counting variable varying in a partial range. A boundary of the partial range is determined according to the initial code. A control circuit is also disclosure.

Abstract: An analog to digital conversion method includes charging a capacitor through an analog signal to sample a voltage of the analog signal; coupling the capacitor and a plurality of reference voltages to a comparator when a voltage of the capacitor is equal to the voltage of the analog signal, to compare the voltage of the capacitor with the reference voltages and generate a first comparison result; coupling the capacitor to a ramp generator when a status of the first comparison result changes, to compare a ramp signal of the ramp generator with a voltage difference of a first reference voltage and the voltage of the capacitor and generate a second comparison result; obtaining a voltage of the ramp signal when a status of the second comparison result changes; and obtaining a digital code of the analog signal according to the first reference voltage and the voltage of the ramp signal.

Abstract: A method, comprising: receiving an analog input; determining an upper outer rail and a lower outer rail as polling values to be used by voltage comparators; blanking at least three comparators; determining which two of the at least three comparators are closest to the input analog voltage levels; defining the two comparators which are closest to the analog input signal to be the next comparators of the next sampling process; assigning a remaining comparator at a voltage level in between the new top and bottom voltage levels; enabling the outer rails, but blanking the inner rail; progressively narrowing down the voltage range spanned by the two outer comparators; and generating a 2-tuple value of an asynchronous voltage comparator crossing.

Abstract: A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to ½ of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits.

Abstract: A high-quality Analog to Digital Converter (ADC) is used to calibrate a difference attributable to a capacitor mismatch in a Digital to Analog Converter (DAC). The present invention is advantageous in that it can fabricate a low-power high-resolution ADC by calibrating an error attributable to a capacitor mismatch through a digital background calibration apparatus and method using a Successive Approximation Register (SAR).

Abstract: A light intensity subtractor according to one aspect of the present invention includes a light subtraction unit, a feedback circuit, a light input port, a first light output port, and a second light output port. The light subtraction unit receives input light through the light input port, outputs first output light to the first light output port, and outputs second output light to the second light output port. The light subtraction unit generates the first output light by reducing the light intensity of the second output light from the light intensity of the input light in accordance with a control voltage. The feedback circuit is connected to the light subtraction unit through the second light output port, and outputs the control voltage in accordance with the light intensity of the received second output light.

Abstract: A reception device and corresponding method for maintaining a high dynamic range of an AD converter circuit and preventing excessive input to the AD converter circuit is disclosed. For example, a reception device includes a variable gain amplifier circuit that amplifies an input analog signal with a gain controlled by a predetermined control signal, an analog-to-digital converter circuit an overload detector circuit with the same frequency characteristic as the analog-to-digital converter circuit. The overload detector circuit outputs a signal according to a comparison between a level of a signal input to the analog-to-digital converter circuit and a predetermined threshold. The signal that lowers the gain of the variable gain amplifier circuit more greatly is selected out of the signal from the overload detector circuit and another signal, and the gain of the variable gain amplifier circuit is controlled on the basis of the selected signal.

Abstract: An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level.

Abstract: The present invention discloses a DAC circuit and a weight error estimation/calibration method thereof. In the method, an output switching circuit dynamically selects several conversion cells (at least containing know weight conversion cells (KWCC)) as a reference conversion cell group (RCCG) from all conversion cells, and dynamically selects at least one unknown weight conversion cell (UWCC) from all UWCCs. An ADC digitalizes the difference of the output of RCCG and the sum of the outputs of the UWCCs, and inputs the result to a digital controller. The digital controller controls the input of the RCCG according to the output of the ADC to make the output of the RCCG approximate the output of the UWCC. The digital controller uses the outputs of the ADC to work out the actual weights of the UWCCs and stores the actual weights in a calibration memory.

Abstract: A sampling circuit comprising: an input node; a first signal path comprising a first sampling capacitor and a first signal path switch in a signal path between the input node and a first plate of the first sampling capacitor; a second signal path comprising a second sampling capacitor and a second signal path switch in a signal path between the input node and a first plate of the second sampling capacitor, and a signal processing circuit for forming a difference between a signal sampled onto the first sampling capacitor and a signal sampled onto the second sampling capacitor.

Abstract: In one embodiment, an integrated circuit includes a pin and a current source for driving current through the pin into an external resistor such as a resistor on a circuit board to generate a pin voltage. The integrated circuit includes an analog-to-digital converter for converting the pin voltage into a digital value, such as an address for the integrated circuit.

Abstract: Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line and a delta-sigma modulator connected to the bit-line. The delta-sigma modulator may include an integrator having a differential amplifier.

Abstract: An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×M+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.

Abstract: A data acquisition system includes an analog-to-digital converter (ADC) having a MUX control outputs, a controller coupled to the ADC, a multiplexer coupled to the MUX control outputs of the ADC, and an operational amplifier coupling an analog data output of the multiplexer to an input of the ADC. An ADC having integrated multiplexer control includes control logic circuitry, ADC circuitry, MUX logic and an oscillator coupled to the control logic circuitry, the ADC circuitry, and the MUX logic.

Abstract: The present invention relates to the field of mobile terminal technology and describes a calibration device for a mobile terminal and an ADC module thereof, the ADC module being disposed inside a baseband chip. The calibration device includes a bandgap voltage reference inside the mobile terminal platform for generating a reference voltage; the device further includes a circuit for connecting the bandgap voltage reference, the circuit being connected with the ADC module for providing the reference voltage generated by the bandgap voltage reference to the ADC module. The present invention uses a bandgap voltage reference inside a mobile terminal platform to provide voltage to an ADC module, which, during the ADC module calibration, does not require an external reference voltage source to perform the ADC calibration, and therefore greatly reduces calibration errors and improves calibration efficiency.

Abstract: An analog-to-digital converter (ADC) function in which digital error correction is provided. Parallel ADC stages are synchronously clocked to convert an analog input signal into digital words; at least one of the digital outputs is encoded according to an error correction code. Decision logic circuitry decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.

Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N?m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.

Abstract: A device for continuous time quantization of an input signal, in order to supply a continuous time output signal that is quantized as two bits, the device including: an electronic circuit, designed to supply a first bit of the output signal called the sign bit which at any time takes a first value when the input signal is positive and a second value when the input signal is negative, and an envelope analysis circuit designed to supply a second bit of the output signal called the envelope variation bit which at any time takes a first value, called high value, when an envelope signal of the input signal is increasing, and a second value, called low value, when the envelope signal is decreasing.

Abstract: Various embodiments of the present invention provide systems, apparatuses and methods for performing analog to digital conversion. For example, an analog to digital converter circuit is discussed that includes an analog input, a number of analog to digital converters and a generalized beamformer. The analog to digital converters are operable to receive the analog input and to yield a number of digital streams. Each of the analog to digital converters samples the analog input with different phase offsets. The generalized beamformer is operable to weight and combine the digital streams to yield a digital output.

Abstract: A current range control circuit for a data driver in an organic light emitting display. The data driver includes a shift register for outputting a latch control signal, a data latch for sequentially receiving video data and to output the video data in parallel, a digital to analog converter for converting the outputs of the data latch into analog currents, and the current range control circuit for outputting data currents corresponding to the analog currents and controlling the data current range using current range control signals. Because it is possible to control the range of the data currents output from the data driver, it is possible to use the data driver in various pixel circuits or electroluminescent devices by changing the current range control signals, and to make the drain voltages of the transistors that form a current mirror equal to each other to obtain the desired current values.

Abstract: A signal processing system includes a receiving terminal configured to receive a digital signal comprising a plurality of samples associated with a plurality of original sampling times, wherein the original sampling times have a period of T, and a compensation module coupled to the receiving terminal. The compensation module is configured to generate, based on the digital signal, a nominal phase shifted signal having a plurality of nominal phase shifted samples associated with a plurality of phase shifted sampling times, wherein the plurality of phase shifted sampling times correspond to fractional intervals of the original sampling times. The compensation module is further configured to generate a compensated signal based at least in part on the digital signal and the nominal phase shifted signal.

Abstract: A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is interpolated by N and processed by a digital filter to obtain the pulse shape required by the particular communication application. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. When implemented in such manner, the logical implementation and memory replaces digital filtering circuits, DAC decoding logic circuit and re-synchronization logic circuits that are conventionally implemented in hardware. Thus, the hardware functionality of these circuits is rendered into arithmetic form and implemented in a memory device.

Abstract: Line drivers are provided that are suitable for driving communication cables (e.g., in Data Over Cable Service Interface Specification (DOCSIS) certified systems) without the need for output drivers and their size, power-consumption, noise and signal-distortion penalities. These line drivers directly couple switched current mirrors to a transformer's input winding to simultaneously provide currents in response to a differential input signal and a digital command signal and drive the load impedance to thereby realize a corresponding signal gain.

Abstract: A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is interpolated by N and processed by a digital filter to obtain the pulse shape required by the particular communication application. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. When implemented in such manner, the logical implementation and memory replaces digital filtering circuits, DAC decoding logic circuit and re-synchronization logic circuits that are conventionally implemented in hardware. Thus, the hardware functionality of these circuits is rendered into arithmetic form and implemented in a memory device.