Abstract: A device for externally referenced ratiometric signal processing includes an external signal source and a control module. The external signal source has an external voltage reference supply for generating an external reference voltage and a gain & offset circuit for generating a signal voltage. The value of the signal voltage is varies so that the ratio of the signal voltage to the external reference voltage is proportional to the position of a transducer. The control module receives the signal voltage and the external voltage reference. The control module includes an analog to digital converter that converts the signal voltage to a digital signal. The digital signal is proportional to the ratio of the signal voltage to the external reference voltage. A microprocessor may then use the digital signal to infer the position of the transducer.

Abstract: A peak detecting device which can efficiently detect a peak of an analog signal in a smaller error for a short time without making a sampling frequency higher. The analog signal processing apparatus (1) as the peak detecting device comprises: the frequency-dividing ratio setting device (2) for outputting the frequency-dividing ratio setting signal (2a); the frequency divider (3) for frequency-dividing the frequency of the reference clock signal (1b) by the frequency-dividing ratio which is changed by the frequency-dividing ratio setting signal (2a), to generate the sampling clock signal (3a); the A/D converter (4) for carrying out the sampling of the analog input signal (1a) at the clock timing which is synchronized with the sampling clock signal (3a); the sampling data memory (5) for memorizing the digital data (4a) which are obtained by sampling by the A/D converter (4); and the data processor (6) for reading out the digital data (4a) as the digital data (5a), to determine the peak of the digital data (5a).

Abstract: A circuit configuration for calibrating the switching points of a decision module that is controlled by an analog input signal, in dependence on a direct component contained in the input signal in addition to an alternating component, is described. The circuit configuration contains a peak detector for detecting the upper and lower signal peaks of the input signal, a controllable reference unit for providing a reference value, an arithmetic unit for determining a mean value, and a comparison unit. In addition, the circuit configuration has a control unit for compensating the direct component of the input signal and a second control unit which is connected downstream of the comparison unit on the input side and is connected to the reference unit on the outputs side for inversely correcting the reference value.

Abstract: Integrated-circuit structures and methods are provided for generating an error signal that represents temperature and process-induced signal changes in transistor parameters. In particular, a reference transistor and a sense transistor are biased to each generate a substantially temperature-insensitive minority-carrier current. The reference transistor is provided with a substantially constant voltage across its current terminals to convert its minority-carrier current into a substantially temperature-insensitive reference current IR. In contrast, the sense transistor is provided with a temperature-varying voltage across its current terminals to convert its minority-carrier current into a temperature-varying sense current IS. The reference current and the sense current are then differenced to realize an error signal IE that contains information that describes temperature and process-induced signal errors in integrated-circuit transistor stages.

Abstract: In a peak detection system having a variable gain amplifier (VGA), a counter is initialized and a countdown is triggered. Each time a qualified peak is detected, the counter is re-initialized. If the countdown is completed, the VGA gain is updated. This method can be used to boost amplifier gain that is too low to generate a qualifying threshold, even while overlooking short periods of very low output.

Abstract: A device and method are disclosed for the acquisition of data at high flow rates and with high accuracy. The device, called a “Selective Digital Integrator” (SDI), provides many improved features relative to older techniques, and in certain instances it provides a less-expensive replacement for lock-in amplifiers while affording greater functionality and versatility. The device can be integrated into existing instrumentation and technology for high-resolution measurements using various radiation sources (e.g., lamps, lasers, synchrotrons), various polarizations (e.g., linear, circular, elliptical), and various detectors (e.g., photo multipliers, diodes). Unlike the case with conventional lock-in amplifiers, the signal need not be known (or presumed) in advance to have a particular shape, but instead may have an arbitrary or unknown waveform.

Abstract: A noise-immune electronic circuit includes an input circuit for receiving an inbound signal through an input transmission line and comparing the inbound signal with a decision threshold to produce input data of the electronic circuit having one of predefined discrete levels depending on relative magnitudes of the inbound signal and the decision threshold and an output circuit for receiving output data of the electronic circuit and producing therefrom an outbound signal and forwarding the outbound signal onto an output transmission line. The input and output transmission lines are inductively coupled together so that a noise is introduced to the received inbound signal when a voltage transition occurs in the forwarded outbound signal.

Abstract: A digital peak detection system digitizes analog signals and provides absolute values to a series of one cycle delays, and to a sequence of comparator stages. Each digital sample is parallel compared to a number of preceding samples equal to the number of active comparator stages. Control signals activate comparator stages to determine sample comparison window length, including lengths exceeding the number of samples between recorded peaks. Peak detection is optimized using a variable gain amplifier whose gain is updated based upon amplitude difference between actual and desired peak samples. When sample amplitudes are smaller than a qualifier threshold, a countdown timer increases amplifier gain after lapse of a programmed time without detecting a qualified pulse. Gain is also updated when the analog to digital converter saturates. Initial gain values can be programmed, and gain stored at the end of a servo mode for future use in reducing gain control loop convergence time.

Abstract: A robust histogram analysis algorithm is used in accordance with the present invention to control the electronic portal image analog to digital (A/D) window such that the acquired images will have sufficient contrast for their uses in radiotherapy. The algorithm includes setting an initial estimate of a region of interest within a histogram, the histogram including pixel counts and pixel values related to the pixel counts, and determining two dominant peaks inside the region of interest. One of the two dominant peaks is below a predetermined value and the other of the two dominant peaks is between the predetermined value and a second predetermined value. If the one dominant peak is more than two times the standard deviation of the other dominant peak, then a first local minimum to the right of the one dominant peak will be the revised boundary.

Abstract: Peak detection is conducted by converting a continuous waveform into discrete samples. The discrete samples are evaluated to identify three points near a peak of the continuous waveform. After the three points near the peak are identified, they are stored in a discrete domain data structure which is used in conjunction with a table generated from a continuous transformation function in order to identify an accurate peak amplitude and time.

Abstract: A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.

Abstract: To more accurately and more simply realize data collection and analysis for analyzing fatigue phenomenon of materials by the Rainflow Method, strain signals from a strain detecting means attached to an object for analyzing fatigue is A/D-converted at predetermined intervals, a peak of the A/D-converted strain signal is sampled, the peak value is detected, a valley is sampled, the valley value is detected, the difference between the peak value and the valley value is calculated, count values for respective levels are calculated in accordance with the magnitudes of the differences and the count values at the respective levels are written to a memory card detachably provided to the main body of the device of sampling data.

Abstract: An high speed apparatus and method for extending a dynamic range of a signal processing device which receives an analog input signal. A peak indicator uses a 90.degree. phase shifter and zero crossing detector to indicate when the analog input signal is at a peak amplitude within each of its cycles, and an analog to digital converter (ADC) samples input signal amplitude when each peak amplitude is indicated to provide a digital control word for each sampled peak. A gain controller adjusts the gain of the analog input signal provided to the signal processing device in response to the digital word. Preferably the ADC calculates log.sub.2 of the sampled peak amplitude so that the digital word is a power-of-two operator, the gain controller compresses the analog input signal by a factor of one over the power-of-two, and the output signal from the signal processing device is thereafter expanded by a data shifter which shifts the output by an amount corresponding to the power-of-two.

Abstract: A high speed wide bandwidth peak detector uses multiple peak detection stages that detect different sub-ranges of a full-scale analog signal range. Splitting the peak detector into multiple stages reduces the number of taps in each stage, and hence their capacitance, which increases their bandwidth. The number of taps can be further reduced by using a non-uniform resolution of the desired full-scale amplitude range. In the preferred embodiment, identical peak detection stages are separated by fixed gain stages that map the different sub-ranges to respective detection stages. This approach minimizes the effects of offset errors in the individual stages but requires gain stages that have wider bandwidths than the detection stages and which can be closely matched to maintain amplitude resolution.

Abstract: An A/D converter wherein data obtained by A/D converting an analog signal in an A/D converting unit is stored in a first register, the data in the first register and the data in a second register are compared to each other by a comparator, and when the data in the first register is larger (or smaller) than that in the second register, a first switching means is closed so that the data in the first register is stored in the second register. In the second register, a maximum value (or a minimum value) of the A/D-converted data hitherto obtained is stored.

Abstract: A symbol detector (110) includes an analog-to-digital converter (115) for converting signal voltages to digital values and peak and valley counters (310, 315) for tracking the digital values to determine peak and valley values associated with high and low voltages of the signal. The symbol detector (110) further includes calculation circuitry (356) for calculating upper, lower, and center thresholds based on the peak and valley values and a decoder (125) for generating data symbols in accordance with the upper, lower, and center thresholds.

Abstract: A signal frequency analyzer and frequency response shaping apparatus using digital techniques and apparatus and methods using the same which is applicable, in one embodiment thereof, to the enhancement of hearing in hearing impaired persons. Analog techniques are used in another embodiment of the invention. The invention includes hearing enhancement apparatus and methods which employ digital transformation, processing and memory functions for performing a wide range of hearing enhancement functions including the control of instantaneous signal gain levels as a function of instantaneous frequency and amplitude values of an audio signal. In another embodiment, the invention is applicable as a simple and inexpensive frequency analyzer which provides many of the characteristics of a complete Fast Fourier Transform (FFT) suitable for audio signals and other signals where a lower resolution FFT equivalent is acceptable.

Abstract: A system and method for reducing signal-to-noise ratio in a multi-component analog signal during analog to digital conversion. The multi-component analog signal is made up of a plurality of separate analog signals, with each of the separate analog signals having separate amplitude levels. A reference gain control signal, corresponding to the largest amplitude component of the multi-component signal, is first determined. Next, the reference gain control signal is used to generate a gain control signal. The gain control signal is then used to adjust each component of the multi-component signal by a gain value. Finally, the gain adjusted signals are converted to corresponding digital signals.

Abstract: An apparatus and method for detecting analog signals representing patterns of n-bit RLL-encoded data read from a data storage device. R integrators each integrate the analog signal over successive time periods consisting of a preselected number n of bit cycles, where n>1, weighted by a preselected set of n orthogonal signals that are staircase functions which vary each bit cycle to provide R integrated weighted outputs. The R integrated weighted outputs are converted by a lookup table or read-only memory into an n-bit digital representation corresponding to a unique one of the n-bit analog data patterns.

Abstract: A peak and valley measuring circuit (40) featuring a single digital-to-analog converter (DAC) (100), a peak counter (110), a valley counter (120), and a comparator (130). The peak and valley measuring circuit (40) uses the peak counter (110) when detecting peaks of the recovered audio signal and the valley counter (120) when detecting valleys of the recovered audio signal. The DAC (100) is used in conjunction with one of the counters (110) or (120) depending on whether peaks or valleys are being detected, and is preferably a current-mode DAC.

Abstract: The invention discloses a system capable of memorizing maximum sensed values. The system includes conditioning circuitry which receives the analog output signal from a sensor transducer. The conditioning circuitry rectifies and filters the analog signal and provides an input signal to a digital driver, which may be either linear or logarithmic. The driver converts the analog signal to discrete digital values, which in turn triggers an output signal on one of a plurality of driver output lines n. The particular output lines selected is dependent on the converted digital value. A microfuse memory device connects across the driver output lines, with n segments. Each segment is associated with one driver output line, and includes a microfuse that is blown when a signal appears on the associated driver output line.

Abstract: A peak detector for use in a fiber optic receiver has a capacitor, an input amplifier driving the capacitor, and a feedback differential amplifier coupled between the capacitor and an input of the input amplifier. The input amplifier is a complementary buffer with unity gain modified to include an additional transistor on one rail that receives an inverter voltage generated by the differential amplifier. The inverter voltage equals the difference between twice the capacitor voltage and an input voltage applied to the peak detector. The input amplifier in a positive peak detector functions so that the capacitor voltage tracks the input voltage when it exceeds the inverter voltage, and equals the average of the input voltage and inverter voltage when the input voltage is less than the inverter voltage. A negative peak detector operates similarly but with opposite polarity. The peak detector also contains transistors used to reset the capacitor voltage upon assertion of a reset signal.

Abstract: A peak-detection threshold circuit for digitally adjusting an analog peak-threshold level in a magnetic storage read channel. A digital scheme is used to monitor both the positive (PX) and negative (NX) peaks detected in an analog signal. For both positive and negative thresholds T.sub.P and T.sub.N, intermediate peak thresholds T.sub.M are established at selectably lower levels than the peak-detection threshold T.sub.P /T.sub.N. Analog signal peaks are detected when the analog signal crosses the intermediate peak threshold T.sub.M. The corresponding peak-detection threshold T.sub.P /T.sub.N is then compared to the analog peak amplitude. If the intermediate peak threshold T.sub.M and the corresponding peak threshold T.sub.P /T.sub.N are both exceeded by the analog signal, a digital "increment" error flag bit is generated. If only the intermediate peak threshold T.sub.M is exceeded by the analog signal, a digital "decrement" error flag bit is generated.

Abstract: A data channel monitor is provided for a data channel that converts analog signal data to binary digital bits. The monitor allows the quality of the data detected to be measured in conjunction with predetermined processing steps performed in the data channel. The channel monitor obtains channel data and uses the data to determine detection margins, which are a measure of the data quality. The detection margins are compared with an acceptable value(s). Error references are generated if a detection margin is outside an acceptable range. The data monitor also preferably includes a diagnostic capability wherein all detection margins may be stored for off-line analysis whenever the data channel is placed in diagnostic mode.

Abstract: A separator provides peak value data and distance value data, a pair of registers respectively store multiple peak values and distance value data between peak values, a subsequent stage subtracts the series of multiple successive peak values to provide difference data, and divides the difference data by the distance value data to provide quotient data representative of a step size, and an interpolator provides a reproduced waveform by interpolating the peak value data and the quotient data.

Abstract: A method for converting an analog voltage (U) into a digital value, includes the voltage (U) being compared with a plurality of mutually different reference voltages (Ur1 to Urn). Depending on the respective comparison, a binary value is produced, which is stored each in one bistable memory element (F1 to Fn) controlled by an enabling signal (22). Thereafter, the stored binary values are converted into the digital value and the latter is emitted. The enabling signal (22) sets all the memory elements (F1 to Fn) to an initial state at the start of the conversion. It is possible to convert a peak value of an analog voltage (U) into a digital value rapidly and precisely, and the voltage (U) may also have an aperiodic profile.

Abstract: A circuit and method for representing in digital form information about the time and amplitude characteristic of a time-varying input signal. The time-varying input signal is delayed and the magnitudes of the time-varying input signal and its delayed version are compared to produce a digital signal representing the time characteristic of the input signal in the form of a transition in a digital output signal each time the magnitudes of the compared signals have a predetermined relationship. The predetermined relationship may be a condition of approximate equality or when the magnitude of the larger of the compared signals becomes less than the magnitude of the smaller of the compared signals. The invention also includes a circuit for outputting a digital representation of the amplitude of the time-varying input signal for each transition of said digital output signal.

Abstract: A glitch detection circuit having an A/D converter, a state holding circuit, a discrimination circuit and a storing circuit. The A/D converter samples an input signal at a predetermined sampling interval to produce digital data during a predetermined acquisition interval which is longer or equal to the sampling interval. The state holding circuit is connected to an output terminal of the A/D converter, and holds a distribution state of the digital data in the predetermined acquisition interval. The discrimination circuit detects a maximum value and a minimum value during the acquisition interval based on the digital data held in the state holding circuit, and the storing circuit stores the maximum value and the minimum value produced from the discrimination circuit for each acquisition interval.

Abstract: An audio processing method is described wherein an audio input signal is delayed and then submitted for signal processing. The signal is sampled prior to the delay and control parameters for speech compression, voice gating, and voice activation of ancillary equipment generated. The delayed audio is then processed according to the parameters determined prior to the delay to eliminate poor transient response and signal clipping.

Abstract: An analog to digital converter circuit and technique including a peak detector circuit for generating a reference potential corresponding to a peak amplitude of the analog signal to be converted, a level shifting circuit for shifting the dc level of the analog signal in response to the reference potential, and an analog to digital converter for converting the shifted analog signal relative to the reference potential to provide automatically high bit resolution digital signals, independent of the magnitude of the input signal. Preferably, the level shifter sums one half the analog signal and one half the reference potential to produce the shifted signal, and the shifted signal is converted using a ratiometric analog to digital converter having a reference signal input of one half the reference potential. The reference potential is periodically updated by detecting a new peak.

Abstract: A signal digitizer for digitizing a continuous time varying input signal has a positive peak detector coupled to the input signal for storing the most positive peak value of the input signal and a negative peak detector coupled to the input signal for storing the most negative peak value of the input signal. Divider means are coupled to the outputs of the positive and negative peak detectors for producing a threshold voltage representative of a voltage between the outputs of the positive and negative peak detectors. A comparator has its inputs coupled to the threshold voltage and the input signal for producing a binary output signal in response to the relative values of its inputs. Limiter means are coupled to the outputs of the peak detectors for maintaining a maximum voltage potential between the peak detectors. Separator means are coupled to the outputs of the peak detectors for maintaining a minimum potential between the peak detectors regardless of the amplitude of the input signal.

Abstract: An analog-to-digital converter circuit is disclosed for receiving an analog input signal and producing a digital output having a plurality of binary bits representative of the input signal. A number of devices are utilized, each of which has a voltage versus current characteristic with a plurality of peaks, and negative resistance regions between said peaks. In the illustrated embodiments, these devices are resonant tunneling diodes. For each bit to be produced, a pair of said devices are provided, each being coupled in series arrangement with a resistor. Predetermined portions of the input signal are applied to both of the series arrangements for each respective bit to be produced. Signals from both of the series arrangements are combined for each respective bit to be produced. The combined outputs respectively represent the produced binary bits.

Abstract: An apparatus for converting an analog image signal to a digital image signal based on a reference voltage, includes a counter having a control terminal, for counting a first signal and outputting a counted value in digital form, a D/A converter for converting the counted value to an analog voltage signal served as the reference voltage, an A/D converter for converting the analog image signal to the digital image signal based on the reference voltage generated by the D/A converter, and a comparator for comparing in magnitude the digital image signal and a threshold level used for limiting the magnitude of the digital image signal, thereby outputting a control signal based on the results of comparison. The counter continues to count the first signal until the control signal derived from the comparator is supplied to the control terminal of the counter.

Abstract: Disclosed is an analog signal envelope detector, namely a detector that gives a signal representing the slow, overall variations but not the instantaneous variations of the level of an analog signal applied to its input. The detector according to the invention uses a logarithmic compression analog-digital coder of the type used in cofidec circuits for telephone sets. A counter gives the envelope signal sought. A comparator compares the content of the counter and the output of the coder. Depending on the orientation of the comparison, it increments or decrements the counter. The incrementation is made at a frequency which is much faster than the decrementation. The result of this is that the content of the counter represents the envelope of the slow variations of the input signal.

Abstract: A peak-valley detector of an analog signal which provides a digital output of the analog signal. A digital counter is used having an output coupled to a digital-to-analog convertor. The output of the digital-to-analog convertor is compared to an input analog signal. The output of the comparator is used to control the input of a clock signal to the counter. A selective invertor controls whether the comparator's output allows counting for signals above or below the digital-to-analog convertor's output level.

Abstract: An analog-to-digital conversion circuit comprises a level detection circuit for detecting the level of an analog input, an amplifier for amplifying the analog input with its amplification degree increased when the detected level is smaller than a predetermined level and decreased when the detected level is larger than a predetermined level, an analog-to-digital converter for analog-to-digital converting the output the amplifier and an attenuator provided in a posterior stage of the analog-to-digital converter for attenuating the digital output of the analog-to-digital converter in association with the amplification degree of the amplifier to maintain a total gain between the analog input and the digital output substantially constant irrespective of the level of the input signal.

Abstract: An adaptive range circuit (10) suitable for use with an analog to digital convertor (11) having operating range control inputs. The invention includes a peak detection unit (12) that can include a positive peak detector (13) and a negative peak detector (14) that provide signals representative of positive and negative peaks for the incoming analog signal to be digitized. These representative signals can be utilized to control the operating range of the A/D convertor (11).

Abstract: A method of and apparatus for converting between first and second digital data formats is disclosed whereby digital words of the first format are analyzed to detect an upper bandwidth limit of a corresponding analog signal in an interval thereof defined by such words and to determine the level of the analog signal at the beginning of such interval. A digital word of the second format is encoded with first and second pluralities of bits representing the determined upper bandwidth limit and the level of the corresponding analog signal at the beginning of the interval.