Abstract: A methodology for capturing analog information, such as from an analog sensor, including converting the analog information to a train of pulses, representing the analog information as the number of pulses in the pulse train. This pulse count data can be communicated to a processor configured to count the pulses in the pulse train, and convert this pulse count data into digital data corresponding to the analog information. An example embodiment uses a DAC/comparator to convert the analog information (such as a sensor reading) into a pulse train derived from a DAC count (such as can be generated by a DAC counter from an input DAC clock) that is compared with an analog magnitude (analog information), such that the DAC count, which can be represented by a number of DAC clock pulses, provides the pulse train (pulse count data) that corresponds to the analog information.

Abstract: Systems and methods for identifying and reporting failures of an analog to digital (A/D) conversion system are presented. The systems and methods may detect and report a problem of input circuitry of an A/D converter and/or an A/D converter itself. For example, an identifiable characteristic can be introduced into the input signal provided to an A/D converter. The A/D converter may output a digital value that includes the identifiable characteristic of the A/D converter input. A monitoring system may determine and/or report a change in, or a failure of, the A/D converter or input circuitry thereto, based on the identification, non-existence of, or variation in the identifiable characteristic in the digital output.

Abstract: The present invention improves an S/N ratio and light intensity resolution provided by an A/D converter, and an analyzer includes: a measurement cell irradiated with light during sample measurement; a dimming element irradiated with the light during reference measurement; an amplifier configured to amplify an analog light intensity signal outputted from a light detector; an A/D converter configured to convert the analog light intensity signal into a digital light intensity signal; and an arithmetic device configured to calculate absorbance using a digital sample light intensity signal outputted from the A/D converter during the sample measurement and a digital reference light intensity signal outputted from the A/D converter during the reference measurement, wherein an amplification factor of the amplifier is set such that the analog reference light intensity signal and the analog sample light intensity signal become less than or equal to a full scale of the A/D converter.

Abstract: Systems, methods, and devices for selecting modes of operation include, in at least one aspect, a method including: selecting a first mode associated with digital-analog conversion; determining whether a second mode associated with digital-analog conversion is available; if the second mode is available, evaluating one or more switching parameters associated with the second mode; switching from the first mode to the second mode if the one or more evaluated switching parameters satisfy one or more predetermined criteria; analyzing one or more performance parameters after switching from the first mode to the second mode; and setting the second mode as a default mode of operation if the one or more analyzed performance parameters are satisfactory.

Abstract: A modulator and a method are disclosed. The modulator is for generating a band pass signal and comprises: sigma delta modulation logic operable to receive an input signal and to perform at least a 3-level quantisation of the input signal to generate an at least 3-level quantised signal; and requantisation logic operable to requantise the at least 3-level quantised signal to a 2-level quantised signal to be provided as the band pass signal. This approach improves the coding efficiency achieved compared to that possible using a 2-level sigma delta modulator, whilst also providing improved noise performance due to the inherent linearity of the 2-level quantised signal which is provided to drive the switch mode power amplifier. Accordingly, the performance of the modulator is improved by increasing its coding efficiency whilst maintaining its linearity which improves the noise performance in adjacent channels.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to ½ of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits.

Abstract: A time domain switching analog-to-digital converter apparatus and methods of utilizing the same. In one implementation, the converter apparatus comprises a carrier signal source, and at least one reference source. The carrier signal is summed with the input signal and the summed modulated signal is fed to a comparator circuit. The comparator is configured detects crossings of the reference level by the modulated waveform thereby generating trigger events. The time period between consecutive trigger events is used to obtain modulated signal deviation due to the input signal thus enabling input signal measurement. Control of the carrier oscillation amplitude and frequency enables real time adjustment of the converter dynamic range and resolution. The use of additional reference signal levels increases sensor frequency response and accuracy. A dual channel converter apparatus enables estimation and removal of common mode noise, thereby improving signal conversion accuracy.

Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Abstract: A signal mixing circuit which mixes input signal(s) and oscillation signal(s) by mixer block(s) to provide a mixed signal. Each mixer block includes a summing node and a circuit unit; the summing node is arranged to provide a sum signal by summing an input signal and an oscillation signal, and the circuit unit is arranged to alternate between a first state and a second state in response to alternating of the oscillation signal; wherein the circuit unit is arranged to provide driving contribution to the mixed signal in response to the sum signal during the first state, and to stop providing driving contribution during the second state. An associated converter, e.g., a digital-to-analog converter, is also disclosed.

Abstract: Digital-to-analog converter circuitry is described. The digital-to-analog converter circuitry includes a plurality of weighted resistance elements. A first weighted resistance element includes a switch coupled to a reference voltage. The first weighted resistance element also includes a T-network coupled to the switch. The T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element.

Abstract: A threshold estimate system includes a level quantizer, a correlation mechanism, and a threshold adaptation component. The level quantizer is configured to receive an input signal and to generate a quantization signal from the input signal according to one or more threshold levels. The correlation mechanism is configured to correlate the quantization signal with reference symbols to generate an output signal. The threshold adaptation component is configured to modify the one or more threshold levels according to the output signal and the input signal.

Abstract: A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.

Abstract: An intelligent electronic device, and in particular, an electrical power meter, includes an internal calibration system capable of calibrating its measurement mechanisms for the integral nonlinearities introduced by the components which make up those mechanisms, in particular, the analog-to-digital converter. The analog-to-digital converter is coupled with at least one sensor which is operable to sense electrical energy in one or more conductors and output a corresponding electrical signal indicative thereof, the analog-to-digital converter being operative to convert the electrical signal output by the sensor to at least one corresponding digital signal. Integral non-linearity describes the deviation between the ideal output of an analog-to-digital converter and the actual output (after offset and gain errors have been removed).

Abstract: An apparatus and method of successive approximation analog-to-digital conversion for receivers comprising that during a sample mode, connecting an array of capacitors to a plurality of sampling switches coupled to a plurality of amplified input signals, and during a conversion mode, connecting in common the array of capacitors to a comparator and isolating the array of capacitors from the plurality of sampling switches. Additionally, filtering is done by the summation of samples at phase offsets.

Abstract: According to an embodiment, there are provided a capacitor DAC for generating an output signal in accordance with a connection state of a capacitor element, a reference voltage generation circuit for supplying a reference voltage to the capacitor DAC, a comparator for outputting a comparison result in accordance with the output signal, a successive approximation register for outputting a digital signal in accordance with the comparison result, and a control circuit for controlling a connection state of the capacitor element in accordance with the comparison result and comparing an ideal code with a digital signal obtained by sampling a predetermined voltage, thereby correcting an error of the digital signal.

Abstract: A sigma-delta (??) difference-of-squares LOG-RMS to digital converter” by merging a traditional ?? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares concept. Two basic architectures include one based on two squaring cells in the feedforward and feedback paths and a second based on a single squaring cell in the forward path. High-order ?? LOG-RMS can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The embodiments as described allow the implementations of ?? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.

Abstract: The device comprises a successive approximation register, a capacitive digital-to-analog converter comprising a plurality of capacitors, the plurality of capacitors being coupled with a first side to a common node; a comparator coupled to the common node and being adapted to make bit decisions by comparing a voltage at the common node with another voltage level, and a SAR control stage for providing a digital code representing a conversion result. The device is configured to operate in a calibration mode, where the device is configured to sample a reference voltage on a first capacitor of the plurality of capacitors by coupling one side of the first capacitor to the reference voltage, to perform a regular conversion cycle with at least those capacitors of the plurality of capacitors having lower significance than the first capacitor and to provide the conversion result of the regular conversion cycle for calibrating the first capacitor.

Abstract: A non-linear power amplifier generates an amplified output signal based on a pre-distorted signal generated by a digital pre-distorter (DPD) based on an input signal. A feedback path generates a feedback signal based on the amplified output signal. The feedback signal is aligned with the input signal, or vice versa, and the aligned signals are used to adaptively update the DPD processing. In particular, a linear FIR filter is estimated to minimize a cost function based on the input and feedback signals. Depending on how the filter is generated, the filter is applied to the input signal or to the feedback signal to generate the aligned input and feedback signals.

Abstract: A data acquisition system includes an analog-to-digital converter (ADC) having a MUX control outputs, a controller coupled to the ADC, a multiplexer coupled to the MUX control outputs of the ADC, and an operational amplifier coupling an analog data output of the multiplexer to an input of the ADC. An ADC having integrated multiplexer control includes control logic circuitry, ADC circuitry, MUX logic and an oscillator coupled to the control logic circuitry, the ADC circuitry, and the MUX logic.

Abstract: A digital-to-analog converter is disclosed. The converter includes a gradient correction module that generates a correction term based on a model of gradient error. The correction term is then applied to the signal path in the digital domain or applied to the output of the digital-to-analog converter in the analog domain. The model used to generate the correction term is based on a vertical gradient error in the array of current source elements, which may be modelled and calibrated using a second-order polynomial. Further, a digital-to-analog converter having a Nyquist DAC and an oversampled DAC is disclosed. When the oversampled DAC is enabled, the resolution of the Nyquist DAC may be increased while slowing the conversion rate.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: A control system provides a control signal to a nonlinear plant that generates a response signal responsive to the control signal. The control system includes a detector that detects a predetermined value of a plant quantity, valley switching logic, coupled to the detector, to change a state of a plant switch when the plant quantity is minimized, and a pulse-width modulator, coupled to the valley switching logic, to generate a control signal that controls the plant switch. The valley switching logic includes a nonlinear delta-sigma modulator that compensates for an error in a plant response signal by adjusting the duration of an on-time of a plant switch to cause an average value of the plant response signal to converge toward a target signal value.

Abstract: An analog-to-digital converter (ADC) function in which digital error correction is provided. Parallel ADC stages are synchronously clocked to convert an analog input signal into digital words; at least one of the digital outputs is encoded according to an error correction code. Decision logic circuitry decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.

Abstract: A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.

Abstract: A non-linear amplifier is linearized using interpolation-based digital pre-distortion (DPD). In one embodiment, the digital input signal is interpolated to generate a higher-sample-rate signal that is then pre-distorted. The resulting higher-sample-rate pre-distorted signal is then decimated to generate a final pre-distorted digital signal that is converted into an analog pre-distorted signal by a digital-to-analog converter (DAC) before being applied to the amplifier. In a polyphase embodiment, different versions of the original input digital signal are generated, where each version is then pre-distorted using a different DPD module to generate a different intermediate pre-distorted digital signal. The intermediate pre-distorted signals are filtered and combined to generate the final pre-distorted digital signal. In both embodiments, better linearization (e.g.

Abstract: The invention includes a successive approximation register, a digital-to-analog converter, a comparator and a control stage. The control stage initially sets the successive approximation register to a first digital value. The digital-to-analog converter converts the digital value stored in the successive approximation register to an analog value. The comparator compares the converted digital value with an analog input value. The control stage restricts subsequent analog-to-digital conversion for the analog input value to a search interval above or below the first digital value depending on whether the analog input value is greater or lower than the converted analog value of the first digital value.

Abstract: A precision charge dump circuit configured to transfer preset quanta of charge to or from a first capacitor (for example, an integration capacitor in an in-pixel ADC circuit). In one example, the charge dump circuit uses a second capacitor that is pre-charged with the preset quanta of charge to determine the preset value of the quanta of charge, and an amplifier in a voltage-follower mode to cause the charge subtraction or addition.

Abstract: A circuit for providing audio signals to a load such as a speaker is provided that uses the speaker or headphone amplifier structure as a current to voltage converter, thereby eliminating a separate current to voltage converter from the circuit. Such a design removes one of the elements that creates noise in the circuit architecture and improves the dynamic range for the audio signal. For example, the output of a digital to analog converter is a single ended output provided to the speaker or headphone amplifier. The digital to analog converter can include a series of current sources that are summed up to provide the single ended output. Where the current sources have positive and negative current source mismatch, a feedback mechanism is employed to correct for the mismatch and reduce introduction of harmonic noise into the signal through the digital to analog converter.

Abstract: An analog-digital conversion system comprising at least one variable gain amplifier amplifying an input signal e, an analog-digital converter CAN digitizing said signal e, an interference-suppressing digital processing module, processing the digitized signal, also comprises a first automatic gain control AGC loop, called the analog AGC loop, that compares an estimate of the output power of the CAN converter with a control setpoint g1 called the control setpoint of the analog AGC loop, a gain ga used to control the variable gain amplifier being deduced from this comparison. The system also comprises a second automatic gain control AGC loop called the digital loop, said digital loop comparing an estimate of the power after the interference-suppressing digital processing with a predetermined control setpoint gn, the analog AGC loop being controlled by a control setpoint deduced from this comparison.

Abstract: A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.

Abstract: An analog-to-digital conversion apparatus includes: a first analog-to-digital converter configured to convert an input analog signal into a digital signal; a second analog-to-digital converter configured to convert an analog signal generated by multiplying the input analog signal by ? times with a coefficient ? into a digital signal; a first non-linear compensation part configured to compensate a non-linear distortion of a first output signal of the first analog-to-digital converter; a second non-linear compensation part configured to compensate a non-linear distortion of a second output signal of the second analog-to-digital converter; and a non-linear detection part configured to estimate how much the non-linear distortions of the first and second analog-to-digital converters are compensated by the first and second non-linear compensation parts depending on first and second signals by the first and second non-linear compensation parts.

Abstract: A signal-linearization system and method reduces nonlinear distortions in a digitized signal generated by an analog-to-digital converter (ADC) when converting an analog input signal from analog to digital form. A signal adder adds a dither waveform to the analog input signal. An ADC includes sample-and-hold (S/H) circuitry and quantizer circuitry. The ADC converts the analog input signal with the added dither waveform into a digitized signal. The dither waveform operates to suppress nonlinear distortions attributed to the quantizer circuitry. A linearizer processor performs nonlinear equalization (NLEQ) on the digitized signal to suppress nonlinear distortions attributed to the S/H circuitry. A dither waveform removal module removes a digital counterpart of the dither waveform from the digitized signal.

Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N?m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.

Abstract: An electronic device and a method for driving an internal function block of a processor of the electric device to operate in a linear region. The electronic device comprises a processor having two multiple purpose pins (MPP1 and MPP2), an external device connection port, and two resistance elements. The external device connection port is further connected to the MPP1 and at a tested voltage. The first resistance element is connected between a high level voltage and the external device connection port. The second resistance element is connected between the external device connection port and the MPP2. The processor is configured to output the high or low level voltage at MPP2 when the tested voltage is in a non-linear operating region, to guarantee the tested voltage to a linear operating region of the function block which is coupled to the MPP1 by a multiplexing design.

Abstract: Embodiments of the present invention provide improved accuracy of displacement control by using a multi-segment transformation of an actuator's non-linear response. The present invention may set intermediate points to effectively divide the actuator response into multiple segments. Each segment may be assigned a transform function that represents the actuator's response in that particular segment. The present invention may operate in two modes, a calibration mode and a normal operations mode. During calibration mode, the intermediate points and the segment transforms may be set. During normal operations mode, a drive signal may be generated according to the calibrated set values.

Abstract: A method and apparatus are provided for Fast Data Weighted Average (DWA) double-sampling modulators with minimal loop delay supporting improved stability. Quantization and DEM are accomplished within non-overlap time. By this reduction in time delay, power can be saved for analog integrators. The DC signal of partitioned DWA is removed by alternating reference voltages, and there is no additional delay as the alternation is performed at the comparator inputs. Embodiments employ an oversampling ratio (OSR) of 8 and a 15-level quantizer.

Abstract: A method of analog to digital voltage conversion including: generating a quadratic signal based on an analog time varying reference signal; generating a ramp signal based on the quadratic signal; and converting an analog input voltage to a digital output value based on a time duration determined by a comparison of the analog input voltage with the ramp signal.

Abstract: An optical code division multiplexing signal generator provided with an optical pulse light source, a first encoder to an Nth encoder, a first optical modulator to an Nth optical modulator, and a first optical circulator to an Nth optical circulator. The first optical circulator inputs an input optical pulse train to a first encoder, and inputs a first encoded optical pulse train output by Bragg reflection from the first encoder to the first optical modulator. The kth optical circulator inputs an input (k?1)th optical pulse train which has passed through the (k?1)th encoder to a kth encoder, and inputs a kth encoded optical pulse train output by Bragg reflection from the kth encoder to the kth optical modulator. Herein k takes all integers from 2 to N, and N is a positive integer of 2 or more.

Abstract: An A/D conversion circuit includes an amplifier circuit that includes a plurality of amplifiers that are cascaded, a selector that selects one of output signals output from the plurality of amplifiers and outputs the selected output signal as a selector output signal, an A/D converter that A/D-converts the selector output signal output from the selector, a determination circuit that determines whether or not a voltage of the output signal output from each of the plurality of amplifiers is within a determination voltage range specified by a high-potential-side determination voltage and a low-potential-side determination voltage, and a control circuit that instructs the selector to select one of the output signals output from the plurality of amplifiers based on the determination result of the determination circuit.

Abstract: An apparatus for analog-to-digital conversion using successive approximation is provided. There is a successive approximation register or SAR controller for providing a digital code representing a conversion result, and an integral non-linearity (INL) compensator configured to provide an INL compensation signal for reducing INL of the analog-to-digital conversion in response to the digital code.

Abstract: A reference voltage generating unit generates a plurality of analog reference voltages, and an A/D converting unit converts the analog reference voltages thus generated and an analog input voltage input from an external device to digital reference values. A CPU generates, based on the analog reference voltages and the digital reference values converted from the analog reference voltages, an equation for correcting the analog input voltage to be converted to a digital value falling in a range of the digital reference values. With the equation generated, the CPU calculates the analog input voltage for the digital value obtained by conversion.

Abstract: A control method is provided for a fluid control device, particularly for an internal combustion engine, equipped with a position sensor having a nominal characteristic curve representative of a predetermined relationship between an admissible range of position values and a corresponding range of return electric signal values. The method includes, but is not limited to determining an offset (offsetopen; offsetclose) between a returned signal related to at least one defined position of the device and an expected signal related to the defined position of the device according to the nominal characteristic curve, estimating an updated characteristic curve of the sensor by applying the offset (offsetopen; offsetclose) to the nominal characteristic curve, and applying a predetermined control strategy of the fluid control device according to the updated characteristic curve.

Abstract: An automatic power level control circuit provides output power control of a transmitter device as used in wireless LAN applications in that an output signal is detected and a corresponding control voltage of a DAC in the base band section is corresponding adjusted. Preferably, the measurement of the output power is carried out during a first transmit cycle and the DAC is adjusted after completion of the first transmit cycle and prior to the begin of a subsequent transmit cycle. Thus, a reliable output level control is obtained with a minimum number of radio frequency components, wherein the control loop shows an enhanced stability due to the time-discrete control operation.

Abstract: An analog-to-digital converter based on an interleaving architecture is disclosed. The analog-to-digital converter can include a first sample and hold circuit for sampling and temporarily storing a first input signal. The analog-to-digital converter can also include a comparator for converting the sampled first input signal into a digital signal in a first time period. The analog-to-digital converter can further include a second sample and hold circuit for sampling and temporarily storing a second input signal in a second time period. The second time period at least partially overlaps with the first time period.

Abstract: An optically sampling device optically samples an optical analog signal using a sampled signal having a predetermined sampling frequency, and outputs control light having a pulse train of an optically sampled optical analog signal. A signal generating device generates a pulse train of signal light which is synchronized with the sampled signal. An optical encoding device optically encodes the pulse train of the signal light according to the control light, by using optical encoders each including nonlinear optical loop mirrors, and outputs pulse trains of optically encoded signal light from said optical encoders, respectively. An optically quantizing device performs optical threshold processing on the pulse trains of optically-encoded signal light to optically quantize them, by using at least one of optical threshold processors each of which is connected to each of said optical encoders and includes a nonlinear optical device, and outputs optically quantized pulse trains as optical digital signals.

Abstract: A linearity corrector is provided that reduces distortion in a signal processing system, such as an ADC. The linearity corrector provides a first order signal path having distortion components connected to an adder, and a filter product circuit that is also connected to the adder. A method is provided for reducing distortion by calculating a filter product and adding the filter product to a first order signal having a relative delay such that the filter product reduces, or eliminates, the order of distortions corresponding to the order of the filter product.

Abstract: When tracing memory events the required bandwidth may be reduced by forming a logical OR of several memory event signals to determine the location of memory events. A second trace run may be made after this, tracing only the limited portions of the application where the first run indicated possible problems.

Abstract: A digitally programmable gain control circuit and method of operating the same is disclosed. The gain control circuit includes a programmable gain amplifier having an amplifier structure represented by a plurality of overlapping discrete monotonic transfer function segments, wherein at least one point of non-monotonicity occurs among one or more of the plurality of overlapping discrete monotonic transfer function segments, and a gain segment translator circuit operative to translate a monotonic gain value to a segment code to match the non-monotonic characteristics of the programmable gain amplifier. The programmability of the gain amplifier is provided by a coarse gain control circuit and a fine gain control circuit.

Abstract: An adaptive controller generates a sequence of dither signals for each of a plurality of control parameters. Each dither signal sequence is uncorrelated with every other dither signal sequence. Each nominal control signal has the first of its respective dither signal values simultaneously summed with it to form the control parameter values used by the controller. Updated control signals are applied in parallel to the controller outputs and a performance measure is taken and stored. The second signals in the dither control sequences are then summed with their respective nominal controls and applied in parallel to the controller and a second performance measure is taken and stored. This process is repeated for the length of the dither control signal sequence to yield a sequence of performance measurements. The sequence of performance measurements is correlated with each of the dither sequences, forming sequences of correlator outputs, one for each control signal.