Abstract: Methods, apparatuses, and computer program products for wireless communication are provided. A user equipment (UE) may be configured to determine a phase rotation for a symbol based at least in part on a tone index. The UE may be configured to apply the phase rotation to the received symbol, and transmit the uplink symbol. Numerous other aspects are provided.

Abstract: An illumination source is operated to illuminate an operating environment and an optical sensor is periodically operated for a detection period to detect illumination reflected from one or more subjects within the operating environment. Upon recognizing a source of interfering pulsed illumination within the operating environment, the timing of a subsequent detection period may be varied. In this way, sensing of the interfering pulsed illumination may be averted.

Abstract: An OFDM communication transceiver, which is configured to test its connection with an antenna circuit unit, has a receiver chain and an emitting chain. The receiver chain includes a time-to-frequency transform unit and the emitting chain includes a frequency-to-time transform unit. The transceiver further includes means for disconnecting the receiver chain to the antenna circuit unit, means for providing a stimulus as input to the emitting chain, means for reintroducing the signal at the output of the emitting chain as an input of the receiving chain, means for determining a circuit resonance frequency, Fr, and a quality factor, Q, of a transfer function computed from the output of the time-to-frequency transform unit, and means for deciding about the connection of said antenna circuit unit according to the resonance frequency and the quality factor.

Abstract: A communication system is provided. A receiver receives a plurality of audio signals, wherein a frequency of each of the audio signals is selected from a frequency group formed by at least three frequencies. A signal detector coupled to the receiver is configured to obtain the frequency of each of the audio signals. A processor coupled to the signal detector is configured to convert the frequency of each of the audio signals into a digital signal having a first logic level or a second logic level. Two adjacent audio signals of the audio signals have different frequencies, and at least one frequency of the frequency group is used to dynamically represent the first logic level or the second logic level.

Abstract: A relaxation oscillator includes a first amplifier having a first input terminal receiving an output voltage signal, a second input terminal receiving a reference voltage signal, and an output terminal comparing the output voltage signal and the reference voltage signal and in response thereto outputting a control signal; a second amplifier having a first input terminal receiving the output voltage signal, a second input terminal connected to the output terminal of the first amplifier for receiving the control signal, and an output terminal connected to the first input terminal of the first amplifier and the first input terminal of the second amplifier for comparing the control signal and the output voltage signal and in response thereto outputting the output voltage signal; and a sensing capacitor for generating the output voltage signal by charging/discharging operations by the output terminal of the second amplifier.

Abstract: A sorting decoder captures the rank-order of a set of input analog signals in the digital domain using simple logic components such as self-timed first state elements, without requiring conventional analog-to-digital signal converters. The analog signals are each compared against a monotonic dynamic reference and the resulting comparisons are snapshot by a self-timed first state element for each input signal, or the last member of a sorted collection of input signals, at the time when it reaches the reference signal, so that a different snapshot representing the signal value ranking relative to the other signal values is produced for each input signal. The resulting rank-order estimation snapshots are binary signals that can then be further processed by a simple sorting logic circuit based on elementary logic components.

Abstract: Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: encoding an information bit and generating a block coded with an NCBPSS bit; generating two sub-blocks by parsing the coded block; and transmitting the two sub-blocks from the transmitter. By preventing the bits that are contiguous to the encoding block from having continuous identical reliabilities on a signal constellation, the deterioration of the decoding performance of the transmitter can be prevented.

Abstract: A system and method for securing wireless communications are provided. A method for secure communications by a first user includes estimating a channel between the first user and a second user based on a pilot signal transmitted by the second user, determining a first threshold and a second threshold based on the estimate of channel, selecting a first subset of channel estimates, signaling the first subset of channel estimates to the second user, receiving a second subset of channel estimates from the second user, for each channel estimate in the second subset of channel estimates, quantizing the channel estimate based on a relationship between a gain of the channel estimate and the first threshold and the second threshold, generating a first secret key based on quantized channel estimates, verifying that the first secret key matches a second secret key generated by the second user, and transmitting information to the second user.

Abstract: Encoding and decoding methods and apparatus as described.

Abstract: Methods and apparatuses for reducing noise in frequency to digital converters (FDCs). An FDC apparatus includes a first FDC, a second FDC and a combiner. The first and second FDCs are configured to independently sample an input signal according to a sample clock to generate first and second digital signals, each representing the instantaneous frequency of the input signal. The combiner is configured to form a resultant digital signal from the first and second digital signals. The first and second FDCs are designed and combined in the noise-canceling FDC apparatus so that the first and second signals they generate have correlated noise profiles in a frequency range of interest. When combined by the combiner to form the resultant digital signal, the resultant digital signal has a signal power to noise power ratio greater than the signal power to noise power ratios characterizing the first and second digital signals of the individual first and second FDCs.

Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called preceding to the modulation encoded bit stream. However, this preceding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before preceding is applied by the precoder. The decoder subsystem operates in the inverse manner.

Abstract: A serial I/F has: a FIFO portion to which m- or n-bit (m<n) parallel data is written based on PCLK; a FIFO reader that reads the parallel data written to the FIFO portion m bits at a time based on FCLK; a parallel/serial converter that converts the m-bit parallel data read by the FIFO reader into 1-bit serial data based on PLLCLK; a PLL circuit that produces PLLCLK by multiplying PCLK by a factor of m or n; and a frequency divider circuit that produces FCLK by dividing the frequency of PLLCLK by m. Here, the multiplication factor of the PLL circuit is so controlled as to be changed according to the number of bits of the parallel data written to the FIFO portion. This makes it possible to flexibly deal with parallel inputs having different bus widths without unduly increasing a device scale and cost.

Abstract: An embodiment method of generating an output pulse stream comprises first pulse modulating a first multi-bit input term to generate a first one-bit pulse stream, using a bitwise logic AND to combine the first one-bit pulse stream and a second multi-bit term, thereby generating a multi-bit AND output, and second pulse modulating the multi-bit AND output to generate a one-bit output pulse stream representing a product of the first and second multi-bit input terms.

Abstract: An embodiment method of generating an output pulse stream comprises first pulse modulating a first multi-bit input term to generate a first one-bit pulse stream, using a bitwise logic AND to combine the first one-bit pulse stream and a second multi-bit term, thereby generating a multi-bit AND output, and second pulse modulating the multi-bit AND output to generate a one-bit output pulse stream representing a product of the first and second multi-bit input terms.

Abstract: Provided is an audio signal encoding method including transforming an input signal from a time domain to a time/frequency domain using a first transformation method, extracting a stereo parameter from a signal of the time/frequency domain, encoding the stereo parameter, and down-mixing the signal of the time/frequency domain, transforming each of sub-bands of the down-mixed signal to a frequency domain by using a second transformation method, and encoding the signal of the frequency domain in the frequency domain.

Abstract: There is provided a digital signal processing device capable of suppressing occurrence of an unnecessary frequency component (spurious) in performing a reduction processing of a bit number of a frequency signal made of a digital signal. A signal output section 10 outputs a frequency signal by a digital signal made of bit data and an addition section 16 adds noise data for suppressing occurrence of an unnecessary frequency component to the bit data. A reduction processing section 11 performs a predetermined processing in correspondence with whether the bit data obtained in the addition section 16 is positive or negative, and thereafter, shifts each bit of the bit data to the right by m digits set in advance (m is an integer smaller than a bit number of the bit data) and cut off an m-bit portion to reduce the number, rounding down “0” and rounding up “1” for the most significant bit of the bits having been cut off.

Abstract: Techniques for improving encoding and decoding data are described herein. According to one embodiment, it is determined whether a current context can encode a retrieved symbol. The current context includes a plurality entries, each representing an encoded symbol, including a count value representing a frequency of the entry being used. A code is generated to a code stream, where the code represents a difference between an index of an entry in the current context associated with the retrieved symbol and a previous index used for encoding a previous symbol, if the current context can encode the retrieved symbol. A count value corresponding to the entry associated with the retrieved symbol is incremented in the current context. The current context is sorted based on count values of all entries in the current context, where the code stream and the literal stream are to be compressed and encoded by a compressor.

Abstract: In a method and apparatus for encoding a tag with an n-bit binary code one or more predetermined frequency sources are associated with the tag that produce known different respective characteristic frequencies, each of which is associated with a known unique position in the n-bit binary code.

Abstract: The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

Abstract: A clock synchronization device is disclosed that includes a phase detecting unit for detecting a phase difference between an external clock signal and an internal clock signal, a binary code generating unit for outputting a binary code value according to output signals from the phase detecting unit, a code converting unit for converting the binary code value from the binary code generating unit into a thermometer code value, a D/A converting unit for outputting a voltage corresponding to the thermometer code value from the code converting unit and a clock synchronization control unit for outputting the internal clock signal from the external clock signal according to the output voltage from the D/A converting unit. As the result, the clock synchronization device is controlled by employing the D/A converting unit for converting the binary code to the thermometer code in order to decrease the number of the registers, the leakage current and the chip size.

Abstract: A digital encoding system for encoding a series of input bits into a plurality of frequencies, includes an encoder for generating a sampled representation of the frequencies corresponding to an input data sequence comprised of bits, and a decoder. The decoder incorporates a Fourier Transform means for recovering the data stream.

Abstract: A digital/analogue communication system is described, where data is generated and received by a processing unit in a digital format and transmitted via a communication path in an analogue format. A DSP unit receives a sequence of multi-bit digital samples at a first sampling rate and generates a plurality of interpolated samples. A bit generation unit receives the multi-bit digital samples and the interpolated samples and generates a sequence of single-bit digital samples at a second sampling rate which is higher than the first sampling rate. A set of single wire communication paths are used to convey the single-bit digital samples to respective digital to analogue converters. The use of single-bit digital samples allows them to be held in a buffer. A buffer controller can be provided to delete single-bit digital samples from the buffer so as to match the sampling times at at least one reference frequency of a received signal with sampling times of a generated signal.

Abstract: A digital encoding system for encoding a series of input bits into a plurality of frequencies, includes an encoder for generating a sampled representation of the frequencies corresponding to an input data sequence comprised of bits, and a decoder. The decoder incorporates a Fourier Transform means for recovering the data stream.

Abstract: An optical demultiplexer demultiplexes an N channel multiplexed optical data signal, at a first data rate, into N signal data channels. The demultiplexing is provided by N optical receivers, each receiver receiving a clock signal and the multiplexed optical data signal which is demultiplexed into a different one of the N signal data channels. In another embodiment, a shared photodetector converts the received multiplexed optical data signal into a multiplexed data signal which is then used by all of the N receivers.

Abstract: A discrete multi-tone communication system employing bin-to-bin differential encoding of data frames to be transmitted within the communication system. The bin-to-bin differential encoding utilizes the phase angle of previously encoded data to encode the current data relative to that phase angle. Hence, only a single reference tone is required to encode a first portion of the data frame into a discrete tone, and then the remaining data portions of the data frame are each subsequently encoded into discrete tones with reference to the phase angle of data already encoded into a discrete tone. Thus, to achieve decoding, a decoding device only requires the reference tone to begin decoding the discrete tones to the correct phase angle for an accurate reproduction of the original data frame.

Abstract: A data capture circuit includes a character detection circuit and a word detection circuit. The character detection circuit determines values for characters represented by a signal having a frequency. In making such determinations, the values for characters are based on an accumulation of differential samples of the signal. The word detection circuit is coupled to receive the values for characters from the character detection circuit. The word detection circuit determines a word value based on the received values for characters. The word detection circuit includes a comparison circuit and an accumulator. The comparison circuit compares a value for a character in a word to a to a value for at least one other character in the word and provides a character value based on the comparison. The accumulator has an input coupled to receive character values from the comparison circuit and an output to provide a summation of character values received by the accumulator.

Abstract: An associative memory is utilized to perform LZW data compression. The respective locations of the memory contain a prefix code field and a character field. A register containing a code field and a character field is associatively compared to the locations of the memory to determine if a match exists therewith. If a match is found, the address of the match is inserted in the code field of the register and the next input character is inserted in the character field thereof. This process is continued until no match occurs. The code existing in the code field of the register is transmitted as the compressed code of the string and the contents of the register is written into the next empty location of the memory. A next cycle is initiated by nulling the code field of the register and repeating the described steps.

Abstract: In this invention, in the case of transforming an input waveform signal into frequency components at a frequency component decomposing circuit 701 to allow the frequency components from the frequency component decomposing circuit 701 to undergo normalization and quantization, and encoding at a normalizing/quantizing circuit 702 and a code train generating circuit 703, operation of QMF is omitted with respect to bands of the unnecessary side by a processing band control circuit 704, whereby the number of operations necessary for filter operation is reduced so that high speed operation can be carried out and work area necessary for filter operation can be reduced. Namely, this invention can simplify filter operation in accordance with, e.g., required quality of reproduction signal, and can reduce circuit scale of encoding unit/decoding unit.

Abstract: Methods and apparatus for recording, reproducing, transmitting and/or receiving compressed data, and a recording medium therefor, utilize frequency dividing filters for dividing the frequency range of digital signals into plural frequency bands, orthogonal transform circuits for producing signal components in plural two-dimensional blocks along time and frequency, an adaptive bit allocation and encoding circuit for quantizing and compressing the information for each two-dimensional block and a bit allocation and calculating circuit. When recording the information together with information compressing parameters for each two-dimensional block, the information compressing parameters for at least two two-dimensional blocks are recorded collectively to avoid complicacy in the structure of the sampling frequency signal generating circuits or the like otherwise caused in case of providing plural sampling frequencies as well as to prevent an increase in hardware scale.

Abstract: In a method for limiting the bandwidth of a selected binary signal (B), there is produced a modulated digital signal (D) which presents a continuous series of changes in signal level. The two occurrent logic states (1,0) are each represented by a respective symmetrical pulse train, wherein the frequencies f1, f2 of the pulse trains are mutually different. The higher frequency f2 is equal to the number of bits transmitted each second divided by two herz. The transition between the two pulse trains is arranged so that the integral of the resultant signal will be zero within the duration of three of four data bits. In a preferred embodiment of a coder and decoder each include a code word counter which, together with a combinatory logic circuit (code word table) activates or is activated by a shift register for transmitting or receiving respectively the modulated digital signal.

Abstract: Sample values of a digital signal of a first sample rate are supplied to a digital filter for conversion into a digital signal of a second sample rate. The coefficients of the digital filter are calculated by a processor from the ratio of the sample rates or are obtained by a read-only memory containing sets of coefficients for respective sample rate ratios for which the apparatus is usable. Filtered sample values are read out of the digital filter at the desired second sample rate. A buffer memory is used at the input of the digital filter and a regulator is provided to prevent fluctuations in the filling of the buffer memory from emptying or exceeding the capacity of the buffer memory.

Abstract: A relatively simplified sampling frequency converter for use in a format conversion apparatus is operative to convert sampled input data of an input sampling frequency into sampled output data of an output sampling frequency. The converter has an over-sampling circuit for increasing the sampling frequency of the sampled input data by a predetermined factor or coefficient to provide over-sampled data; an output data extractor for periodically extracting data from the over-sampled data in response to a timing pulse having the output sampling frequency; and a controller for controlling the phase of the timing pulse which controls the phase of the sampled output data.

Abstract: A method of and apparatus for converting between first and second digital data formats is disclosed whereby digital words of the first format are analyzed to detect an upper bandwidth limit of a corresponding analog signal in an interval thereof defined by such words and to determine the level of the analog signal at the beginning of such interval. A digital word of the second format is encoded with first and second pluralities of bits representing the determined upper bandwidth limit and the level of the corresponding analog signal at the beginning of the interval.