Abstract: A method, computer system, and a computer program product for high-speed data compression is provided. The present invention may include receiving an input stream. The present invention may include selecting a header based on the received input stream, wherein the header includes a base, a scheme and a delta count. The present invention may include determining whether there are any remaining values in an uncompressed input stream. The present invention may include reading a first next value from the input stream. The present invention may include determining whether the read first next value is representable with a current base scheme. The present invention may include calculating the delta count based on determining that the read first next value is representable with the current base scheme. The present invention may include writing the calculated delta count to the selected header. The present invention may include incrementing the written delta count.

Abstract: A lossless encoding method is provided that includes determining a lossless encoding mode of a quantization coefficient as one of an infinite-range lossless encoding mode and a finite-range lossless encoding mode; encoding the quantization coefficient in the infinite-range lossless encoding mode in correspondence with a result of the lossless encoding mode determination; and encoding the quantization coefficient in the finite-range lossless encoding mode in correspondence with a result of the lossless encoding mode determination.

Abstract: A method, computer system, and a computer program product for high-speed data compression is provided. The present invention may include receiving an input stream. The present invention may include selecting a header based on the received input stream, wherein the header includes a base, a scheme and a delta count. The present invention may include determining whether there are any remaining values in an uncompressed input stream. The present invention may include reading a first next value from the input stream. The present invention may include determining whether the read first next value is representable with a current base scheme. The present invention may include calculating the delta count based on determining that the read first next value is representable with the current base scheme. The present invention may include writing the calculated delta count to the selected header. The present invention may include incrementing the written delta count.

Abstract: An electronic device obtains a file header for a file that corresponds to a plurality of clusters. The file header includes a cluster index that enables coarse searching within the file. At least one of the file header and the file omits information that is known to or calculable by the device for extracting content from the file. In response to receiving a request to seek to a position within the file, the device identifies a cluster that includes content that corresponds to the position based on the cluster index and obtains a cluster header that enables fine searching within the cluster. After obtaining the cluster header, the device identifies, within the cluster, the content that corresponds to the position based on the content index and provides at least a portion of content corresponding to the file to a presentation device, starting with the content that corresponds to the position.

Abstract: Integrated circuits with clock distribution circuitry are provided. The clock distribution circuitry may include a clock source, a clock distribution network, a frequency encoder placed at the output of the clock source, and one or more frequency decoders placed at the destinations of the clock distribution network. The frequency encoder can be used to obtain calibrated delay settings proportional to a reference clock generated by the clock source. Each frequency decoder can be placed in a closed loop configuration and can use the calibrated delay settings to locally self-generate a recovered clock at the destination during a locked state. During the locked state, clock buffers in the clock distribution network can be powered down to save power.

Abstract: Circuitry formed of a two-dimensional regular array of capacitive elements 2 is coupled to decoding circuitry in the form of column decoder 8 and a row decoder 6. The decoders 8, 6 are used to select a start point and an end point within a sequence of selected capacitive elements to be connected in parallel following a horizontal raster scan arrangement. The selected capacitive elements may be used to generate an output voltage with a magnitude corresponding to the number of selected capacitive elements.

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.

Abstract: In an RF source, a digital waveform synthesizer comprises a computational module to synchronously determine a desired periodic function, f(?), within a first bandwidth portion, to which computational result there is combined an injected digital noise increment in an adjustable range of bounded amplitude, specifically selected to average over discontinuities of the DAC transfer characteristic. The combination is effected after passing the injected noise increment through a programmable digital filter forming a composite tuning word having a total bandwidth at a selected Nyquist zone and thence passing the composite tuning word through a truncation component to a DAC. The programmable digital filter is constructed to displace the spectral distribution of the injected noise increment to a portion of the total bandwidth remote from the first bandwidth portion.

Abstract: A method for managing information includes receiving bits of data, determining phasors for bits at only one frequency of a transmission spectrum, combining the phasors of bits that form a phasor having a spectral energy that lies within a predetermined range, and forming a codeword from the bits of the combined phasors.

Abstract: A method for delivering media content over a network includes transcoding the media content to generate multiple copies of the media content, each of the multiple copies having a different destination type or a different source type or both, storing the multiple copies in a cache, receiving requests for the media content, and selecting and delivering a copy of one of the multiple copies in response to each of the requests. A further method for providing media content transcoding services includes fetching media content, selecting one of multiple transcoders for transcoding from multiple source types to multiple destination types, wherein the one transcoder is selected based at least on the destination type, sending the media content to the selected transcoder, transcoding the media content to the destination type, thereby generating transcoded media content, and transmitting the transcoded media content.

Abstract: In one aspect, methods and systems for variable-block length encoding of data, such as an inverted index for a file are disclosed. These methods and systems provide for relatively fast encoding and decoding, while also providing for compact storage. Other aspects include a nearly 1:1 inverted index comprising a position vector and a data store, wherein values that have a unique location mapping are represented directly in the position vector, while for 1:n values (n>1), the position vector can include a pointer, and potentially some portion of information that would typically be stored in the data area, in order to fully use fixed width portions of the position vector (where a maximum pointer size is smaller than a maximum location identifier size).

Abstract: A method of decoding data that is encoded with a set of prefix codes begins by receiving the data at a computing device, and then compiling native machine code from the prefix code set for execution by a processing unit of the computing device. The machine code implements a binary tree of prefix codes that corresponds to the prefix code set. The data is decoded by traversing the prefix code tree, which is effected by executing the machine code with the processing unit.

Abstract: A coding method, a decoding method, a coder, and a decoder are disclosed herein. A coding method includes: obtaining the pulse distribution, on a track, of the pulses to be encoded on the track; determining a distribution identifier for identifying the pulse distribution according to the pulse distribution; and generating a coding index that includes the distribution identifier. A decoding method includes: receiving a coding index; obtaining a distribution identifier from the coding index, wherein the distribution identifier is configured to identify the pulse distribution, on a track, of the pulses to be encoded on the track; determining the pulse distribution, on a track, of all the pulses to be encoded on the track according to the distribution identifier; and reconstructing the pulse order on the track according to the pulse distribution.

Abstract: A decoding apparatus is disclosed. The decoding apparatus is applied to a data signal comprising a plurality of bits. A plurality of sampled data is generated by sampling the data signal. Each of the bits has a same cycle. The decoding apparatus comprises a calculating module and a determining module. When the calculating module sets a first interval and a second interval in the cycle of a specific bit, the calculating module generates a first count according to the sampled data in the first interval corresponding to a first logic level and generates a second count according to the sampled data in the second interval corresponding to a second logic level. The determining module determines a digital logic value of the specific bit.

Abstract: A method and apparatus for compressing data is described. In one embodiment, a processor receives one or more strings of data to be compressed. Duplicate strings are replaced with pointers using a first compression algorithm. An output of the first compression algorithm is processed with a second compression algorithm using a variable context dynamic encoder to generate a tree of non-overlapping bit-sequences where the length of each sequence is being inversely proportional of the likelihood of that symbol needing to be encoded. Unused symbols are not generated on the tree.

Abstract: An integrated circuit, such as a dynamic RAM, includes a plurality of terminals for coupling to signal lines. One of the signal lines is an input signal line that conveys a clock signal, and at least one other signal line is also an input signal line that conveys information that is encoded by a level of the at least one other signal line at n consecutive edge transitions of the clock signal, where n?2.

Abstract: A variable length decoder comprises: a first storage unit that stores encoded data; a variable length decoding unit; a second storage unit that stores coefficient data; a reverse quantizing unit; and a reverse DCT unit. The variable length decoding unit includes a control unit, a decoding unit, and an address generating unit. The second storage unit includes an initializing mechanism and is initialized all at once by the control unit in advance of decoding in a macro block unit. Only non-zero quantized data decoded by the decoding unit is stored in an address of the second storage unit generated by the address generating unit. The reverse quantizing unit reads and performs reverse quantization of the quantized data from the second storage unit, the reverse DCT unit performs reverse DCT, and then decoded data is acquired.

Abstract: A soft-output decoder that uses a-priori likelihood values to compute metrics while decoding a received data stream also uses the a-priori likelihood values to decide whether or not to compute the metrics for each position in the received data stream. Unnecessary computation can thereby be avoided, saving time and power. In an iterated soft-output decoding scheme, the soft-output decoder may decide whether or not to compute metrics for each position in the next iteration of the soft-output decoding process. These decisions may also be used to decide when to terminate the decoding process.

Abstract: A computer implemented method and system for selecting a string for serving as a reference string for a comparison scheme for compressing a set of strings calculates preliminary compression results for every string relative to an initial reference string, and uses the preliminary compression results to find a better reference string without additional compression tests. According to one embodiment, a histogram is calculated showing the number of occurrences of each compressed length for each string in the set plotted against the initial reference string and the better reference string has a length corresponding to an average compression length or center of gravity of the histogram.

Abstract: Waveform information is transmitted from the ends of a protection zone by first compressing the information using a lossy compression technique such as wavelets and then compressing the lossy compressed waveform information using a loss-less compression technique such as the Burrows-Wheeler transform. Status information is transmitted from the ends of the protection zone by compressing that information using the loss-less technique. The time for transmission can be less than, equal to or greater than the time for one cycle of the power line frequency.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.

Abstract: A thermometric-binary code conversion circuit 201 including an input unit 202 that outputs an encode input signal upon receiving a thermometric input signal. An encoder unit 204 outputs an encoded output signal upon receiving an encode input signal. An output unit 203 outputs a binary output signal upon receiving the encoded output signal. The encoder unit directly converts the code in accordance with a thermometric-binary code conversion equation expressed by Boolean algebra without forming intermediate code and without having dependence among bits of the binary output signal.

Abstract: An audio signal compression and decompression method and apparatus that provide lossless, realtime performance. The compression/decompression method and apparatus are based on an entropy encoding technique using multiple Huffman code tables. Uncompressed audio data samples are first processed by a prediction filter which generates prediction error samples. An optimum coding table is then selected from a number of different preselected tables which have been tailored to different probability density functions of the prediction error. For each frame of prediction error samples, an entropy encoder selects the one Huffman code table which will yield the shortest encoded representation of the frame of prediction error samples. The frame of prediction error samples is then encoded using the selected Huffman code table. A block structure for the compressed data and a decoder for reconstructing the original audio signal from the compressed data are also disclosed.

Abstract: A signal coding system capable of high efficiency, high quality signal coding is provided. Digital signals represented in the time domain are divided into set time interval data units and output. One output is converted to a digital signal represented in the frequency domain, and the other is output as-is. The energy dispersion of the digital signal represented in the frequency domain is compared with that of the digital signal represented in the time domain, and the digital signal having the least energy dispersion is coded. This coded digital signal is then multiplexed with an identification signal to identify it as a frequency domain or time domain signal, and the resulting multiplexed signal is output.

Abstract: A method whereby a database storage structure is created by selectively applying one or more data compaction methods to fields of a database. A specific compaction method is applied to a field if the field data characteristics satisfy criteria for that compaction method. The compaction methods used are: single-field encoding, where codes are substituted for data values in a field; multiple-field combining, where a single code is substituted for data values from two or more fields; pattern suppression, where recurring character patterns within data values are removed; numeric substitution, where binary values are substituted for numeric character data; and text compression, where codes are substituted for words and phrases in a text field. These compaction methods create compacted records which are reduced storage equivalents of the database records. Translation tables and auxiliary tables created by the compaction methods allow the compacted data to be retranslated into a user-readable format.

Abstract: A serial data decoding system is described in which a state machine (FIG. 5) is provided having a plurality of branching hierarchies of states, each branching hierarchy of states corresponding to a different decoding table. The state machine incorporates a memory 72 storing control data words (FIG. 7). A latch 74 stores the most recent control data word to be output from the memory. The memory 72 is addressed with a read address formed from a concatenation of the latched value 84, a table selecting word 86, Y/C and a received bit of serial data. When the state machine enters a state 88 corresponding to valid code, the current control data word is output as an identifier of that valid code.

Abstract: Data compression encoding and decoding circuitry which eliminates the need for decode circuitry that looks for the flux reversal points, or peaks, namely the peak detector and the phase-lock-loop circuitry combination. The encoding circuitry manipulates data by encoding data in a pulse position modulation (PPM) format such that ONE's (1's) in a data stream are delayed a first predetermined time period from the prior flux reversal (transition), and the ZERO's (0's) in the data stream are delayed a predetermined second time period from the previous transition. The encoder includes timing delay calibration circuitry that controls the time difference between transitions representing ONE's and ZERO's. The timing difference being controlled by a phase-lock loop (PLL)/precision crystal oscillator circuit combination that provides a reference delay for use by ASIC delay elements.

Abstract: Digitalized encoded audio signals for transmission over disturbed channels are composed of a series of information blocks made of information units containing various types of information, such as control information, scale factor information and information on encoded scanning values derived from partial-band and/or transformation coding at the source. The units of information concerning the encoded scanning values are allocated to a predetermined spectral structure. Before its transmission or storage, the encoded audio signal is subjected to a channel encoding dependent on the desired error protection. When errors are recognized, they are corrected, and when the errors cannot be corrected, they are concealed. For the channel encoding of the units of information concerning the encoded scanning values, a variable bit error protection is provided depending on the allocation of the individual information unit to a determined spectral structure, i.e.

Abstract: A thermometer-to-binary encoder includes a set of J input stage encoders E(1) through E(J) and an output encoder D, where J= 2.sup.K is an integer greater than 1. A set of digital input signals each representing a separate bit of a thermometer code T is grouped into J signal subsets representing further thermometer codes T(1) through T(J) providing inputs to a set of input stage encoders E(1) through E(J) respectively. Encoder E(J) produces an N-K+1 bit output binary code B(J) representing thermometer code T(J). Encoders E(1) through E(J-1) produce M-bit output binary codes G(1) through G(J-1), respectively, comprising the lower M bits of a binary code representing thermometer codes T(1) through T(J-1), respectively, where M is an integer greater than 1. Output encoder D processes codes G(1) through G(J-1) and B(J) to produce a set of digital output signals representing a binary code Y representing input thermometer code T.

Abstract: A transmitter pulse circuit produces two-phase pulse trains containing a certain number of pulse edges corresponding to an integral number represented by binary parallel bits of a data value to be transferred. The transmitter responds to a coordinate data value derived from a digitizer. The receiver includes a counter for counting pulse edges contained in the two-phase pulse trains, and a retrieving circuit for retrieving intermittently the counted contents to determine the number of received pulse edges. The counting circuit and the retrieving circuit constitute together a bus mouse interface of a host computer in the receiver. The coordinate data can be transferred to the host computer through the bus mouse interface without using a general RS-232C interface, thereby efficiently improving the host computer multiple terminal processing capacity.

Abstract: A circuit for inversely converting the signal of six bits converted by the 5B6B coding rule conversion method in the digital transmission into the original signal of five bits is described. On the occasion of inversely converting the 6-bit signal to the original 5-bit signal, the mark rate of the 6-bit signal to be converted inversely is detected in accordance with the 5B6B coding rule conversion pattern. In this case, all patterns of six bits are not detected but such six bits are divided into the upper three bits and lower three bits and the mark rates of six bits are detected from the patterns of upper three bits and lower three bits. Thereby, a number of detected patterns can be reduced and simplification of circuit structure can also be realized.

Abstract: A digital encoder (34) is partitioned into a plurality of rank ordered encoder circuits (36-39) which concurrently encodes least significant bits of an input signal from a first digital format to an output signal in a second digital format. Simultaneously, at least one bit of the input signal is used by a most significant bit encoder (42) to provide at least one most significant bit of the input signal in the second digital format. The at least one most significant bit is also used to select an output encoding of one of the plurality of rank ordered encoder circuits (36-39)as a remainder of the bits of the output signal in the second digital format.

Abstract: An apparatus and method, for use with a computer, for converting an uncompressed one-dimensional array of binary bits into a compressed binary bit string and/or for processing a Boolean operation on a first and a second compressed bit string. The first and second bit strings each contain one or more impulses. An impulse contains a run, which is a string of one or more bits of the same binary value, and an ending bit having a polarity opposite the polarity of the run. The impulses are encoded in one or more compressed impulse formats. Each compressed impulse format contains at least a first and a second indicator. The first indicator is for indicating the binary value of one or more same polarity bits of the run and the second indicator is for indicating the length of bits of the impulse. The length of bits is a quantity of the same polarity bits of the run and/or the ending bit having a polarity opposite the run.

Abstract: A method and apparatus for correcting errors in a thermometer code data array (32). A parallel A/D converter (22) comprises an array (26) of comparators and an encoder (30). The correction of errors in the data array (32) produced by the comparators (26) is accomplished by an array (24) of majority error correction gates which is placed between the array (26) of comparators and the encoder (30) in the A/D converter (22).

Abstract: A method for modulating binary data into a format suitable for encoding and decoding information, that employs a non-return-to-zero (NRZ) technique. The modulating method includes: defining within a recording medium an event-cell as the time between two adjacent clock transitions having a similar, unique characteristic; and, selectively writing to the recording medium within the event-cell, at an arbitrary time, either a first or a second information. The selective writing step includes generating a first event and a corresponding first read signal in response to a first information and generating a second event and a corresponding second read signal in response to the second information. The method can be employed for a first situation where the information transfer rate during the modulating process is well-regulated, and is advantageously employed for a second situation where the information transfer rate is dependent on unpredictable and variable transfer rate velocities and accelerations.

Abstract: An electrical circuit suitable for encoding binary information, in accordance with a novel modulation method, is provided. The encoder circuit includes: a clock driver; an n-phase counter driven by the clock driver for producing a succession of event-cells, wherein each event-cell is demarcated by a pair of similar, unique clock transitions; first logic circuitry for generating a first transitional event in a first event-cell in response to a first information; and second logic circuitry for generating a second transitional event in a second event-cell in response to a second information, the first transitional event and the second transitional event differing by the number of transitions occurring per event-cell. A specific, preferred encoder circuit embodiment is set forth.

Abstract: A single-step digital-to-analog converter includes a multiplicity of individual interconnected sources disposed in a matrix having matrix rows and matrix columns; a decoder apparatus connected to the matrix for addressing the individual sources, the decoder apparatus including a column decoder for addressing at least the more significant part of an n-bit-wide digital word to be converted and a row decoder in the form of a thermometer decoder.Logic apparatus is connected between the decoder apparatus and the matrix for determining the matrix column of one of the individual sources being addressed and for suppressing switching over of the individual sources of others of the columns. The logic apparatus includes first and second logic devices, the first logic device being connected between the column decoder and the matrix for deriving further column information (E.sub.i) and additional information (S.sub.i) from column information (X.sub.i) in accordance with the logical equations: E.sub.i =S.sub.i and S.sub.