Abstract: A MASH type sigma delta AD converter includes a modulator, an analog filter filtering an extraction signal obtained by extracting a probe signal and an quantization error generated in a quantizer within a sigma delta modulator, a low speed AD converter performing an AD conversion of an output signal of the analog filter, a first adaptive filter searching for a transfer function of the sigma delta modulator, a second adaptive filter searching for a transfer function from an output of the modulator to the low speed AD converter via the analog filter, and a noise cancellation circuit cancelling the probe signal and the quantization error included in an output signal of the quantizer using the search results by the first and second adaptive filters.

Abstract: The disclosed embodiments provide a system for processing data. During operation, the system obtains a group of two or more integer values. Next, the system sets, for each integer value in the two or more integer values, a delta encoding tag that represents a delta encoding of the integer value with respect to at least one other integer value in the group and uses a delta encoding state represented by the delta encoding tag to calculate an encoded value from the integer value. The system then encodes a length of the encoded value in a length tag for the integer value. Finally, the system replaces the integer value in the group with an encoded version containing the delta encoding tag, the length tag, and the encoded value.

Abstract: A data compression method based on sampling and estimation is provided. The method includes: receiving a piece of data; extracting N data regions from M data regions of the piece of data; examining a data redundancy ratio in the N data regions; and determining, according to a value of the data redundancy ratio, whether to compress the piece of data.

Abstract: Exemplary embodiments of the present disclosure are directed towards a system and methods employed for signal reception by providing programmable and switchable line terminations a universal serial bus physical layer. The system comprising at least one switching unit comprising at least two receiver pad units configured to provide programmable and switchable line terminations for signal reception in the universal serial bus physical layer. The switching unit further comprises at least one current mode logic switching unit interfaced with the receiver pad units. The system further comprises two pairs of receiver pads connected to the receiver pad units configured to receive a plurality of speed signals from at least four transmission units. The receiver pad units are enabled to route the plurality of speed signals to at least one input of a receive amplifier through the current mode logic switching unit.

Abstract: Circuitry for performing digital modulation is described. The circuitry includes a digital modulator. The digital modulator receives a first signal with a first duty cycle. The digital modulator also receives a second signal with a second duty cycle. The digital modulator further produces a monotonic multiplied modulated signal based on the first signal and the second signal.

Abstract: There is provided an encoder and decoder for encoding and decoding input data (D1, D2 or D3) to generate corresponding encoded output data (D2 or D3, D5). The encoder includes a data processing arrangement, optionally for analyzing a range of values present in the input data (D1) to determine at least one pre- and/or post-pedestal value, optionally to translate the input data (D1) using the at least one pre- and/or post-pedestal value to generate translated data, and then to apply a form of ODelta coding to the data, optionally translated data, to generate processed data, and to combine the processed data and optionally the at least one pre- and/or post-pedestal value for generating the encoded output data (D2 or D3). The decoder includes a data processing arrangement for processing the encoded data (D2 or D3), optionally to extract therefrom at least one pre- and/or post-pedestal value.

Abstract: Systems and methods of storing previously transmitted data and using it to reduce bandwidth usage and accelerate future communications are described. By using algorithms to identify long compression history matches, a network device may improve compression efficiently and speed. A network device may also use application specific parsing to improve the length and number of compression history matches. Further, by sharing compression histories and compression history indexes across multiple devices, devices can utilize data previously transmitted to other devices to compress network traffic. Any combination of the systems and methods may be used to efficiently find long matches to stored data, synchronize the storage of previously sent data, and share previously sent data among one or more other devices.

Abstract: In accordance with some embodiments of the present disclosure, a receiver may include a downconverter configured to demodulate a modulated wireless signal to produce a current-mode baseband signal and an analog-to-digital converter (ADC) configured to convert the current-mode baseband signal into a digital output signal. The downconverter may be coupled to the ADC without an intervening filter element.

Abstract: A method for encoding an input sequence of symbols to produce a bitstream and a method of decoding the bitstream to generate a reconstructed binary sequence. Encoding employs an encoding tree having primary codewords associated with leaf nodes and secondary codewords associated with internal nodes. A flush event may cause output of secondary codewords. A context model is used to select an encoding tree corresponding to an estimated probability at the encoder. The same context model is used by the decoder to select a decoding tree. The decoder interleaves bits from decoded bit sequences associated with different estimated probabilities based on the context model.

Abstract: In a method and device for encoding and/or decoding a sequence of discrete source values (Si) sub-groups (Gi) of a number of successive source values are taken from the sequence of source values. The sub-groups of source values are encoded into packets, comprising in each case an initial value (S1) corresponding to a first source value in a sub-group, a standardization factor (R) and difference values (?Si), standardized in accordance with the standardization factor, between values corresponding with other source values (Si) in the sub-group and in each case a value corresponding with a preceding source value (Si-1) in the sub-group. A standardization factor (R) is determined per packet subject to a greatest difference value (?max) within the sub-group between a source value and a preceding source value. The invention also relates to an information carrier provided with a thus encoded sequence of source values.

Abstract: A signal corresponding to a short-period change and a signal corresponding to a long-period change of a sound signal are detected, and optimal quantization is performed based on the combination of the two signals. In an ADPCM encoding apparatus (100), a differential value dn between a 16-bit input signal Xn and a decoded signal Yn-1 of one sample ago is calculated by a subtractor (102). Thereafter, the 16-bit differential value dn is adaptively quantized by an adaptive quantizing section (103), so as to be converted to a (1 to 8)-bit length-variable ADPCM value Dn. Thereafter, the ADPCM value Dn is compression-encoded by a compression-encoding section (108) to generate a signal D?n, and the signal D?n is framed by a framing section (130) and outputted. Further, in an ADPCM decoding apparatus, a framed input signal is subjected to a reverse of the aforesaid process so as to be decoded.

Abstract: A variable modulus sigma delta (??) modulator for a fractional-N frequency synthesizer in accordance with the present invention may include an integer division unit; a pulse-width modulation (PWM) generator, a ?? noise-shaping unit, a first input FRAC for receiving a first programmable integer, and a second input MOD for receiving a second input, wherein the integer division unit is configured to perform a translation from the first input and the second input into a first output FRAC? and a second output R, the PWM generator is configured to receive the second input MOD and the second output R, and generate a modulated pulse signal, and the ?? noise-shaping unit is configured to receive the first output and the modulated pulse signal, and generate a sequence whose average equals approximately the first input over the second input.

Abstract: Systems and methods for the encoding of data in a dataset, comprising the storage of the data in an i-th temporary code list (TCL(i)); generating an i-th folder (folder(i)) from the i-th temporary code list (TCL(i)) by replacing each value by an index that refers to the same value in a reference database; generating new temporary codes, using a predetermined formula F that always combines at least two values from the i-th folder (folder(i)), and placing thereof in an (i+1)-th temporary code list (TCL(i+1)); and the recursive repetition of actions b) and c) for subsequent values of i, so long as the (i+1)-th temporary code list (TCL(i+1)) or the (i+1)-th folder (Folder(i+1)) contains one or more values more than once.

Abstract: A circuit arrangement includes a first light emitting diode and a second light emitting diode emitting light of different colors arranged adjacent to each other for additive color mixing. A first and second controllable current sources are connected to the first and second light emitting diode, respectively, such that the load currents of the light emitting diodes depend on respective control signals received by the current sources. First and second sigma-delta modulators are connected to the first and second light emitting diodes, respectively, and provide bit-streams as control signals to the current sources. The mean value of each bit-stream corresponds to the value of an input signal of the respective sigma-delta modulator.

Abstract: Provided are a coefficient multiplier and digital delta-sigma modulator using the same. The coefficient multiplier has the average of output signals of respective dependent multipliers as an effective coefficient using a coefficient averaging technique without employing an adder that has a complex structure and occupies a large chip area. Accordingly, the coefficient multiplier has a simple hardware constitution and small chip area in comparison with a canonical signed digit (CSD) coefficient multiplier, and the digital delta-sigma modulator employing the coefficient multiplier has a simple structure and small size.

Abstract: Disclosed herein are devices, methods, and techniques including analog to digital converters having at least one digital filter.

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to a time-interleaved delta-sigma modulator are described. Other embodiments may be described and claimed.

Abstract: Implementations and embodiments of decoders, encoder/decoder systems and converters are depicted and described.

Abstract: A method for detecting the presence or absence of an audio signal in a communications system in which an audio signal is encoded by a delta modulation encoding algorithm, and in which a step size parameter is adapted according to characteristics of the encoded signal, the method comprising determining based on the magnitude of the step size parameter whether the encoded signal represents audio activity, and adapting the operation of the communication system based on that determination.

Abstract: A pulse modulator has a subtraction stage that produces a control error signal from the difference between a complex input signal and a feedback signal. A signal conversion stage converts the control error signal to a control signal. The control signal is multiplied by a complex mixing signal at the frequency ?0 in a first multiplication stage. At least one of the real and imaginary parts of the up-mixed control signal is then quantized by a quantization stage to produce a real pulsed signal. The pulsed signal is then employed to produce the feedback signal for the subtraction stage in a feedback unit. The pulse modulator according to the invention allows the range of reduced quantization noise to be shifted toward a desired operating frequency ?0.

Abstract: A denoising process or system uses convex optimization to determine characteristics of a clean signal. In one embodiment, a noisy signal that represents a set of symbols can be scanned to determine an empirical vector with components respectively indicating respective empirical probabilities of symbols in the noisy signal that occur in a particular context. A convex optimization process can then identify a vector such that a difference between the empirical vector and a product of the identified vector and a channel matrix is minimized. The identified vector can be used to determine when a symbol in the noisy signal should be replaced when assembling a reconstructed signal.

Abstract: Apparatus and method for processing signals. A sigma-delta modulator is used. An adaptive dynamic range controller is configured to adaptively adjust the dynamic range of a signal output from the sigma-delta modulator.

Abstract: A performance monitor device includes an input unit to input both of address information and event occurrence information, an address mask unit to determine an address area to which each piece of the inputted address information belongs, an execution frequency counter to count a number of times of execution of programs in the address areas, an execution frequency holding unit to hold a counting result of the number of times of execution, an event occurrence information counter to count the event occurrence information corresponding to the address areas having the counting result of the number of times of execution included within a predetermined number of highest ranks, a holding unit to hold a counting results of the event occurrence information, and a storing unit to store the counting result of the event occurrence information corresponding to the address area having the highest number of times of execution in predetermined periods.

Abstract: In a pulse width modulation method of the present invention, a digital signal is modulated and a pulse width modulation signal is generated in a pulse width modulator by using a digital signal output unit and the pulse width modulator The pulse width modulation method includes: outputting to the pulse width modulator a first value corresponding to the input signal as a first digital signal at a first timing by the digital signal output unit; determining a limited value range based on the first value by the digital signal output unit; determining a second value corresponding to a new input signal by the digital signal output unit; judging whether or not the second value is included in the limited value range, and when the second value being judged to be included, outputting the second value to the pulse width modulator as a second digital signal, and when the second value being judged not to be included, outputting a value included in the limited value range to the pulse width modulator as the second digital s

Abstract: Denoising such as discrete universal denoising (DUDE) that scans a noisy signal in an attempt to characterize probabilities of finding symbol values in a particular context in a clean signal can perform a rough denoising on the noisy signal and identify contexts from a roughly denoised signal. The rough denoising improves estimation of the statistical properties of the clean signal by reducing the false differentiation of contexts that noise can otherwise create. Statistical information regarding occurrences of symbols in the noisy signal and corresponding contexts in the roughly denoised signal can then be used to denoise the noisy signal. The specifics of the rough denoising can be chosen based on knowledge of the noise or of the clean data. Alternatively, the DUDE can be used in an iterative fashion where the denoised signal produced from a prior iteration provides the contexts for the next iteration.

Abstract: A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.

Abstract: Sigma-delta modulators and a method of modulating are disclosed in which a first sigma-delta modulator having a first quantizer is provided, and a second quantizer is also provided. At least a first node of the first sigma-delta modulator upstream of the first quantizer and a second node of the first sigma-delta modulator upstream of the first quantizer to the second quantizer are coupled together.

Abstract: By using a selector, an output of a delta sigma modulator having a quantizer for quantizing a signal is selectively supplied to one of a first D/A converter having a linear amplifier and a second D/A converter having a digital amplifier. Further, the number of quantization levels of the quantizer, the sampling frequency, or the order of a transfer function of the delta sigma modulator is selected by a control signal selector in conjunction with the selector. An output of the first D/A converter is supplied to a line terminal, while an output of the second D/A converter is supplied to a headphone terminal.

Abstract: A sigma-delta modulator is supplied with a data word and includes a first and at least one further modulation stage, each having at least two adders. The adders in the first modulation stage process a low-significance component and a delayed more significant component of the data word and provide a result word and a carry at their respective outputs. The adders in the at least one further modulation stage process a low-significance component and a more significant component of the result word and provide a further result word and a carry at their respective outputs. The low-significance component and the more significant component of the result word are provided to the further modulation stages with an unvarying delay. A bit stream is derived from a carry from final instances of the at least two adders in the first modulation stage and in the further modulation stage respectively.

Abstract: The invention is directed to a phase locked loop with a ?? modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ?? modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

Abstract: A device for performing predetermined processing on an input signal that may have a signal amplitude of more than one bit. The input signal is obtained by subjecting one-bit serial signals to predetermined signal processing, wherein the signal amplitude of more than one bit is converted to a one-bit serial signal by accumulating the signal amplitudes that exceed one bit, delaying the accumulated signal on the basis of the input signal, and outputting the accumulated signal.

Abstract: A digital signal processing system utilizes an internal filter of a delta-sigma modulator in a novel manner to implement both the integration functions of the delta-sigma modulator and a decimation function. Using the internal filter to combine integration and decimation functions can eliminate the need for a separate decimation filter. The combination of integration and decimation functions can also improve signal-to-noise ratio by improving low-pass filtering performance.

Abstract: An eight-channel PCM recorder is utilized for recording two channels of delta-sigma modulated audio signals. Employed to this end is a PCM adapter comprising a bit stream divider for dividing the bit streams of the delta-sigma modulated signals into series of sixteen-bit segments, and a reformatter for rearranging the bit segments into eight signals having a format in agreement with the format of the PCM signals normally handled by the PCM recorder. The eight reformatted delta-sigma signals are introduced into the PCM recorder thereby to be recorded in place of the eight channels of PCM signals.

Abstract: Methods and apparatuses for encoding speech signals in the presence of interference that accurately establishes a speech signal value subsequent to lost transmission packets. For one embodiment of the present invention, the initial bits of a speech transmission packet are encoded using a PCM encoding scheme and the remaining bits are encoded using a CVSD encoding scheme. Upon encoding, the initial bits of each packet, the instantaneous value of the voltage as derived from CVSD coder/decoder at the transmitter is encoded using PCM coding rather than CVSD coding. At the receiver, each packet is decoded independently using the PCM-encoded bits, rather than the terminal value of a preceding packet, to define a starting value. The PCM encoded bits of a valid packet are used to reestablish the signal value, thus avoiding packet-to-packet error extension in the presence of burst interference.

Abstract: An apparatus for processing a digital signal that generates a one-bit output signal using a delta-sigma modulation apparatus, which includes a quantizer for quantizing an integrated output of a sixth integrator to generate a one-bit output signal that is send to respective integrators through an adder under feedback processing to output the one-bit output signal to the outside of a six-order Delta-sigma modulator, and a control unit for generating a control signal that controls the feedback loop signal from the quantizer so as to change the signal level of a signal component of the audio frequency band of the one-bit output signal. The control unit receives an integrated output from a second integrator being an input side integrator of the six-order delta-sigma modulator.

Abstract: In an encoding apparatus, when difference value between adjacent quantization units of quantization accuracy information where, e.g., distribution range is 0˜7, e.g., if difference value is 3 or more, 8 is subtracted, and if difference value is less than ?4, 8 is added to thereby transform two difference values where difference therebetween is 8 into the same value. Thus, the distribution range of difference value becomes ?4˜3, and size of code book (table) can be held down to the same size in the case where difference is not taken. In addition, high order 1 bit of difference value may be masked to carry out replacement into value consisting of only low order 3 bits, thus also making it possible to prevent increase in size of code book (table).

Abstract: In a filter circuit of the present invention, a partial quantization value is computed by a quantization circuit according to a spread code and others in a unit at an arbitrary stage, where an integrating value is increased. The partial quantization value is successively added by an adder formed by a counter and is transmitted to a unit of the following stage. In an adder of the following stage, an analog residual is computed by subtracting an analog converted value of the partial quantization value, that is obtained by a D/A converter, from the integrating value so as to suppress an increase in the analog cumulative value. With this arrangement, the cumulative value is increased according to an increase in the number of taps, so that an analog adder can reduce power consumption, which is caused by expansion of a dynamic range at the following stage.

Abstract: A self-adaptable data compression technique includes compressing the digital data points of a waveform according to at least a first protocol and a second protocol, and various comparing the compressed data under various protocols to determine which would require the least memory for storage.

Abstract: Processing signals to record media information includes receiving an analog signal at an analog-to-digital converter, where the analog signal includes media information. The analog-to-digital converter converts the analog signal to a corresponding digital signal, where the digital signal includes a first sequence having a first number of bits. A sigma-delta converter processes the digital signal according to a sigma-delta conversion, where the processed digital signal includes a second sequence having a second number of bits, and where the second number of bits is lower than the first number of bits. The processed digital signal is stored in a digital format in a medium in order to record the media information.

Abstract: Signal conversion is implemented employing a memory system operating as a look-up table that stores a plurality of sets of output samples associated with each of a plurality of respective input samples. The look-up table thus can generate a corresponding set of output samples in response to a given input sample, thereby emulating desired digital upsampling and delta-sigma modulation. The output samples can be aggregated, such as by multiplexing, to provide an output data stream at a desired sample rate.

Abstract: Processing signals to record media information includes receiving an analog signal at an analog-to-digital converter, where the analog signal includes media information. The analog-to-digital converter converts the analog signal to a corresponding digital signal, where the digital signal includes a first sequence having a first number of bits. A sigma-delta converter processes the digital signal according to a sigma-delta conversion, where the processed digital signal includes a second sequence having a second number of bits, and where the second number of bits is lower than the first number of bits. The processed digital signal is stored in a digital format in a medium in order to record the media information.

Abstract: An apparatus for processing a digital signal that generates a one-bit output signal using a &Dgr;&Sgr; modulation apparatus, which includes a quantizer for quantizing an integrated output of a sixth integrator to generate a one-bit output signal that is sent to respective integrators through an adder under feedback processing to output the one-bit output signal to the outside of a six-order &Dgr;&Sgr; modulator, and a control unit for generating a control signal that controls the feedback loop signal from the quantizer so as to change the signal level of a signal component of the audio frequency band of the one-bit output signal. The control unit receives an integrated output from a second integrator being an input side integrator of the six-order &Dgr;&Sgr; modulator.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels.

Abstract: A computer implemented method and system for selecting a string for serving as a reference string for a comparison scheme for compressing a set of strings calculates preliminary compression results for every string relative to an initial reference string, and uses the preliminary compression results to find a better reference string without additional compression tests. According to one embodiment, a histogram is calculated showing the number of occurrences of each compressed length for each string in the set plotted against the initial reference string and the better reference string has a length corresponding to an average compression length or center of gravity of the histogram.

Abstract: An adaptive sigma delta modulator has an input stage, a conventional sigma delta modulator, and adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal and an adaptive signal, the amplitude of the analog input signal being in a first range [−a+a]. The conventional sigma delta modulator produces an intermediate digital output sequence representative of the difference signal, the amplitude of the intermediate digital output sequence being in a second range [−b+b], wherein b<a. The adaptation stage produces the adaptive feedback signal such that the amplitude of the adaptive signal keeps the difference signal within the second range [−b+b].

Abstract: A digital to digital Sigma-Delta modulator comprises an input which receives a digital input value encoded over N bits, an output which delivers a digital output value encoded over n bits, where n is less than N, and at least a first Sigma-Delta cell which includes a quantizer having a quantization interval which is a prime number. The choice of a prime number decreases the power of the limit cycles (lines with a power value higher than the local mean value) which may appear depending on the input code of the modulator and on the initial conditions. Application is proposed to a digital frequency synthesizer.

Abstract: A transmitting apparatus and a reproducing apparatus include a converter for converting an input one-bit digital signal into a multi-bit signal while effecting down-sampling of a sampling frequency. A one-bit digital signal that could develop an overflow (clip) depending on its modulation degree is attenuated at a stage upstream of the input of the converter, and the multi-bit signal is amplified at a stage downstream of the converter to avert a clipped state between the stages.

Abstract: A multi-mode interface circuit for coupling a delta sigma modulator (24) to a processor includes a decoder 20 for decoding mode selection inputs to produce a plurality of control signals controlling an oscillator and a plurality of multiplexers. The oscillator is enabled to produce a first clock signal (INTCLK). The first clock signal or an external clock signal (EXTCLK) is multiplexed as a second clock signal (40) to the input of a code generator circuit (23), causing it to generate a clock input signal (MCLK) applied the delta sigma modulator, third and fourth clock signals (41, 42), and a phase-shift-modulated signal (43) in response to both the second clock signal and a 1-bit data signal (MDAT) produced by the delta sigma modulator. One of the third and fourth clock signals and a ground signal is multiplexed to a clock conductor (13). The phase-shift-modulated signal or the 1-bit data signal is multiplexed onto a data output conductor (14).

Abstract: The invention relates to a circuit configuration for quantization of digital signals and for filtering quantization noise. Said circuit configuration comprises a multitude of digital control loops connected in series and having quantizers. The digital signals having a word length of m-bits are fed to a first control loop in the series. The quantization error signal of each quantizer is filtered and fed back to the corresponding digital control loop. It is then fed to a downstream digital control loop. The quantized output signal of the first digital control loop is adapted to a third word length of u-bits which is smaller than the first word length. Except for the quantized output signal of the first digital control loop, the quantized output signals of the digital control loops of the series are respectively filtered by a digital filter.

Abstract: A data processing apparatus includes an input terminal for receiving an audio signal, a 1-bit A/D converter for A/D converting the audio signal into a 1-bit bitstream signal, and a prediction unit for carrying out a prediction step on the bitstream signal so as to obtain a predicted bitstream signal. The data processing apparatus further includes a signal combination unit for combining the bitstream signal and the predicted bitstream signal so as to obtain a residue bitstream signal. A recording apparatus or a transmitter apparatus can use the data processing apparatus. The residue bitstream signal is data compressed by lossless encoding and then error encoded and channel encoded prior to transmission through a media.