Abstract: Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output.

Abstract: AN LED driving apparatus includes a power stage circuit and a dimming control circuit. The power stage circuit drives an LED circuit. The dimming control circuit includes a duty ratio conversion circuit, a digital-to analog conversion (DAC) circuit, an error amplifier (EA) circuit and a modulation control circuit. The duty ratio conversion circuit converts a PWM dimming signal to a digital duty ratio signal. The DAC circuit converts the digital duty ratio signal to an analog reference signal. The EA circuit generates an error amplified signal according to a difference between the analog reference signal and an output current related signal. The modulation control circuit generates a PWM control signal according to the error amplified signal, to control the power switch, such that the output current relates to a dimming duty ratio, whereby the dimming control circuit dims the LED circuit according to the PWM dimming signal.

Abstract: A method for providing an automatically reconfigurable input interface includes analyzing input received through an input interface of the computing device, determining a context based on the input; and reconfiguring the input interface to comprise a key based on a domain associated with the context. A computing system for providing automatic reconfiguration of an input interface includes a processor and a memory communicatively coupled to the processor. The processor is configured to analyze input received through an input interface of a computing device, determine a context based on the input, and reconfigure the input interface to comprise a key based on a domain associated with the context.

Abstract: Provided is an eigendecomposition cipher. Input data is formatted into a numerical representation and arranged as a data matrix. Eigendecomposition is performed on the data matrix to determine at least a first component matrix (of eigenvalues) and a second component matrix (of eigenvectors). The eigendecomposition process is modified to ensure that the first component matrix has a diagonalized matrix of eigenvalues. Provided are additional features of shaping, compression, and message generation for an eigendecomposition-based cipher. A first message is generated based upon the first component matrix. A second message is generated based upon the second component matrix. The first and second messages comprise separate indecipherable parts of the input data. The first and second messages may be transmitted or stored separately such that the source data may not be recovered without both messages.

Abstract: An access control system includes: a lock control apparatus, an authentication terminal and a terminal to be authenticated; said authentication terminal sends own identity information to the lock control apparatus to be authenticated, and generates a random authorization code after receiving an authentication passing message responded by said lock control apparatus, and sends it to said terminal to be authenticated and lock control apparatus respectively; said lock control apparatus stores the identity information of a legal user, and authenticates the identity information sent by said authentication terminal, and responds said authentication passing message after passing authentication; and the lock control apparatus interworks with said terminal to be authenticated after receiving said random authorization code, and if judging that both of the random authorization codes are consistent, then unlocks; said terminal to be authenticated stores a received random authorization code, and interworks said random aut

Abstract: A size comparison unit reports, to an access control unit, the size of a piece of compressed data having the smallest size from among pieces of compressed data generated via compression processing units compressing blocks, an algorithm name representing a compression processing unit that has generated the piece of compressed data having the smallest size; the access control unit selects a piece of compressed data to be written in a tape medium and reports, to a statistical information processing unit, an algorithm name representing a compression processing unit that has generated this selected piece of compressed data; the statistical information processing unit extracts, from the reported algorithm name, a regularity present in a result of the selection of compressed data and, in accordance with this extracted regularity, specifies and stops a compression processing unit to be stopped.

Abstract: A method comprising receiving a syntax element to be encoded as a code word of a set of code words, determining a mapping between the syntax element and the code word on the basis of a hierarchy level in a tree structure, using the mapping to obtain the code word, and updating the mapping is disclosed.

Abstract: A method for parallel context modeling through reordering the bits of an input sequence to form groups of bits in accordance with a context model-specific reordering schedule. The reordering schedule is developed such that the groups of bits are formed to satisfy two conditions: first, that the context for each of the bits in a group of bits is different from the context of each of the other bits in that group, and the context of each of the bits in that group is determined independently from each of the other bits in that group. The parallel context modeling may be used in encoding or decoding operations.

Abstract: A method for storing node information of a Huffman tree. The method creates an index of each node in the Huffman tree using a breadth first search (BFS) algorithm. The method further reads each node of the Huffman tree beginning from a root node according to a sequence of the index of each node, and stores node information of each node into an array of the Huffman tree.

Abstract: A data redundancy elimination system. In particular implementations, a method includes accessing a data block; dividing the data block into a plurality of data chunks; computing chunk signatures for the plurality of data chunks; identifying a plurality of anchor chunks in the plurality of data chunks; accessing a second memory to identify one or more matching chunk signatures; reading one or more signature blocks corresponding to the matching chunk signatures from a first memory into the signature block search space of the second memory; and matching one or more computed chunk signatures to chunk signatures of the one or more signature blocks in the signature block search space.

Abstract: A finite-state network that supports substring-number mapping is compiled from a grammar that includes a plurality of classes of substrings. Each of the plurality of classes of substrings has a finite number of substrings. In applying the network to an input string, substrings are identified in the input string. Some or all of the substrings identified in the input string are mapped to a unique index within their class. This unique index is labeled with an identifier that identifies its class to define a labeled index. The string is encoded by forming a set of labeled indices using the labeled index of each substring of the input string.

Abstract: An encoder includes a first storage array having a first set of values, a second storage array having a second set of values, and a selection circuit. Each of the first and second storage arrays have address ports coupled to receive a first or second portion of an input value, and are adapted to output a first or second value of the first or second set in response to a value of the first or second portion of the input value, respectively. The selection circuit has input ports coupled to the first storage array, to the second storage array, and for receiving the input value. The selection circuit is adapted to output the second value from the second storage array as an encoded value of the input value or the first value from the first storage array as the encoded value.

Abstract: An input/output (I/O) circuit bank is disclosed, in accordance with one embodiment, having programmable I/O circuits configurable to support I/O interface standards for single-ended and differential signaling. The associated pads of one or more of the I/O circuits may be utilized to provide an external reference signal via a pass transistor onto an internal bus for use by the remainder of the I/O circuits. The pass transistors may be designed to function as lowpass filters to limit the amount of noise that passes through them.

Abstract: An addressing device selects an element from a set of N≦2K regular elements or alternatively from a set of R<N redundant elements in dependence on a K-bit input address which is applied to a 1-out-of-N decoder, and which addresses the regular elements. For each redundant element, a bypass circuit is provided and has in each case a reference bit transmitter for supplying K reference bits that are programmable by selective destruction or by selective introduction of conductive links in order to set a comparison device to the identification of a selected address. If the relevant address is identified, the bypass circuit addresses the redundant element assigned to it while switching off the 1-out-of-N decoder, provided that it is sensitized. For its sensitization, each bi-stable-circuit checks M<K preselected specimens of the reference bits in order to set the relevant bypass circuit into an active state if the binary values of these reference bits differ from a chosen bit combination.

Abstract: A method of automatically generating and verifying programmable logic controller (PLC) code. The method includes the steps of constructing a neutral control model file, determining whether the neutral control model file is correct, generating PLC code if the neutral control model file is correct, verifying whether the PLC code is correct, and using the PLC code to build a tool.

Abstract: A programmable logic device makes better use of its I/O terminals (for example, package pins) by both amplitude and phase encoding a stream of multi-bit digital values into a single DATA signal. Information in the DATA signal is encoded into four different voltage levels and four different phases. The DATA signal is communicated from the FPGA via just one I/O terminal, as opposed to many I/O terminals. An amplitude/phase encoder is described that includes a delay line in a delay-locked loop, as well as two other delay lines that are slaved to the delay line of the delay-locked loop. The slaved delay lines are used to phase encode the information into the DATA signal. An amplitude/phase decoder is also described that enables the programmable logic device to receive and decode such a DATA signal. The amplitude/phase decoder includes a delay line in a delay-locked loop, as well as two other delay lines that are slaved to the delay line of the delay-locked loop.

Abstract: A programmable video interface (20) eliminates the need for select-in-test parts during manufacture. The video interface (20) includes a scaling module (40) and a programming module (60). The scaling module (40) converts an analog input signal into a digital output signal based on a plurality of analog programming signals. The programming module (60) generates the plurality of analog programming signals, where the analog programming signals maintain operation of the scaling module at a predetermined transfer characteristic and an associated tolerance. The programming module generates the plurality of analog programming signals based on digital programming data. The use of D/A converters (62, 64) in the programming module (60) allows the elimination of resistor divider networks and associated tolerance problems.

Abstract: The bits comprising a computer data structure are reversed rapidly and efficiently using a combination of data partitioning and table look ups. In an exemplary embodiment, the invention is employed in the pre-processing of Advanced Configuration and Power Interface (ACPI) tables stored in little-endian format for use by a big-endian operating system.

Abstract: The present invention offers a method and a circuit for generating codes enabling transmission of long-codes to start on a reverse channel in a shorter waiting time. The method involves corresponding a shift quantity between the beginning of a sequence M or long-codes cycle, and each timing to a combination of a plurality of masking data; determining a combination of masking data for timing to start generation of long-codes in response to a transmission request at a point of time as soon as possible; and shifting of an initial value of a vector according to the masking data.

Abstract: The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.

Abstract: A data processor is provided to increase the number of instructions it can handle, even with a large number of operands required for the instructions. The data processor comprises a decoding circuit (1) extracting bits (a1, a2) of an instruction as first operand fields and decoding an operation code, using the remaining bits (a4); an operand-field storage portion (3) including a first operand-field storage portion (3a) storing bits (a1, a2) obtained from the decoding circuit (1) via a selector (2), and a second operand-field storage portion (3b) storing a second operand field obtained on the basis of those bits (a2); and a data processing portion (5) receiving the first and the second operand fields from the operand-field storage portion (3) and processing data in registers designated by the first and the second operand fields.

Abstract: A system and method for decoding telecommunication tracer information originating from any telecommunication network element and utilizing any commercial or proprietary telecommunication protocol. The system includes a storage repository for storing trace data that includes a plurality of individual events provided by a telecommunications network element that utilizes one or more telecommunications protocol. An encoder creates and stores a plurality of executable programs used to decode the trace data. A decoder engine receives trace data from the storage repository, determines the telecommunication protocol or protocols associated with the trace data, and invokes one or more executable programs stored in the catalog encoder subsystem to decode the trace data. A graphical user interface that receives an output from said decoder engine and displays the decoded results.

Abstract: The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.

Abstract: The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.

Abstract: A message processing device for sending and receiving a message composed of one or more elements between different kinds of devices including a parse tree holding unit having a function of holding a parse tree generated from syntax descriptions which define structure of a message sent or received, a parse tree scanning unit connected to the parse tree holding unit and having a function of scanning the parse tree as message data to be processed is applied, encoding and decoding a value and outputting encoded and decoded values, a preamble processing unit connected to the parse tree scanning unit and having a function of processing a preamble field of a message for use in indicating whether an element exists or not in the message data sent or received, and an index processing unit connected to the parse tree scanning unit and having a function of processing an index field of a message for use in indicating what number of element is selected in the message data whose one of a plurality of elements is selected to

Abstract: A programmable numeric converter (10) converts a floating point number to a fixed point format by selecting the proper offset. The mantissa is loaded with an implied value one into the least significant, or most significant, bits of the shifter (20). The programmable offset is added (24) to the exponent to determine the number of shifts to the mantissa bits. The number of bits of resolution necessary in the fixed point number is reduced because the offset can be programmed to move the decimal point to the left, or to the right, to provide accuracy wherever the significant digits are located. That is, the decimal point is moved left to provide more resolution in the fractional portion of the fixed point number for small numbers. Alternately, the decimal point is moved right to provide more resolution in the whole number portion of the fixed point number for large numbers.

Abstract: A method for testing protocol converters is presented, which permits the achievement of a test of all commands, independently of a corresponding test system. A modified protocol converter itself is used for the test. With the help of this method, a test for conversion of data structures can be carried out, of a slow protocol into the corresponding data structures of a fast protocol in the original speed.

Abstract: An apparatus and a method for receiving television signals can display a television signal of a novel signal format, even at a low cost, without addition of any hardware.

Abstract: A Viterbi decoder includes a branch metric generator, a subset maximum likelihood estimator, an accumulator switch circuit (ACS circuit), a most likely path setter, a first selector, and a path-memory circuit for the purpose of estimating encoding bits of a 4-bit error-correcting encoded information symbol string. The Viterbi decoder also includes a noncoding bit detector, eight j-level shift registers, and a second selector for the purpose of estimating a noncoding bit of the 4-bit error-correcting encoded information symbol string. The j-level shift registers are provided for temporarily holding the output signals of the noncoding bit detector. The second selector is provided for selecting one output signal from the output signals of the j-level shift registers in accordance with the output signal of the selector.

Abstract: A data input/output circuit includes a 32-bit reversible shift register (1) which includes four 8-bit reversible shift registers (2-5). Input gate circuits (6, 7) selectively apply data being inputted in a bit-serial fashion from an external to the 8-bit reversible shift registers (3, 4), and output gate circuits (8-12) selectively output data being stored in arbitrary stages of the 32-bit reversible shift register (1) in a bit-serial fashion. Input latches (13-15) and output latches (16-18) each of which is an 8-bit latch are connected to the respective 8-bit reversible shift registers (2-4) and a data bus (19). The input latches (13-15) hold the data being stored in the 8-bit reversible shift registers (2-4) and send the same onto the data bus (19) in a bit-parallel fashion, and the output latches (16-18) hold the data being sent from the data bus (19) and preset the same into the 8-bit reversible shift registers (2-4) in a bit-parallel fashion.

Abstract: This invention encodes information (such as the field values of a database record, or the words of a text document) so that the original information may be efficiently searched by a computer. An information object is encoded into a small "signature" or codeword using a method. A base or "leaf" signature S1 34 is computed by a known technique such as hashing. The logical intersection (AND) of each possible combination of pairs of bits of the base signature is computed, and the result is stored as one bit of a longer combinatorial signature CS1 42. The bit-wise logical union (bit-OR) of the combinatorial signatures of a group of records produces a second-level combinatorial signature CS2 52 representing particular field values present among those records. Higher-level combinatorial signatures CS3 60, CS4, etc. are computed similarly.

Abstract: A signal processor which is specially adapted for decoding sequential codes, including trellis codes, convolutional codes and detecting signals in partial response channels. The processor has three units, a branch metric generator unit, an add-compare-select unit and a survivor-trace and decoding unit, each of which is independently programmable. A central control unit synchronizes operations between the units at the received symbol rate. Between synchronizations, each of the units operate concurrently and independently of the others.

Abstract: A method structure for the compression of data utilizes an encoder which effects a transform with the aid of a coding neural network, and a decoder which includes a matched decoding neural network with effects almost the inverse transform of the encoder. The method puts in competition M coding neural networks (30.sub.1 to 30.sub.M) wherein M>1 positioned at the transmission end which effects a same type of transform and the encoded data of one of which are transmitted, after selection (32, 33) at a given instant, towards a matched decoding neural network which forms part of a set of several matched neural networks (60.sub.1 to 60.sub.Q) provided at the receiver end. Learning is effected on the basis of predetermined samples. The encoder may comprise, in addition to the coding neural network (30.sub.1 to 30.sub.M), a matched decoding neural network (35.sub.1 to 35.sub.M) so as to effect the selection (32, 33) of the best coding neural network in accordance with an error criterion.

Abstract: A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme is accessible from outside the physical package(s) in which the functional unit is housed. The data order conversion unit may comprise a load aligner and/or a store aligner, one or both of which may comprise means for shifting informational units of a smaller size within informational units of a larger size. The shift amount may derive from the low order address bits and may be altered depending on the external data ordering means selected.

Abstract: Programmable transcoding device which sequences of binary words of variable lengths corresponding to strings of characters in a first alphabet are transcoded into other sequences of binary words intelligible in a second alphabet. The device is connected to digital systems exchanging sequences of words via interfaces provided with files. A CPU connected to the interfaces via a switching device receives the incoming sequences, and delivers transcoded outgoing sequences of binary words. An exchange management unit monitors the data transfers in the device and regulates the flows of words between the device and the digital systems. A terminal or microcomputer can also equip the device so as to produce transcoding tables to be downloaded in an RAM of the CPU.