Abstract: Interleaver for scrambling an information word, the information word having a multitude of digits, for obtaining a permuted information word. The interleaver includes a first interleaver stage for a row-by-row arranging of the digits of the information word in a plurality of first rows and first columns, and a second interleaver stage for scrambling the digits of one of the first rows by interchanging at least two digits of the one first row in order to obtain a first scrambled row, and for replacing the one of the first rows by the first scrambled row. The first interleaver stage is configured for reading the first row, which is replaced based on the first scrambled row, in a column-by-column manner in order to obtain the permuted information word.

Abstract: Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes at least a first detector, a second detector, a decoder, and a queuing buffer. The first detector is operable to perform a data detection on an input data set at a first time. The decoder receives a derivation of an output from the first detector and performs a decoding process. Where the decoding process fails to converge, the decoder output is passed to the second detector for a subsequent detection and decoding process at a second time.

Abstract: A MIMO wireless system includes a transmitter that has a transmitter having a parser that parses a bit stream into multiple spatial data streams and multiple interleavers corresponding to the multiple spatial data streams, where each interleaver interleaves the bits in the corresponding spatial data stream by performing multiple column rotation to increase diversity of the wireless system. The MIMO wireless system also includes a receiver that has deinterleavers that deinterleaves spatial bit streams transmitted by the transmitter.

Abstract: Embodiments of our invention describe the method for producing forbidden pattern free (FPF) codewords using an encoder-decoder (CODEC). First, the method encodes a dataword to produce a FPF codeword by mapping dataword to a Fibonacci Numeral System space. Further, the FPF codeword is transmitted via adjacent lines of a bus and decoded when received from the bus to recover the dataword to eliminate all crosstalk on the bus.

Abstract: A trace receiver with multiple recording interfaces may be used to record the same input. The historical control point for starting and stopping trace recording is placed very near the front end. A new control point further from the front end allows the front end to continue operation while data is either presented to the memory interface for storage or discarded.

Abstract: A trace receiver with multiple recording interfaces is used to record the same input. This configuration may provide multiple recording interfaces and multiple recording channels. The recording channels may be in a single unit or in multiple units. Separate out of phase clocks may be used to time division multiplex data to be recorded.

Abstract: An apparatus and method of multi-stage network for iterative network are disclosed. The apparatus has M stages, and each stage uses N multiplexers to transmit N codeword partitions simultaneously. Every starting terminal, either the output port of memories, soft-in soft-out decoders, or multiplexers, has two paths to couple with two different multiplexers at next stage. One path connects the source to the first data port of one multiplexer; the other connects the source to the second data port of another multiplexer. The two multiplexers will be controlled with the same 1-bit signal, so each source has only one valid path to next stage. The invention can guarantee that the transmission of N data blocks is free from contention.

Abstract: Embodiments described herein may include example embodiments of a method, article and/or apparatus for coding data which may be used for communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system, and/or for communication between computing platforms via a network or other interconnection medium.

Abstract: A means for avoiding hash collisions by means of message pre-processing function to increase randomness and reduce redundancy of an input message whereby hash collisions are avoided when it is applied before hashing any message and the message pre-processing function comprises 4 steps like shuffling of bits, compression T-function and LFSR which steps increase the entropy of the input message at the end of 4 rounds, the output becomes more random.

Abstract: A block interleaving apparatus for block interleaving M-bit input streams to be transferred with a modulus k using a mixed radix system in a multi-band orthogonal frequency division multiplexing communication system, including an array processor having an array including M cells in which the number of columns is k and the number of rows is M/k. The array processor inputs the input streams from the bottom-right cell up to the top-left last cell in the horizontal direction, and, after the first bit of the input streams reaches the last cell, generates interleaved output streams by changing the output of the array processor from horizontal direction to vertical direction.

Abstract: A decoder comprising a decoding element arranged to operate in a first mode for decoding a turbo encoded data stream and in a second mode for decoding a viterbi encoded data stream, wherein the decoding element is responsive to a first control signal for switching from the first mode to the second mode during decoding of a turbo code block and responsive to a second control signal for switching from the second mode to the first mode to allow continued decoding of the turbo code block.

Abstract: The invention relates to a method for the compression of data comprising values to be coded, in particular grey values or prediction errors using a run-length coding. A bit sequence of a bit plane which represents at least one item of partial information of at least one value to be coded is thereby coded coherently. This method is particularly used in connection with medical image data.

Abstract: An interwoven spreading code is formed by a stretched spreading code series at a first frequency and a mirror of the stretched spreading code series at a second frequency. The interwoven spreading code can be used to spread a baseband signal. Data can be recovered through correlation of a received signal with the interwoven spreading code. The spreading code used in forming the interwoven spreading code can be a Barker code.

Abstract: An interleaver/de-interleaver that may be used for multiple interleaving algorithms and look up tables (LUTs) of one or more interleaving standards. In at least some embodiments, the interleaver/de-interleaver may comprise an initial value selector, offset selector, and a pruning adjuster coupled to a combining block. The interleaver/de-interleaver may further comprise a boundary regulator coupled to the combining block, wherein the boundary regulator is configurable to modify an output of the combining block according to one or more pre-determined rules. The interleaver/de-interleaver may further comprise a controller coupled to, at least, the initial value selector, the offset value selector, and the offset adjuster, whereby the interleaver/de-interleaver may be used to interleave or de-interleave a block of data in accordance with a plurality of interleaving algorithms.

Abstract: Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

Abstract: A method and apparatus for deshuffling received shuffled data in a communication system supporting multi-level modulation. A transmitter encodes information bits and shuffles code symbols so that systematic symbols having a relatively high priority are disposed at high-transmission reliability positions and parity symbols having a relatively low priority are disposed at low-transmission reliability positions in a modulation symbol. A receiver demodulates received data and outputs a modulation symbol having a plurality of code symbols, stores the code symbols separately as systematic symbols and parity symbols in corresponding memory areas according to a deshuffling order corresponding to the shuffling, reads the stored code symbols, decodes the stored code symbols at a predetermined code rate, and thus outputs an packet.

Abstract: A bit interleaver and a bit interleaving method are provided. The bit interleaver includes delay devices which are applied with symbol interleaving and tone interleaving, and delay a bit stream output from a memory, to generate a delayed bit stream; a first multiplexer (MUX) unit which selects any one of a bit of the bit stream output from the memory and a bit of the delayed bit stream, to generate a selection bit stream; and a second MUX unit which changes an order of the selection bit stream to generate an output bit stream. Accordingly, it is possible to easily and effectively perform bit interleaving including a cyclic shift.

Abstract: A diversity code transmission system is disclosed. The diversity code transmission system comprises an encoder encoding a set of bits. The system also comprises an interleaver receiving the encoded bits and providing an output. A coder or modulator for providing a first transmission signal is also used. The interleaver iteratively receives its own output to provide an iterated output to a coder or modulator to provide a diversity transmission signal. The receiving system supports iterative decoding and joint iterative demodulation and decoding.

Abstract: A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.

Abstract: Disclosed is a method for generating codewords through a repetition having a number of repetitions by means of multiple code symbols generated by a mother code and included in a slot. The method including the steps of generating the code symbols through a channel coding for input information symbols, and mapping the code symbols so that copies generated by the repetition are located within a bit sequence in an order different from an order of the code symbols in a bit sequence before the repetition, and performing the repetition.

Abstract: A buffer structure for storing symbols received via a number of (e.g., physical or transport) channels. Each channel is associated with a particular time interval (e.g., a radio frame period or a transmission time interval (TTI)) over which the received symbols are processed (e.g., interleaved). The buffer structure includes a buffer and an address generator. The buffer is partitioned into a number of sections. One section is assigned to each channel being processed. Each section can be operated as a circular buffer. The address generator provides addresses for writing symbols to the assigned sections. If the buffer structure is used for the transport channels, the sections can be assigned to the transport channels based on the associated TTIs (e.g., in descending order of TTIs). For each coded composite transport channel (CCTrCH), the transport channels in the CCTrCH can be assigned to sections defined starting from a respective initial location (e.g.

Abstract: An arrangement for generating addresses for interleaving/de-interleaving sequences (X1, X2, X3, . . . , XK) including a given number (K) of items, wherein each value for said given number (K) identifies a corresponding set of interleaving parameters (R, C, p, v). The arrangement has at least one memory unit wherein a plurality of records are stored, each record being indicative of a respective set of parameters (R, C, p, v) corresponding to at least one value for said given number (K). Sets of interleaving parameters (R, C, p, v) are thus available in the memory unit to be promptly and directly retrieved for all possible values of said given number of items (K). A preferred use is in turbo encoders/decoders for advanced telecommunications applications such as UMTS.

Abstract: A method and system using a single interleaver at a either a receiving device or a transmitting device where a first symbol set is read from the single interleaver and concurrently with a second symbol set is written to the single interleaver, and a controller that synchronizes the reading of the first symbol set from the interleaver and the writing of the second symbol set to the interleaver so that a particular symbol of the second symbol set is only written to a location of the interleaver after a particular symbol of the first symbol set has been read from the location. The controller may switch between orders, e.g., row order and column order, of reading and/or writing symbols to the single interleaver when all of the symbols for a particular set of symbols associated with the single interleaver have been read, according to another embodiment.

Abstract: Techniques are provided for performing substitutions of bit sequences that are known to cause errors. Input data is initially modulation encoded. The modulated data is then analyzed in a sliding window to determine if it contains any additional bit sequences that are known to cause errors. If an error prone bit sequence is identified in the data, a substitution engine replaces the error prone bit sequence with a predetermined pattern of bits that is less likely to cause errors. The bit stream output of the substitution engine is then recorded on a storage medium. The recorded bit stream is decoded when it read from the medium. The decoding process identifies the substituted bit pattern and replaces the substituted pattern with the original sequence of bits.

Abstract: Techniques are provided for applying modulation constraints to data streams divided into separate interleaved portions. The even and odd bits in a data stream are separated into two data paths. A first modulation encoder encodes the even bits according to a first constraint. A second modulation encoder encodes the odd bits according to a second constraint. The two encoded data streams are then interleaved to form one data stream. The modulation encoders can encode the two data paths using Fibonacci encoding.

Abstract: This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting. according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the interleaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.

Abstract: Techniques are provided for applying modulation constraints to data by using periodically changing symbol mappings to replace certain prohibited error prone data patterns. Initially, user data in a first base is mapped to integers of a second base using a base conversion technique. The integers in the second base correspond to symbols. Subsequently, periodically changing symbol mappings are performed during which prohibited symbols generated during base conversion are mapped to permitted symbols. The periodically changing symbol mappings occur in multiple phases, and the prohibited symbols are different in each phase. The resulting data is processed by a precoder in some embodiments.

Abstract: A method and apparatus for interleaving bits in a first sequence is disclosed. An exemplary method comprises storing a set of offset values in at least one table, applying in order each of the set of offset values to identify an adjacent bit pair in the first sequence of the bits for a new interleaved sequence of the bits and incrementing each of the set of offset values until an upper limit is reached to further identify additional adjacent bit pairs in the first sequence of the bits for the new interleaved sequence of the bits. The table is significantly shorter, requiring less memory than that used in a conventional interleaver, particularly a GSM interleaver for half rate speech.

Abstract: Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

Abstract: A system and method of forming RLL coded data streams with separator blocks has an RLL encoder and a channel encoder. The input code word is divided into data portions and a separator portion. The data portions are inserted into an output codeword without encoding. Each data portion is separated from a next data portion by a space. The separator portion is encoded into non-zero separator sub-matrices, which are stuffed into the spaces between the data portions. The separator portions and the data portions may be separately permuted without exceeding a maximum number of consecutive zeros.

Abstract: A transmitter transmits successive data fields, and each data field includes a mix of VSB data segments and E-VSB data segments and interleaved portions of maps. The maps define the mixes of VSB data segments and E-VSB data segments in corresponding data fields to be transmitted after the corresponding maps are transmitted. Prior to interleaving, the maps are encoded. At a receiver, the maps are de-interleaved and de-coded so as to derive the mix of VSB and E-VSB data segments defining each of the data fields. The interleaving and de-interleaving have a combined latency of at least L fields. The VSB and E-VSB data segments of each of the data fields are separated in response to the de-interleaved maps.

Abstract: The invention relates to a method, a system and a computer program product for bit swapping, wherein periodically I successive bits of a data packet that comprises K bits are mapped onto interleaved bit positions in I different bursts, respectively, according to a predefined interleaving scheme and a selected interleaving depth I, comprising the step of swapping the value of at least one bit that is associated with a respective first bit position m in the data packet with the value of a bit that is associated with a respective second bit position n in the data packet, wherein the respective second bit position n is selected such that n>m holds and that the difference n?m is divisible by I.

Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset.

Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset.

Abstract: The invention relates to a method, a system and a computer program product for bit swapping, wherein periodically I successive bits of a data packet that comprises K bits are mapped onto interleaved bit positions in I different bursts, respectively, according to a predefined interleaving scheme and a selected interleaving depth I, comprising the step of swapping the value of at least one bit that is associated with a respective first bit position m in the data packet with the value of a bit that is associated with a respective second bit position n in the data packet, wherein the respective second bit position n is selected such that n>m holds and that the difference n−m is divisible by I.

Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset.

Abstract: A system and method to modulate coding based on an ECC interleave structure include a first encoder encoding an input stream of bits comprising input blocks sorted into interleaves. A second encoder encodes a subset of the input blocks to produce output blocks, where the first encoder permutates a remainder of the input blocks and the output blocks to produce a codeword.

Abstract: A system and method to modulate coding based on an ECC interleave structure include a first encoder encoding an input stream of bits comprising input blocks sorted into interleaves. A second encoder encodes a subset of the input blocks to produce output blocks, where the first encoder permutates a remainder of the input blocks and the output blocks to produce a codeword.

Abstract: Presented is a method and system for interleaving or de-interleaving a datastream of codewords divided into indexed symbols including the step of allocating an electronic memory into a predetermined number of FIFOs equal to the desired depth (D) of the interleave operation.

Abstract: A block interleaver is provided using a relatively small register file and a larger random access memory (RAM). In one embodiment, the size of the RAM is larger than the size of the register file by at least one order of magnitude. As a result, the register file consumes significantly less power than the RAM for similar operations. The register file receives a stream of sequential data values and stores the data values in a column order. The data values are then read from the register file in a row order. The data values read from the register file in a row order are then written to the RAM in a row order. The data values are then read from the RAM in a row order, thereby creating an interleaved data stream. In a particular embodiment, the data values are written to the RAM in a staggered row order and read from the RAM in a sequential row order. All accesses to the RAM are performed using the full width of the RAM, such that no unnecessary power is used to access the RAM.

Abstract: A receiver unit for use in a CDMA system and including a channel processor, a buffer, and a data processor. The channel processor processes samples for one or more physical channels for each time interval to provide symbols. The buffer is operated as a number of memory banks. Each memory bank is associated with a respective time interval and stores symbols associated with that time interval. The data processor retrieves symbols for a particular “traffic” from one or more memory banks and processes the retrieved symbols. For the W-CDMA system, each traffic includes one or more radio frames for a particular transmission time interval. The receiver unit typically further includes a controller that directs the storage and retrieval of symbols to and from the memory banks and a decoder that decodes symbols processed by the data processor.

Abstract: A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.

Abstract: A method for prioritizing protection in the symbol mapping of selected information includes the steps of supplying information bits and overhead bits. Interleaving the information bits and overhead bits to supply a plurality of interleaved data blocks. And selectively mapping the plurality of interleaved data blocks into a modulation symbol.

Abstract: In this invention a thirty three bit word is encoded from a thirty two bit word to conform to RLL coding constraints. A parity bit is added to the coded word after coding is complete. With the parity bit inserted the code satisfies a minimum Hamming weight of nine and no more than eleven consecutive zeros and no more than eleven consecutive zeros in both the odd and even interleaves. A table of “bad” eight bit sequences is used to compare the odd and even interleaves of the right and left halves of the input word that is being encoded. If a “bad” sequence is found, its position in the table points to a second table containing a four bit replacement code that is inserted into the coded output word. Flag bits in the output coded word are set to indicate the violation of the coding constraints and provide a means by which a decoder can be used to reverse the process and obtain the original input word.

Abstract: A method and apparatus for convolution encoding and Viterbi decoding utilizes a flexible, digital signal processing architecture that comprises a core processor and a plurality of re-configurable processing elements arranged in a two-dimensional array. The core processor is operable to configure the re-configurable processing elements to perform data encoding and data decoding functions. A received data input is encoded by configuring one of the re-configurable processing elements to emulate a convolution encoding algorithm and applying the received data input to the convolution encoding algorithm. A received encoded data input is decoded by configuring the plurality of re-configurable processing elements to emulate a Viterbi decoding algorithm wherein the plurality of re-configurable processing elements is configured to accommodate every data state of the convolution encoding algorithm.

Abstract: A device and method for performing channel encoding using a frame structure having a termination effect in a recursive systemic encoder for a communication system. The channel encoding device having: an inserter for inserting at least one predefined bit in an input data bit stream at a predetermined position; and a channel encoder for encoding the bit-inserted data bit stream.

Abstract: The invention concerns a method and device for interleaving data forming part of a transmission or reception method. More particularly, the object of the present invention is an interleaving and deinterleaving method, intended to form part of a so-called “turbocoding” method and the associated turbodecoding method, with the aim of proposing more efficient interleavers for a turbocoder, that is to say ones making it possible to obtain a greater minimum distance for the code.

Abstract: A buffer structure for storing intermediate results (i.e., APP data) for a Turbo decoder to increase access throughput, the buffer structure is designed to support concurrent access of APP data for two or more bits for each access cycle. This is achieved by partitioning the buffer into a number of banks, with each bank being independently accessible. To avoid access contentions, the banks are assigned to the rows and columns of a 2-dimensional array used for code interleaving such that APP data for consecutive bits are accessed from different banks. To support “linear” addressing, the banks can be arranged into two sets, which are assigned to even-numbered and odd-number columns of the array. To support “interleaved” addressing, the banks can be assigned to groups of rows of the array such that adjacent rows in the interleaved array are assigned to different groups.

Abstract: The present invention offers a method and a circuit for generating codes enabling transmission of long-codes to start on a reverse channel in a shorter waiting time. The method involves corresponding a shift quantity between the beginning of a sequence M or long-codes cycle, and each timing to a combination of a plurality of masking data; determining a combination of masking data for timing to start generation of long-codes in response to a transmission request at a point of time as soon as possible; and shifting of an initial value of a vector according to the masking data.