Abstract: Embodiments of the invention are directed to a computer-implemented method of for parallel conversion to binary coded decimal format. The method includes receiving, by a floating point unit (FPU), a value in binary floating point (BFP) format. The BFP value includes an integer part and a fractional part. The FPU converts the BFP value to a binary coded decimal (BCD) value. In parallel to converting the BFP value to a BCD value, the FPU performs a rounding operation on the BFP value. The FPU receives the rounding information and operates on the BCD value accordingly.

Abstract: A method of creating a presentation includes extracting text parts from content, assigning first attributes to the text parts based on the content and design similarities between the text parts, assigning second attributes to the text parts based on processing the text content to extract contextual similarities between the text parts, determining groups of the text parts based on the first and second attributes, determining first links between the text parts of different groups using the display information and adjacencies of the text parts, determining second links of the text parts to object types defined by a graph restriction listing the object types and their parameters, and outputting a presentation by setting the text parts in the presentation corresponding to the parameters of their linked object type in the graph restriction, wherein the text parts of each of the groups are associated with a same one of the object types.

Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.

Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.

Abstract: Method and apparatus for determining an alternative character string, in response to an invalid character string being received by a consumer application, wherein the invalid character string is derived from the selection of a series of keyboard keys in combination with a modifier key and wherein each key is associated with at least one glyph. An embodiment includes: a converter component for converting each glyph of the invalid character string into a first format; a converter component for parsing each of the converted first formats into a second format; an alternatives engine for determining from each of the second formats a third format which can be derived from a combination of a selection of the key and an alternative modifier key; and a converter component for converting each of the determined third formats into their associated glyphs for compiling into a list of alternative character strings.

Abstract: The invention relates to a method to efficiently transmit a digital message over a unidirectional optical link, such as the link between a computer screen and a security token equipped with photosensitive elements. It is an object of this invention to provide a source coding scheme that is optimized for transmissions of alphanumerical data containing frequent occurrences of numerals and less frequent occurrences of non-numerical data. This is achieved by using a modified Huffman code for source coding, consisting of a nibble-based prefix-free binary code. The output of the coder is efficiently mapped onto a 6B4T channel code, wherein unused ternary codewords can be used to signal data-link layer events. This efficient signalling of data-link layer events, in turn, allows for a synchronization scheme based on repeated transmissions of a finite-length message, combined with an out-of-band clock signal.

Abstract: Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.

Abstract: Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.

Abstract: Character conversion methods for converting characters from a source character code set to a destination character code set. The source and destination character code sets are analyzed to establish a mapping table indicating relationships therebetween. A target character encoded in the source character code set is converted to destination code encoded in the destination character code set by searching the mapping table.

Abstract: A binary encoding circuit is for converting at least first and second binary input signals into an output code that includes at least first and second binary output signals. The circuit may include at least one first selection circuit and at least one second selection circuit that are interconnected and comprise transistors that can be activated/deactivated, i.e. made to conduct/not conduct, according to the binary input signals. The circuit makes it possible to generate a binary code that represents the binary number of the binary input signals that are simultaneously asserted. The encoding circuit can act as a static counter, for example.

Abstract: An exemplary embodiment of the invention is a method and system for converting a number from binary to decimal. The method includes obtaining an N-bit binary number and then determining the number of multiplications necessary to complete the conversion process by first determining the number of leading zeroes. The method then divides the N-bit number into 12-bit segments where each segment is represented as a binary coded decimal number. The method then multiplies at least one binary coded decimal number by a variable in response to the number of multiplications to determine the resulting decimal value.

Abstract: An LBA/MSF converter includes a decade selector, the decade selector receiving a first input and generating a decade selector output corresponding to a decade of the first input. An operand selector receives the decade selector output and outputs an operand corresponding to the decade selector output. An adder outputs the sum of the first input and the operand, the sum being an MSF value corresponding to the first input when the first input is an LBA value, and a subtractor outputs the difference of the first input and the operand, the difference being an LBA value corresponding to the first input when the first input is an MSF value.

Abstract: A system includes an input, a character set mapping function and a character set compression function. The input receives binary data that includes a plurality of binary data bits that may be organized into a plurality of binary data bytes. The character set mapping function maps the binary data bits into a predetermined character set to produce a plurality of characters. The character set compression function compresses the plurality of characters using a character set compression algorithm to produce a plurality of compressed characters. After compression of the character set data, the plurality of compressed characters may be modulated via a modem and transmitted across a data link to a receiving location. At the receiving location, a demodulator receives the modulated data and demodulates the modulated data to produce the plurality of compressed characters. Then, a character set decompression function decompresses the plurality of compressed characters to produce a plurality of characters.

Abstract: The first shift-register 1 has 4 bits.times.N stages for storing the operated result BCD data 4 bits by 4 bits from LSD. The second shift-register 2 has 4 bits.times.M stages for storing a BIN data to be translated 4 bits by 4 bits from MSD. The D-F/F 5 is to store the output from the first shift-register 1 and the intermediate result, and output thereof is supplied to the arithmetic/logic circuit 6 through the first selector 3. The output of the second shift-register 2 is selected by the second selector 4 to be supplied to the arithmetic/logic circuit 6. The arithmetic/logic circuit 6 performs.times.16 operation for the stored data in the shift register 1, and adding the resultant to 4 bits data stored in the shift-register 2 with carry process. The output DO of the arithmetic/logic circuit 6 is stored in the D-F/F 5 in the first half of the shift clock SCK1, and stored in the shift-register 1 in the latter half of the shift clock SCK1.

Abstract: An extended binary encoding for a plurality of inputs is sensed using a two-phase process. In a first phase binary values are sensed at the inputs. In the second phase, inputs sensed as having a first binary signal value are driven to a second binary value to test whether other inputs which had the first binary signal value also change to the second binary value indicative of a direct connection between the inputs. Accordingly, an enhanced binary encoding is achieved by evaluating not only the binary signal value at the inputs, but also which inputs are connected together, the selective interconnection of inputs extending the 2.sup.N options available for conventional binary encoding.

Abstract: An optimized multiplexer structure reduces the cost in emulation gates in an emulator test system. Extra encoding and decoding logic is added to form a selector with multiple separate subblocks so that the data flow subblock has a reduced input/output (I/O) control path. The circuit reduces the number of control bits from N bits to log.sub.2 N bits.

Abstract: A method and related input/output devices for using biased 2 digit "hybrid radix" numeric fields for inputting, generating, storing, processing, and outputting year numbers ranging from 1900 to 2059 in a data processing system. In a hybrid radix 2 digit year number, the higher digit is treated as hexadecimal, but displayed in a decimal-like style with font patterns such as 0-9 and '0-'5, while the lower digit is treated as ordinary decimal, so that the year 1900 is represented and processed as 00 while the year 2000 as '00. For applications written with high level languages such as COBOL and SQL, the method can be embodied solely in the system side (compiler, other system software and/or hardware), and so that no change other than a re-compilation with a new compiler is needed for existing application software. Compatibility with existing data files and databases is automatically maintained.

Abstract: Binary-Coded-Decimal to binary (DTB) and binary to Binary Coded Decimal (BTD) instructions are executed by an address and execution (AX) chip, a decimal numeric (DN) chip, and a cache. For a DTB instruction, the DN chip receives the operand to be converted from the cache, saves the sign, and stores it in a conversion register. When a bit is converted, a Ready-to-Send signal is sent on a COMFROM bus with a Ready-to-Receive Command on a COMTO bus causes the AX chip to accept the bit and the DN chip to generate the next bit until the resultant operand is produced. If the operand to be converted is negative, the DN chip inverts each remaining bit after the first "1" to obtain a two's-complement result. The result in either case is sent to the cache. For a BTD instruction, the AX chip receives the operand to be converted from the cache, send the sign bit to the DN chip and then the bits of the operand when the Ready-to-Send and Ready to Ready-to-Receive signals are produced.

Abstract: A high-speed universal scaler operates in real time, accepting as an input an N-bit binary data word which is to be scaled (multiplied) by a scale factor specified in units per bit. The input data word is divided into M-bit sections which are provided (together with a count value indicating the position of the M-bit section within the input data word and a scale indicator value specifying which of a plurality of programmed scale factors values is to be used) sequentially as scaling addresses specifying binary coded decimal scale data in a scale memory. The sequential outputs of the scale memory in response to the scaling addresses are summed. When the sequence of addresses has been completed and all of the sequential memory outputs have been summed, the resulting sum will be a scaled binary coded decimal value equivalent to the input data word.

Abstract: A digital level display in which a digital input signal has its highest order non-zero part logarithmically converted by a first decoder and its lower order part logarithmically converted by a second decoder. The outputs of the two decoders are added to be displayed.