Abstract: Systems and methods of storing previously transmitted data and using it to reduce bandwidth usage and accelerate future communications are described. By using algorithms to identify long compression history matches, a network device may improve compression efficiently and speed. A network device may also use application specific parsing to improve the length and number of compression history matches. Further, by sharing compression histories and compression history indexes across multiple devices, devices can utilize data previously transmitted to other devices to compress network traffic. Any combination of the systems and methods may be used to efficiently find long matches to stored data, synchronize the storage of previously sent data, and share previously sent data among one or more other devices.

Abstract: A method comprising receiving a syntax element to be encoded as a code word of a set of code words, determining a mapping between the syntax element and the code word on the basis of a hierarchy level in a tree structure, using the mapping to obtain the code word, and updating the mapping is disclosed.

Abstract: A system and method is disclosed for programming a field programmable gate array. The system involves the recognition of the next following bit sequence to be transmitted to the FPGA through a general purpose input output device. Once the bit sequence is identified, the data line is only changed at the GPIO in those instances in which the next succeeding data bit in the bit sequences is different from the preceding data bit. In those situations in which the next following bit sequence is not different, the clock line is triggered without the necessity of testing, and changing the logic level of the data line.

Abstract: Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.

Abstract: Datawords encoded using a first-order Reed-Muller code are decoded using a Fast Hadamard Transform (FHT). Where the dataword is known to comprise a number of unused bits at one end, the soft decisions of the codeword are reordered. Majority polling is then performed on groups of the soft decisions to produce a series of soft decisions which make up a new codeword. The new codeword is then decoded using an FHT of lower order than the FHT applicable to the originally received codeword.

Abstract: Character conversion methods for converting characters from a source character code set to a destination character code set. The source and destination character code sets are analyzed to establish a mapping table indicating relationships therebetween. A target character encoded in the source character code set is converted to destination code encoded in the destination character code set by searching the mapping table.

Abstract: The data compressor utilizes a plurality of subdictionaries arranged in levels for storing strings of data characters. The subdictionary at the first level stores two character strings and a subdictionary at a subsequent level stores strings that are one character longer than the strings stored in the subdictionary at the level prior thereto. A plurality of data characters are fetched from the input into an input buffer and applied to the respective levels. The subdictionary at a level is searched for the string comprising the string matched at the prior level extended by the fetched character applied to the level. The string code of a string matched at a level is cascaded to the next level. The longest match with the fetched characters is determined by one of the fetched characters resulting in a mismatch at one of the levels. The string code associated with the longest match is output.

Abstract: An LBA/MSF converter includes a decade selector, the decade selector receiving a first input and generating a decade selector output corresponding to a decade of the first input. An operand selector receives the decade selector output and outputs an operand corresponding to the decade selector output. An adder outputs the sum of the first input and the operand, the sum being an MSF value corresponding to the first input when the first input is an LBA value, and a subtractor outputs the difference of the first input and the operand, the difference being an LBA value corresponding to the first input when the first input is an MSF value.

Abstract: The first shift-register 1 has 4 bits.times.N stages for storing the operated result BCD data 4 bits by 4 bits from LSD. The second shift-register 2 has 4 bits.times.M stages for storing a BIN data to be translated 4 bits by 4 bits from MSD. The D-F/F 5 is to store the output from the first shift-register 1 and the intermediate result, and output thereof is supplied to the arithmetic/logic circuit 6 through the first selector 3. The output of the second shift-register 2 is selected by the second selector 4 to be supplied to the arithmetic/logic circuit 6. The arithmetic/logic circuit 6 performs.times.16 operation for the stored data in the shift register 1, and adding the resultant to 4 bits data stored in the shift-register 2 with carry process. The output DO of the arithmetic/logic circuit 6 is stored in the D-F/F 5 in the first half of the shift clock SCK1, and stored in the shift-register 1 in the latter half of the shift clock SCK1.

Abstract: An optimized multiplexer structure reduces the cost in emulation gates in an emulator test system. Extra encoding and decoding logic is added to form a selector with multiple separate subblocks so that the data flow subblock has a reduced input/output (I/O) control path. The circuit reduces the number of control bits from N bits to log.sub.2 N bits.

Abstract: A method and related input/output devices for using biased 2 digit "hybrid radix" numeric fields for inputting, generating, storing, processing, and outputting year numbers ranging from 1900 to 2059 in a data processing system. In a hybrid radix 2 digit year number, the higher digit is treated as hexadecimal, but displayed in a decimal-like style with font patterns such as 0-9 and '0-'5, while the lower digit is treated as ordinary decimal, so that the year 1900 is represented and processed as 00 while the year 2000 as '00. For applications written with high level languages such as COBOL and SQL, the method can be embodied solely in the system side (compiler, other system software and/or hardware), and so that no change other than a re-compilation with a new compiler is needed for existing application software. Compatibility with existing data files and databases is automatically maintained.

Abstract: Binary-Coded-Decimal to binary (DTB) and binary to Binary Coded Decimal (BTD) instructions are executed by an address and execution (AX) chip, a decimal numeric (DN) chip, and a cache. For a DTB instruction, the DN chip receives the operand to be converted from the cache, saves the sign, and stores it in a conversion register. When a bit is converted, a Ready-to-Send signal is sent on a COMFROM bus with a Ready-to-Receive Command on a COMTO bus causes the AX chip to accept the bit and the DN chip to generate the next bit until the resultant operand is produced. If the operand to be converted is negative, the DN chip inverts each remaining bit after the first "1" to obtain a two's-complement result. The result in either case is sent to the cache. For a BTD instruction, the AX chip receives the operand to be converted from the cache, send the sign bit to the DN chip and then the bits of the operand when the Ready-to-Send and Ready to Ready-to-Receive signals are produced.

Abstract: An apparatus for converting a multidigit decimal number into a binary number. In a preferred embodiment, the apparatus includes a register for holding the multidigit decimal number; first conversion logic, coupled to the register, for simultaneously converting a first pair of decimal digits in the multidigit decimal number, into a first binary representation and second conversion logic, coupled to said first conversion logic and the register, for simultaneously converting a second pair of decimal digits in the multidigit decimal number and the first binary representation into a second binary representation of a decimal number defined by the first and second pair of decimal digits.