Abstract: A method executed by a computer system that transmits a multimedia content through a negative-base number. The method includes generating a binary sequence for the multimedia content, converting the binary sequence into a negative-base number, receiving the negative-base number, retrieving a negative base of the negative base number, calculating the binary sequence based on the negative-base number and the negative base, and obtaining the multimedia content based on the binary sequence.

Abstract: Methods and apparatus for compressing data for network transport in support of continuous availability of applications are described. One computer-implemented method of compressing data includes receiving a current instance of data in an input buffer. A candidate chunk of data is selected from the input buffer. A signature hash is computed from a signature length range of data within the candidate chunk. A matching dictionary entry having a matching signature hash from a multi-tiered dictionary is identified. The matching dictionary entry prospectively identifies a location of a prior occurrence of a selected range of consecutive symbols including the signature length range of data within at least one of the current instance of data and a prior instance of data in the input buffer. A dedupe processed representation of the instance of data is formed wherein a dedupe item is substituted for the selected range of consecutive symbols if the selected range is verified as recurring.

Abstract: The present disclosure includes apparatus, systems and techniques relating to pipelined processing. In some implementations, a method performed by a data processing device includes storing data in a memory module. The method includes processing the stored data in accordance with a compression algorithm to produce processed data. Processing the stored data includes pipelined processing of a defined number of symbols of the stored data in parallel, and discarding results of the pipelined processing that are rendered invalid by other results of the pipelined processing. Additionally, the method includes outputting the processed data.

Abstract: An integrated circuit 2 is provided including multiple devices 4, 6, 8, 10, 12, 14 for communicating via an interconnect 16. A sending device 18 includes a sideband signal indicating the use of a representation of a repeating data word in place of that repeating data word itself. The receiving device can then form the repeating pattern of data words in response to receipt of the representation. This reduces the bandwidth consumed upon the interconnect 16.

Abstract: A memory device includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal. A memory system includes a memory controller and one or more memory devices, at least one or which includes a receiver to receive a first input data signal and to create an output signal corresponding to the first input data signal and a voltage representative of a second signal received earlier in time than the first input data signal.

Abstract: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n?2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.

Abstract: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n?2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.

Abstract: Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded bit to be coupled to a first address in a memory device may be exchanged with an encoded bit to be coupled to a second address in the memory device. Apparatus, systems, and methods are disclosed that operate to invert encoded bits in logic circuits in the memory device if original bits were inverted. Additional apparatus, systems, and methods are disclosed.

Abstract: An apparatus, system, and method are disclosed for communicating binary data using a self-descriptive binary data structure. The binary data structure also may be referred to as a microcode reconstruct and boot (MRB) image. The binary data structure includes a plurality of data segments, a target data set, and a data structure descriptor. Each of the data segments has a data segment header and data field. The target data set is stored within the data field and may be an executable. The data structure descriptor is descriptive of the binary data structure and identifies the location of the target data set within the data field. The binary data structure is self-descriptive in that the location of an individual target data set may be identified by the data structure descriptor.

Abstract: An integrated circuit can operate in a first mode as a parallel-to-serial converter, and in a second mode as a serial-to-parallel converter. Some of the components of the integrated circuit are used in both modes. For example, the IC has a single parallel interface, which is used as a parallel input in the first mode, and as a parallel output in the second mode. Further, the IC includes a single phase-locked loop circuit, which is used in a clock multiplier unit in the first mode, and in a clock recovery circuit in the second mode.

Abstract: A product with stored non-sequential data may be provided using a method that codes the data to a coding pattern using at least one sequence with symbols. The coding pattern may be configured such that an arbitrary subsequence of a predetermined magnitude of the sequence unambiguously defines the position of the subsequence in the sequence. The coding pattern may be reproduced on a product. An apparatus may be adapted to record and decode the coding pattern.

Abstract: A media storage device includes an embedded filter for manipulating universal clock based streams of data as they are written to or read from the media storage device. The media storage device will also manipulate streams of data which are not being written to or read from the media storage device. Preferably the embedded filter within the media storage device is an isochronous data pipe which will receive programmed instructions from an external controller and manipulate streams of data according to the programmed instructions in real time, coordinated with the universal clock. Alternatively, the isochronous data pipe includes fixed firmware for performing the appropriate manipulations. The media storage device is also preferably coupled to an IEEE 1394-1995 serial bus structure.

Abstract: A programmable bandwidth I/O port using a DRAM connected to a plurality of serial access memories. Data is synchronously transferred between the DRAM and the serial access memories and is asynchronously transferred between the serial access memories and a plurality of single or multiple bit I/O ports. The bus widths of the I/O ports may be easily programmed to provide a wide variety of I/O port configurations.

Abstract: The raw digital output signal generated at the transmitter by an ADC is XOR'd with a sequence of pseudo-random numbers to generate an encoded output signal. This removes all correlation between the analog input signal and the encoded output signal. Coherence between the encoded output signal and the analog input signal is prevented and the effects of crosstalk to the analog input signal are mitigated. In a first embodiment of the invention, the sequence of pseudo-random numbers is a sequence of one-bit pseudo-random numbers that are XOR'd with each bit of the raw digital output signal. In a second embodiment, the sequence of pseudo-random numbers is a sequence of N-bit pseudo-random numbers that are XOR'd with the N-bit words of the digital output signal. To recreate the original raw digital output signal in the receiver, a second XOR operation is performed between the encoded output signal and the sequence of pseudo-random numbers.

Abstract: A data format converter for executing log conversion, antilog conversion, floating point conversion and inverse floating point conversion in an adaptive differential pulse code modulation (ADPCM) processor, which has an excellent data format conversion speed.

Abstract: In a digital communication network in which pieces of information having different PCM coding rules are present, an information storage apparatus includes a control unit, a storage unit, and at least one transconverter. The control unit includes a comparator which compares the coding rule identifier read from the storage unit with a coding rule identifier of the read destination, when the control unit receives the information read request signal transmitted with the coding rule identifier of the read destination, so that if the coding rule identifier read out from the storage unit coincides with the coding rule identifier of the read destination, the PCM-coded information read out from the storage unit is transmitted without code conversion, and if the coding rule identifier read out from the storage unit does not coincide with the coding rule identifier, the PCM-coded information is transmitted through a selected transconverter to produce code-converted PCM-coded information.

Abstract: A cable for connecting a peripheral device to an input/output port configured in accordance with either a SCSI protocol or a parallel port protocol has a first connector which has a plurality of contact pins for connecting the cable to the peripheral device; a second connector which has a plurality of contact pins for connecting the cable to the input/output port; and a plurality of twisted pairs each having a first conductor and a second conductor. The first conductor of each of the twisted pairs is a data/control line, and the second conductor of the twisted pair is a return for the respective data/control line in accordance with the SCSI protocol. The first and second conductors of each of the twisted pairs are connected between selected pins of the first and second connectors such that none of the twisted pairs carries a data/control signal on both its first and second conductors when the cable is connected to an input/output port that is configured in accordance with the parallel port protocol.

Abstract: A bidirectional device converts a series of data bits partitioned into first group of frames corresponding to a first type of interface into second groups of frames having a second type of interface. The converter first converts signals from a device operating under the first type of interface to standard bilevel digital signals and then converts the standard bilevel digital signals into the second type of interface.

Abstract: A bit pattern conversion system for converting a sequence of a bit pattern between a central processing unit and a peripheral circuit, including a data bus line connected between the central processing unit and the peripheral circuit, and a conversion circuit provided in the peripheral circuit for converting the sequence of the bit pattern from a most significant bit to a least significant bit, and vice versa, in accordance with a conversion signal.

Abstract: Dedicated convert hardware is disclosed for performing bidirectional conversions of numbers between binary and another base b (illustratively decimal) for use in a data processing system. The dedicated convert hardware comprises a special purpose multiply-and-add unit and a convert register. The output of the multiply-and-add unit is coupled to the input of the convert register, and the output of the convert register is recycled to the inputs of the multiply-and-add unit. The multiply-and-add unit is hardwired to multiply the input by b and concurrently add the value at a separate digit input. Means are also provided for initializing the convert register with zero or with any desired number.