Abstract: An LED control circuit and an electronic device, and an electronic apparatus. The LED control circuit includes a power terminal, a grounding terminal, and a plurality of control signal outputs, and a level recognition circuit outputs a digital signal according to a voltage difference between a voltage at the power terminal and a voltage at the grounding terminal. a decoding circuit parses the digital signal to obtain control data of the LED control circuit, and output a plurality of control signals to a plurality of control signal outputs according to the control data. Thus, a reference circuit for providing the reference voltage is omitted, a circuit configuration is simplified and a hardware cost is reduced.

Abstract: The present application discloses an identification circuit for a power-line carrier signal. During signal transmission on a power line, the amplitude change and duration of a voltage signal on the power line are identified and then decoded into corresponding data, so as to reduce dependency on a power supply voltage during signal identification, and prevent the signal identification rate from decreasing as a result of an increase in the transmission distance, thereby reducing requirements for a system power supply.

Abstract: A method and device for intra prediction are provided. The method includes: when determining that a current level obtained by partitioning an input point cloud is lower than a target level, obtaining occupation information of a first number of neighbouring nodes of a current node; extracting occupation information of a second number of neighbouring nodes from the occupation information of the first number of neighbouring nodes, the first number being greater than the second number, and the second number of neighbouring nodes being in an association relationship with a child node of the current node, and performing intra prediction on occupation information of the child node of the current node based on the occupation information of the second number of neighbouring nodes to obtain a first prediction result.

Abstract: A decoding circuit is adapted for decoding an input signal. The input signal includes at least a break and the time length of the break is a preset time. The decoding circuit includes a decoding unit and a detecting unit. The detecting unit detects whether the voltage level of the input signal is kept at a specific logic level for more than the preset time. If the input signal is kept at the specific logic level for more than the preset time, the detecting circuit, according to the voltage level of the specific logic level, outputs the input signal or the inverted input signal to the decoding unit so as to perform a decoding process.

Abstract: A system comprising a control logic that generates a code having n digits, a translation logic coupled to the control logic that translates the code to a new code having greater than n digits, and a variable resistance logic coupled to the translation logic and comprising greater than n semiconductor devices. A resistance associated with the variable resistance logic depends on activation statuses of the semiconductor devices. The translation logic adjusts at least some of the semiconductor devices in accordance with the new code.

Abstract: A current controller for a multi-level current mode driver. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied from the at least one source calibration signal to the comparator.

Abstract: A semiconductor integrated circuit device has an analog signal conductor and a digital signal conductor formed on a single circuit board. In the lowest layer is laid a polysilicon conductor as the digital signal conductor, on top thereof is laid a first aluminum conductor as a shielding conductor, and further on top thereof is laid a second aluminum conductor as the analog signal conductor. With this structure, it is possible to give the highest priority to improving the transmission quality of analog signals and simultaneously reduce transfer of noise from the digital signal conductor to the analog signal conductor.

Abstract: A semiconductor integrated circuit device has an analog signal conductor and a digital signal conductor formed on a single circuit board. In the lowest layer is laid a polysilicon conductor as the digital signal conductor, on top thereof is laid a first aluminum conductor as a shielding conductor, and further on top thereof is laid a second aluminum conductor as the analog signal conductor. With this structure, it is possible to give the highest priority to improving the transmission quality of analog signals and simultaneously reduce transfer of noise from the digital signal conductor to the analog signal conductor.

Abstract: A device information generating device comprises a device key matrix storage unit configured to store a device key matrix in which device keys are arranged in a two dimensional manner, and a device key generating unit configured to select one of the device keys in each one dimensional array of the device key matrix according to each numeral of a device ID, wherein the selected device keys and the device ID are the device information.

Abstract: The apparatus and method describes herein shows a system of digitizing analog or digital electronic or optical signals with very high single bit serial digital data streams which digitizing is suitable to automatically adapt the transmission of multiple types of analog and digital signals. The system is especially well suited for allowing the coupling and transmission of signals.

Abstract: A multistage data compression system includes an encoder for receiving input data sequences from a data source, where the encoder comprises two or more quantizer stages, each stage having a memory for storing an established set of codewords preselected such that the sum of different combinations of codewords, one for each stage, is representative of likely to occur input data sequences. Each codeword of each stage has a respective index associated therewith. The encoder operates to select a codeword from at least two of the stages such that the sum of the selected codewords is a closer match to each input sequence than any other sum of codewords formed from the selected stages. When the codewords of interest are determined, the indices of those codewords are retrieved. These indices may then be transmitted to another location, stored in memory or otherwise processed. The system also includes a decoder coupled to the transmission channel, memory, or other mechanism which operates on the indices.