Abstract: A signal processing apparatus comprises an operation processing part that performs operation processing on data represented in the two's complement representation and a storage processing part that performs storage processing on data represented in a second representation format as a data representation format, and in the second representation format, a data value is identical to one in the two's complement representation when the value is positive or zero, and all the bits lower than the most significant bit that indicates the sign in the two's complement representation are inverted when a data value is negative.

Abstract: Systems and devices are provided to perform low-power digital filtering of sensor or other data based on bitwise operations. A reference sinusoid is encoded via a plurality of pulse trains, such that each pulse train includes a number of pulses n representing a value of the reference sinusoid out of a maximum possible pulses corresponding to an encoding quantization level. A circular register stores a representation of the encoded sinusoid. A set of multiple logical gate blocks are configured to multiply, via one or more bitwise operations, each of multiple bits of a received input signal with a pulse train corresponding to a value of the encoded sinusoid. A logic circuit coupled to the circular register and the set of multiple logical gate blocks is configured to generate, based on the encoded sinusoid and on the input signal, an output signal indicating an approximate value of the received input signal multiplied by the encoded sinusoid.

Abstract: An apparatus is configured to extract a rightmost bit position of a target value based on input data and a complement of the input data, sequentially extract a bit position of the target value, and output the extracted bit position.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

Abstract: A display device with reduced power consumption has pixels coupled with data lines and arranged in a matrix, a signal controller processing input image signals and outputting output image signals, and a data driver applying data voltages, corresponding to output image signals, to the data lines. When all the input image signals have either a first or second value, the output image signals have the first value. The signal controller generates a polarity signal for determining data voltage polarity, and when all the input image signals have either a first or second value, data voltages corresponding to the input image signals have a polarity equivalent to a polarity of previously applied data voltages. The signal controller generates a control signal for controlling the data driver's clock synchronization circuit, and the control signal halts the clock synchronization circuit when an operating frequency is lower than a predetermined value.

Abstract: Systems, methods and data structures are provided for representing robust data transmitted within a control system. The data structure includes at least two data fields identifying sub-modules and sub-modes of the control system, and optionally includes a third field for designating a primary operating mode of the control system and/or a fourth field representing a handshaking bit or value. The operating modes, sub-modes and sub-module designators are represented by values of the bits selected such that no single bit transition results in the selection of another valid operating state of the control system. As a result, single bit errors will not produce erroneous operating results. Similar concepts can be optionally applied to ensure that errors in contiguous sets of four, eight or any other number of bits do not produce valid states represented by the data structure.

Abstract: A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular symbol cell, and integrating for a second interval with a negative polarity within the particular symbol cell, to produce output representing the codewords. A sense circuit produces an output data stream.

Abstract: An adapter configured to automatically detect and compensate for differential signal inversion is herein disclosed. In one embodiment, the adapter is part of a computer network having differential conductor pairs conveying differential signals between network devices. The network devices include adapters coupled to transmit and receive signals via the differential conductor pairs. The adapter preferably includes a lane receiver, a decoder, and a synchronization circuit. The lane receiver is configured to receive a single differential signal and to convert the differential signal into a sequence of code symbols. The decoder decodes the code symbols to produce a sequence of received symbols. The synchronization circuit examines the sequence of received symbols to determine if it is incorrect due to inversion of the differential signal, and if so, it causes the lane receiver to correct for the differential signal inversion.

Abstract: An analog/digital converting device includes: a first constant-voltage circuit which outputs a predetermined conversion reference voltage used for analog/digital conversion; a second constant-voltage circuit which outputs a predetermined correction reference voltage used for correction of the analog/digital conversion; an analog/digital converter for converting an object analog value and a correction analog value indicative of a voltage value of the correction reference voltage into an object digital value and a correction digital value on the basis of the conversion reference voltage at a predetermined resolution; and a correction processor for previously storing a correction ideal digital value obtained by analog/digital converting a correction ideal voltage value without an error corresponding to the voltage value of the correction reference voltage on the basis of a conversion ideal voltage value without an error corresponding to the voltage value of the conversion reference voltage at the resolution, and

Abstract: A descrambling method is suitable for improving the data transfer rate and fast data processing separate scrambled data into a plurality of data groups each including plural pieces of scrambled unit data. Initial scramble patterns are respectively assigned to the data groups. An initial scramble pattern is prepared and assigned to a specific data group. A first scramble pattern is generated in one clock cycle using the prepared initial scramble pattern and then one of the scrambled unit data pieces in the specific data group is prepared. A descrambling operation using the first scramble pattern and the prepared one scrambled unit data piece is then performed to produce an original data piece.

Abstract: A digital half-band filter with mutliplications using Wallace trees which have lower bits truncated for reduction in size and with a true/complementer providing saturation compensation together with accumulator overflow compensation by monitoring bits more significant than the output bits.

Abstract: A 2's complementer having a simple circuit arrangement and yet obtaining a high 2's-complementation rate. The 2's complementer includes an inverting circuit for inverting binary data with at least two bits to produce an 1's complement. The 2's complementer also includes an inverter for inverting inverted data resulted from an inversion of the least-significant bit of the 1's-complement data of at least two bits, and at least one exclusive OR gate for comparing bit data to be currently processed with lower-order bit data of at least one bit of the 1's-complement data, and inverting the current bit data when the at least one lower-order bit data has the value of logic-1.

Abstract: A hard-wired circuit (25) is provided for controlling or for monitoring a plant or process (12). The circuit incorporates means (14) to sense the current state of the process, an input encoder (16) to generate multi-digit binary coded signals representing that sensed state, and an output encoder (18) to generate multi-digit binary output coded signals corresponding to the signals from the input encoder (16), which output signals can be used to control process or plant actuators. Both the input encoder (16) and the output encoder (18) may be PROMs. A complement modulator (20) activated by an oscillator (24) may be used to provide dynamic output signals; and by means of appropriate comparators (26, 38) and watchdogs (28, 40) the input and output coded signals may be verified.

Abstract: A parallel-serial data converter according to the present invention comprises a n-th latch circuit which latches the sign bit at the most significant bit of parallel data, a n-1th selector which selects either of the n-1th bit or the ground level, a n-1th latch circuit which latches the output from the selector n-1, a i-th selector which selects either of the i-th bit (i=n-2, n-3, . . .

Abstract: An absolute value circuit comprises a first "1" bit detecting unit for sequentially searching input binary data from the least significant bit toward the most significant bit so as to detect a first "1" bit whose value first becomes "1", and a sign discriminating unit for discriminating the polarity of the input binary data. When the input binary data is positive, a data processing unit outputs the input binary data without modification. When the input binary data is negative, the data processing unit outputs data composed of bits from the least significant bit of the input binary data to the first "1" bit detected by the first "1" bit detecting unit, and an inverted bit or bits of a bit or bits of the input binary data more significant than the first "1" bit.

Abstract: A binary data converter is adapted to convert a positive binary data into a negative binary data represented by a complement on two and vice verse. The conversion is effected as follows. A least significant bit of an inputted binary data is outputted as the least significant bit of the converted binary date as it is. With respect to bit signal other than the least significant bit, respective input bit signals less significant than the corresponding input bit signal are ORed. Depending on the result thereof, inverted or non-inverted signals of the corresponding input bit signals are outputted as the bit signals of the converted binary data. Therefore, carry delay is not generated, and thus the operation speed can be increased. Further, the simple circuit structures can reduce the number of required elements.

Abstract: A multi-stage adder has a plurality of parallel inputs some fed to one stage of the adder and other inputs fed to a next stage of the adder. To effect selective inversion of a pair of inputs one of the pair is connected to one stage and the other of the pair is connected to the next stage. A cross-over switch is provided on both inputs so that their connection to the two successive stages can be interchanged.

Abstract: A digital signal processor comprises a code converter which converts an integer coded in a Binary Two's Complement (BTC) code to an integer coded in a Sign Magnitude Binary (SMB) code and/or a code converter which converts the SMB code to the BTC code. An integer coded in the BTC code and stored in an m-bits register is converted to an integer coded in the SMB code and input to an n-bits register, by an EXCLUSIVE OR processing of the bits with the sign bits and by supplementing a logic "1" in the less significant bit next to the least significant bit of the result of the exclusive OR operation. An integer coded in the SMB code and stored in an n-bits register is converted to an integer coded in the BTC code and input to an m-bits register, by an EXCLUSIVE OR processing of m-1 bits of magnitude bits with a sign bit. The code converters have a relatively simple construction, will not output an incorrect result, and are most suitable for processing AC signals.

Abstract: As an orthogonally transformed signal carries a value adjacent to zero, the output of an orthogonal transformer is coupled in series to a fixed length code encoder for converting the orthogonally transformed signal into a fixed length code signal which exhibits less bit inversion between positive and negative signals near zero. The orthogonal transformer and the fixed length code encoder constitute in combination an orthogonal transformer device.

Abstract: A code converter includes an extraction device for extracting a reference level from a binary-coded input signal, which is offset at a predetermined voltage level and which varies arbitrarily with the same polarity as the voltage level. A twos-complement conversion device, connected to the extraction device, converts the reference level into a twos-complement value. A creation device, connected to the extraction device and the twos-complement conversion device adds an output signal of the twos-complement conversion device and the binary-coded input signal, thereby producing a bipolar binary-coded output signal to which a polarity bit is added.

Abstract: A format converting circuit for numeric data comprises an operation unit which operates according to a mode decision signal to output an input data as it is or a two's complement of the input data; a storage device which stores a positive or negative sign data to be read out and is reset by an initializing signal to a positive data storing state; and a control circuit which operates in two conversion modes. One of the modes is a signed-to-unsigned conversion mode in which the control circuit controls the operation unit with the mode decision signal such that, if a sign bit of the input data is 0, the operation unit outputs the data as it is while, if the sign bit is 1, the operation unit outputs a two's complement of the input data. At the same time, the control circuit inverts the data stored in the storage device if the above-mentioned sign bit is 1.

Abstract: An arithmetic processor is disclosed for performing arithmetic operations utilizing an arithmetic operand represented by a signed digit expression having a plurality of digits which may have a positive, zero or negative value.