Abstract: According to one exemplary embodiment of a buffer clearing apparatus for computer graphics, a buffer clearing (BC) hardware agent is configured to interface between one or more system buses and a memory controller, to execute one or more frame buffer clearing operations while performing memory access or power of buffer-related operations at the same time. The BC hardware agent keeps track of a plurality of status to read from and/or write to a frame buffer. When the frame buffer is to be cleared, the BC hardware agent clears a clear tag table. When a background pixel of the frame buffer is to be read, the BC hardware agent returns a background value stored in itself.

Abstract: A display uses x illuminator systems to produce x primary colors and y overlap colors, which are combinations of primary colors, to illuminate a spatial light modulator in a display system. A first set of n duty cycles for the x primary colors over a frame is provided, wherein the display system can select any one of the duty cycles to produce a desired white point. A second set of n duty cycles of x+y colors over a frame corresponding to the first set of duty cycles is determined, where the second set of duty cycles are generated responsive to a specified desired allocation of the frame to the y overlap colors, such that each of the overlap colors can be displayed from a dark shade to a bright shade while maintaining a constant color point.

Abstract: A method for correcting colored fringe artifacts in a region of an image around saturated pixels captured by an electronic imager associated with a color filter array, includes providing a threshold map of the image based on thresholding one or more color channels with a common or separate threshold value for each color channel; providing a first edge map by dilating the threshold map as a function of the color fringe width, producing a first dilated threshold map and subtracting the threshold map from the first dilated threshold map; and color-desaturating image pixels that correspond to the first edge map.

Abstract: Methods are disclosed for selectively loading one control at a time based on the location of a selection component relative to a graphical representation of a user interface.

Abstract: These teachings present triple data transport redundancy in the form of three data bus interfaces that are each designed and manufactured independently from one another and compatible with a common data handling protocol. This protocol can be one that includes no error correction. These interfaces can each couple to a corresponding first, second, and third data bus that may comprise optical data busses. Information gauges can be realized through use a memory that stores a plurality of images comprising views of an information gauge (or gauges) of interest showing a variety of different readings. Upon receiving information regarding a monitored parameter of interest (via, for example, the aforementioned data busses and data bus interfaces), this information can be used to address the stored information gauge view that corresponds to the present parameter value. That particular view can be recalled and displayed to thereby provide the corresponding information to a viewer.

Abstract: Disclosed is a visual communication signal (32) which comprises image model information (10) for generating 3-D images. The image model information (10) may comprise a 3-D image model, e.g. a 3-D wireframe model or a 3-D voxel map. Some of the generated 3-D images may have a relatively low image quality. The visual communication signal (32) further comprises image enhancement information (20) corresponding to at least part of the 3-D images for enhancing the image quality of the generated 3-D images. This image enhancement information (20) may comprise image information corresponding to one or more single viewpoints (22, 24) and/or image information corresponding to one or more ranges of viewpoints (26, 28). The visual communication signal (32) may be transmitted from a transmitter (30) to a receiver (34) in a visual communication system (40) such as a 3-D television system or a 3-D teleconferencing system. Alternatively, the visual communication signal (32) may be carried by a tangible medium, e.g.

Abstract: With the present invention, there is provided a driving method that favorably drives an electron source, which is driven in a passive matrix manner, without being affected by a disturbance. There is also provided an image-forming apparatus that uses this electron source. An anode electrode having a constant potential is arranged over a plurality of electron-emitting devices including gate electrodes and cathode electrodes. During passive matrix driving of the electron source where the amount of electrons to be emitted is adjusted by modulating potentials between the cathode electrodes and the gate electrodes, a predetermined time difference is maintained between the driving of signal lines in a group and the driving of signal lines in another group during the driving of signal lines divided into N groups after selection of scanning lines.

Abstract: A shooting video game machine includes a monitor screen, a light source near the monitor screen, and a mock gun having an image sensor with a pixel array for capturing an image including the monitor screen and the light source. A light source position detection unit detects as image position of an image of the light source in the pixel array. A hit position detection unit for determines a position aimed at on the monitor screen based on the image position. The light source position detection unit includes a detector for detecting pixels having data of the image of the light source and stores only address of the detect pixels to a memory. A light source position calculator calculate the image position of the light source according to the address data stored in the memory in a certain time period.

Abstract: A mapping apparatus is disclosed for showing special effects on screen images.

Abstract: There is provided a display control device according to which video data for a plurality of windows to be displayed on a display screen is prestored in a video memory regardless of a display position of the video data in each of the windows and an effective zone of each of the windows in a display screen and a priority order of the respective windows are also prestored. With respect to each scanning position in the display screen, one of the windows which is of the highest priority order is selected from among the windows which are being scanned in accordance with an effective display zone and a priority order of each of the windows, and video data of the selected window is read from the video memory on the basis of relation between the display position and the storage position of the video data.

Abstract: A computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed.

Abstract: A graphic pattern processing apparatus having a display memory, a data processor, a graphic processor, and a plurality of parallel to serial convertors. The display memory stores graphic data in words, each word has a plurality of pixel data and each pixel data has a plurality of bits. A graphic processor accesses the display memory and processes a plurality of the pixel data in response to instructions received from a data processor. The number of parallel to serial convertors corresponds to the number of bits per pixel and are configured to allow a word from the display memory to be converted into a serial stream of pixel data.

Abstract: A system that clears a portion of a graphics display in synchronization with an electron beam scanning the face of the graphics display. When a clear operation for a window on the graphics display screen is received, the system compares the location of the beam with the window and determines whether an interference would occur if the window is cleared immediately. If no interference would occur, the window clear operation is immediately started. If an interference would occur, the system waits until the electron beam has scanned beyond the top of the window before starting the clear operation. Then, before clearing each scan line, the system waits until the beam has already scanned past the scan line being cleared.

Abstract: A timing generator 12' applies a control signal SC1 consisting of a row address strobe signal RAS1, a column address strobe signal CAS1 and a writing control signal WE1 to a control input C of a DRAM 31 while it also applies a control signal SC2 consisting of a row address strobe signal RAS2, a column address strobe signal CAS2 and a writing control signal WE2 to a control input C of a DRAM 32. The control signals SC1and SC2 are produced in accordance with the least significant bit LSB of an inside address MA and independent of each other. The display data reading operation can be performed on each of memories (DRAMs) independent of each other, and therefore, the total period for the display data reading can be shortened, and accordingly, a saving of time allows an interruption of a longer period of the display data writing operation during the display period, and thus, a time for a display data renewal can be shortened.

Abstract: A video display system includes a frame buffer comprising five sets of one or more VRAMs. An address generator for generating address locations in the frame buffer generates chip select, row select and column select address signals. Because the frame buffer comprises five sets of VRAMs, the generation of the address signals requires divide-by-five operations to be carried out. Accordingly, the address generator includes a unique divide-by-five circuit wherein the division is carried out by a sequence of additions and multiplications. In comparison to conventional systems, the video system of the present invention makes more efficient use of memory capacity in the frame buffer.