Field Rate Type Flicker Compensating Patents (Class 348/447)
  • Patent number: 6714191
    Abstract: A method, system and apparatus for detecting a sub-pixel pair susceptible of producing a flicker event in an image from a video signal source displayed on a liquid crystal display (LCD) unit is described. A two dimensional flicker pattern analysis is performed on a selected group of sub-pixels some of which are included in a first plurality of sub-pixels that includes a first current sub-pixel and a first next sub-pixel included in a first video frameline and a remainder of which are included in a second plurality of sub-pixels included in a second video frameline that is received, in real time, from the video signal source that includes a second current sub-pixel and a second current sub-pixel.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: March 30, 2004
    Assignee: Genesis Microchip Inc.
    Inventors: Che Ming Wu, Vincent Wang, Jih Hsien Soong
  • Patent number: 6714250
    Abstract: Plasma Display Panels (PDP) are becoming more and more interesting for TV technology. Due to the larger size of PDPs, with larger viewing angle the large area flicker effect will become more serious in the future, in particular when handling 50 Hz video standards. This invention proposes a different sub-field organisation, with different coding, which reduces large area flicker artefact, and which includes grouping of sub-fields in two sub-field groups wherein the two sub-field groups are identical in terms of the most significant sub-fields and different in terms of the least significant sub-fields, and a sub-field coding process that distributes luminance weight symmetrically over the two sub-field groups so as to minimize the large area flicker luminance component.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: March 30, 2004
    Assignee: Thomson Licensing S.A.
    Inventors: Carlos Correa, Sébastien Weitbruch, Rainer Zwing, Gangolf Hirtz
  • Patent number: 6710819
    Abstract: A method and a system for improved filtering of display data is disclosed herein. A display system may be used to separately filter display components of the display data based on frequency content of the display components. The display system can include a display data source, a digital image processor, and a display. The display system receives display data from the display data source. The frequency content of a plurality of display components in the display data is determined by the digital image processor. The digital image processor filters the plurality of display components based on the associated frequency content. In at least one embodiment, display components having lower frequency content are filtered to minimize flicker, while display components having higher frequency content are filtered to maximize resolution. The filtered display data is then transmitted to the display.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: March 23, 2004
    Assignee: ATI Technologies, Inc.
    Inventor: Philip L. Swan
  • Patent number: 6678003
    Abstract: Deinterlacing is applied to a composite video image that includes alternating even and odd rows of pixels. The even rows form a first image; the odd rows, a second image; these are recorded at different times, introducing a possibility of motion artifact. A first average horizontal intensity difference is computed between the first image and the second image. The first image is offset by one pixel in each horizontal direction to form a horizontally offset image, and another average horizontal intensity difference is computed. A minimum average intensity difference is determined from a comparison of the average horizontal intensity differences. The first image is shifted in a horizontal direction determined to achieve the minimum average horizontal intensity difference, and the horizontally shifted first image is combined with the second image to form an improved composite image. An analogous series of steps is carried out in a vertical direction.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: January 13, 2004
    Assignee: Alcon, Inc.
    Inventor: Gary Paul Gray
  • Patent number: 6667773
    Abstract: An apparatus and a method for format converting a video are provided, in which an input video is format converted in a horizontal direction according to a horizontal output size to store in a line memory and the image stored in the line memory is format converted in a vertical direction according to a vertical output size, such that the amount of line memory required for converting various kinds of videos including the high resolution video to videos of the NTSC or the standard screen quality video are minimized. An input video is format converted in the horizontal direction and a plurality of the divided lines are temporarily format converted by using a single horizontal format converting unit, so that the required hardware becomes reduced.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: December 23, 2003
    Assignee: LG Electronics Inc.
    Inventor: Dong Il Han
  • Patent number: 6657659
    Abstract: In a method of compensating an image signal (10) having a field frequency of substantially N times a mains frequency, in which N≧2, for AC light source induced fluctuations, the image signal (10) and an average signal representing an average image signal content over a given time period are arithmetically processed (14,16-20,8) to obtain a corrected signal (9), in which at least N−1 differences between at least N−1 respective phases of the corrected signal (9) on the one hand, and a selected phase (ph2) other than the N−1 phases of the corrected signal (9), or an average over N fields of the image signal (10), on the other hand, are integrated (14,16), and in which at least N−1 integrated differences are processed (20) to obtain a correction factor for the image signal (10).
    Type: Grant
    Filed: April 23, 1999
    Date of Patent: December 2, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Johannes H. J. M. Van Rooy, Antonius G. Moelands
  • Patent number: 6646684
    Abstract: One of an output picture signal with a field double speed of AABB type and an output picture signal with a field double speed of ABAB type is selectively generated with selection signals SL1 and SL2. In the AABB type, among first, second, third, and fourth output fields, the vertical pixel position of the second output field is the same as the vertical pixel position of the first output field. In addition, the vertical pixel position of the fourth output field is the same as the vertical pixel position of the third output field. In the ABAB type, among first, second, third, and fourth output fields that are chronologically successive, the vertical pixel position of the second output field deviates from the vertical pixel position of the first output field. In addition, the vertical pixel position of the third output field deviates from the vertical pixel position of the second output field.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: November 11, 2003
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Yasushi Tatehira, Masaaki Hattori
  • Publication number: 20030174246
    Abstract: A method for processing an image to convert a non-interlacing scan data into an interlacing scan data is disclosed. The method includes the steps of receiving a non-interlacing scan data, the non-interlacing scan data including plural pixels, replacing a color space value of a selected one of the pixels in the non-interlacing scan data with a combination of color space values of the selected one pixel and at least one adjacent pixel to obtain a blurringly filtered non-interlacing scan data, scaling the blurringly filtered non-interlacing scan data according to a specific algorithm, and converting the blurringly filtered non-interlacing scan data into an interlacing scan data. An image-processing device for converting a non-interlacing scan data into an interlacing scan data is also disclosed. The device includes a blurring filter, a scaler and a converter.
    Type: Application
    Filed: September 3, 2002
    Publication date: September 18, 2003
    Applicant: VIA Technologies, Inc.
    Inventors: Chuan-Chen Lee, Chia-Liang Tai, Yi-Chieh Huang
  • Patent number: 6597402
    Abstract: An interlaced television signal is derived from an interlaced 625 line, nominally 50 Hz field rate television signal, the derived television signal having perceived reduced line structure and reduced flicker. The field rate and the number of lines of the derived television signal are increased with respect to the field rate and the number of lines of the original television signal, such that perceived flicker and line structure in the derived television signal is reduced. The increase in the field rate and the increase in the number of lines in the derived television signal results in a horizontal scanning rate that does not substantially exceed twice the horizontal scanning rate of the original television signal while minimizing undesirable motion artifacts.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: July 22, 2003
    Assignee: Sage, Inc.
    Inventors: Donald S. Butler, Xu Dong, Jack J. Campbell
  • Publication number: 20030095204
    Abstract: An image data conversion processing device including an issue unit, plural line storing units, and a generating unit for converting to a television signal image data stored in plural kinds of developing formats in a storing unit. The image data comprises plural lines, and the television signal comprises a predetermined number of lines. The issue unit issues a transmission instruction of image data to the storing unit in accordance with a period specified by a ratio of the number of lines of the image data to be converted and the number of lines of the television signal. The plural line storing units cyclically store the image data transmitted from the storing unit line by line on the basis of the transmission instruction of the issue unit.
    Type: Application
    Filed: December 31, 2002
    Publication date: May 22, 2003
    Applicant: Fujitsu Limited
    Inventors: Makoto Nakamoto, Satoshi Nakamura, Akinori Takayama, Kazunori Takahashi, Akio Takigami, Yasuo Sato, Chiaki Ito, Yoichi Aoki
  • Patent number: 6563544
    Abstract: An apparatus and method for converting computer graphics images into a format suitable for display on a TV. A flicker filter is combined with a vertical scaling filter and/or vertical overscan compensation filter to produce an interlaced image formatted for display on a TV, more efficiently than if the processes occurred sequentially. The apparatus and method are not limited to any particular filter sizes or set of filter coefficient values. The apparatus and method may be used as part of a multimedia computer system.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: May 13, 2003
    Assignee: Intel Corporation
    Inventor: Maximino Vasquez
  • Patent number: 6563511
    Abstract: The present invention is a method and apparatus to generate an anti-flickered pixel from a source pixel having a source pixel value in a display memory. The apparatus comprises a plurality of storage elements, a filter, a comparator, and an output selector. The plurality of storage elements store a sequence of pixels in the display memory which includes the source pixel. The filter is coupled to the plurality of storage elements to filter the sequence of pixels. The filter generates a filtered pixel corresponding to the source pixel. The comparator is coupled to the plurality of storage elements to compare the source pixel value with a threshold value. The comparator generates a comparison result. The output selector is coupled to the filter and the storage elements to select one of the source and filtered pixels according to the comparison result. The selected one of the source and filtered pixels is the anti-flickered pixel.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: May 13, 2003
    Assignee: Teralogic, Inc.
    Inventors: Gerard K. Yeh, Anoush Khazeni
  • Patent number: 6545719
    Abstract: Progressive-scan video signals that are generated from interlaced-scan video signals by interpolation may be subject to temporal distortion when the interstitial interpolated lines have a different time reference than the interlaced lines. This distortion may be mitigated by detecting vertical low-frequency spatial distortion in an interpolated video signal and by generating a compensating signal that, when added to the interpolated video signal reduces that vertical low-frequency spatial distortion. A spatial low-pass filter is applied to corresponding pixels of several adjacent lines of the current field of the original interlaced image. Concurrently, a spatial low-pass filter is applied to corresponding pixels of several interpolated lines that are inserted between the lines of the interlaced image to produce the progressive image. At each pixel position, the low-pass filtered values are compared.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: April 8, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Robert J. Topper
  • Patent number: 6522362
    Abstract: An image data conversion processing device including an issue unit, plural line storing units and a generating unit for converting to a television signal image data stored in plural kinds of developing formats in a storing unit. The image data comprises plural lines, and the television signal comprises a predetermined number of lines. The issue unit issues a transmission instruction of image data to the storing unit in accordance with a period specified by a ratio of the number of lines of the image data to be converted and the line number of the television signal. The plural line storing units cyclically store the image data transmitted from the storing unit line by line on the basis of the transmission instruction of the issue unit.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: February 18, 2003
    Assignee: Fujitsu Limited
    Inventors: Makoto Nakamoto, Satoshi Nakamura, Akinori Takayama, Kazunori Takahashi, Akio Takigami, Yasuo Sato, Chiaki Ito, Yoichi Aoki
  • Publication number: 20030020830
    Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.
    Type: Application
    Filed: May 13, 2002
    Publication date: January 30, 2003
    Inventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen
  • Patent number: 6441858
    Abstract: An image data conversion processing device including an issue unit, plural line storing units and a generating unit for converting to a television signal image data stored in plural kinds of developing formats in a storing unit. The image data comprises plural lines, and the television signal comprises a predetermined number of lines. The issue unit issues a transmission instruction of image data to the storing unit in accordance with a period specified by a ratio of the number of lines of the image data to be converted and the number of lines of the television signal. The plural line storing units cyclically store the image data transmitted from the storing unit line by line on the basis of the transmission instruction of the issue unit.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: August 27, 2002
    Assignee: Fujitsu Limited
    Inventors: Makoto Nakamoto, Satoshi Nakamura, Akinori Takayama, Kazunori Takahashi, Akio Takigami, Yasuo Sato, Chiaki Ito, Yoichi Aoki
  • Publication number: 20020113899
    Abstract: A method and a system for improved filtering of display data is disclosed herein. A display system may be used to separately filter display components of the display data based on frequency content of the display components. The display system can include a display data source, a digital image processor, and a display. The display system receives display data from the display data source. The frequency content of a plurality of display components in the display data is determined by the digital image processor. The digital image processor filters the plurality of display components based on the associated frequency content. In at least one embodiment, display components having lower frequency content are filtered to minimize flicker, while display components having higher frequency content are filtered to maximize resolution. The filtered display data is then transmitted to the display.
    Type: Application
    Filed: February 22, 2001
    Publication date: August 22, 2002
    Inventor: Philip L. Swan
  • Patent number: 6417887
    Abstract: An image processing display apparatus for converting an image signal of an interlace system into a progressive scanning system and displaying an image, having means for conducting low band frequency passing processing so as to reduce flicker for a vertical direction signal component of a still picture signal component included in a video image signal, and means for synthesizing a still picture signal component to which the low band frequency passing processing is applied and a moving picture signal component included in the above-described video image signal to generate a progressive signal.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: July 9, 2002
    Assignee: NEC Corporation
    Inventor: Hirotaka Yamaji
  • Patent number: 6392718
    Abstract: A device and method for preventing flicker that occurs while displaying image data by attenuating a high-frequency portion of orthogonal transformed color signals of the image data. The present invention is also directed to a computer-readable recording medium on which a program for flicker prevention is recorded.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: May 21, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koji Muramatsu
  • Patent number: 6359653
    Abstract: A VGA to TV data transformation system uses a background-based adaptive flicker reduction method. Information in a picture displayed on a screen of a monitor is divided as graphic and video information. Graphic information which includes cursor, graphic data, and sub-picture of video data in video information is prone to flicker. A background-based adaptive flicker reduction is applied to pixels in regions containing graphic information. A current pixel and the adjacent pixels directly above and below the current pixel are used to compute Mean and Diff values. The background state of a current pixel is determined by comparing the Mean value with a threshold value. The background state, the Mean value and the Diff value are then used to select a flicker reduction mode that may be strong reduction, median reduction, mild reduction or no reduction. An anti-flicker pixel is generated according to the flicker reduction mode.
    Type: Grant
    Filed: June 22, 1999
    Date of Patent: March 19, 2002
    Assignee: Silicon Integrated Systems Corp.
    Inventor: Chien-Hsiu Huang
  • Patent number: 6346970
    Abstract: The invention is a flicker filter for use with video signals. The flicker filter of the invention has at least two user-adjustable inputs adapted to balance image quality versus flicker in the second video image. A first user-adjustable input is adapted to govern an amount of flicker suppression. A second user-adjustable input is adapted to govern an amount of blur, or sharpness. The two inputs are independently adjustable such that a user may dynamically adjust the two-dimensional system characteristics. This ability allows the circuit to be tune to adjust pixel intensities where an amount of pixel intensity adjustment increases with decreasing boundary angle, inter alia.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: February 12, 2002
    Assignee: Focus Enhancements, Inc.
    Inventor: Kenneth A. Boehlke
  • Patent number: 6327003
    Abstract: A method is provided for correcting flicker and flutter of an OSD on a video image. According to the method, values of pixels of the OSD are stored, pixels of lines of the OSD that are to be displayed without processing are substituted for pixels of the video image, and pixels of lines of the OSD that are to be displayed after processing are subjected to a mathematical filter. In the subjecting step, the value of another pixel of the video image is assigned to each pixel of the video image that is required by the mathematical filter but presently unavailable, with the other pixel belonging to the same column as the required pixel. In a preferred embodiment, the required pixel is a pixel of the video image that is not covered by the OSD, and the other pixel belongs to the closest line of the video image that is covered by the OSD. This makes it possible to simplify the use of mathematical filters associated with a unique equation for all of the lines of the overlaid OSD.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: December 4, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Mark Vos
  • Patent number: 6320619
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a flicker filter circuit. The flicker filter circuit has a configuration so that during filter operation two line buffers are employed to store partial sums of the filtered input digital signal samples. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: three line buffers, three multipliers, and three adders. The buffers, multipliers and adders are coupled in a circuit configuration so as to implement a flicker filter during circuit operation.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: November 20, 2001
    Assignee: Intel Corporation
    Inventor: Hong Jiang
  • Patent number: 6317158
    Abstract: When processing a time varying effect that positions an input image into an interlaced output image, the input image is filtered first. The filtered input image then is positioned in the output image by mapping one line in the output image to one line in the input image space. The input image may be filtered once and the filtered image may be used to create all output fields for the effect. Thus, the overhead per output field used to create the output field from the input image is reduced in comparison to filtered subpixel positioning. In addition, equipment that is capable of performing only unfiltered subpixel positioning may use the filtered input image to reduce interlaced artifacts.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: November 13, 2001
    Assignee: Avid Technology, Inc.
    Inventor: Raymond H. Tice
  • Patent number: 6297847
    Abstract: Visible artifacts introduced into a digitally sampled video signal are removed from a non-interlaced version of the video signal. The non-interlaced version of the video signal is generated by a converter that converts a digitally sampled interlaced video stream to a non-interlaced video stream. An artifact removal module responds to at least a first component of the non-interlaced video stream by adaptively modifying the first component of the non-interlaced video stream to reduce artifacts introduced into the non-interlaced video stream by the converter to generate a modified non-interlaced video stream.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: October 2, 2001
    Assignee: S3 Graphics Co., Ltd.
    Inventor: Eberhard H. Fisch
  • Publication number: 20010017666
    Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.
    Type: Application
    Filed: February 13, 2001
    Publication date: August 30, 2001
    Inventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen
  • Patent number: 6281933
    Abstract: A two-dimensional (2D) filter is disclosed that accomplishes flicker filtering with virtually no loss of image resolution. The 2D filter operates without adaption and only on the non-detail portions of the original image. The filter works first in the horizontal (x-axis) direction by separating the high-pass (detail, high-resolution) image elements from the low-pass (blurred, low-resolution) elements. A vertical (y-axis) flicker filter is applied to the low-pass elements and the result is summed with the high-pass elements. Thus, the detail elements are not subjected to flicker filtering and, as a result, remain well-defined while flicker is eliminated from the overall image.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: August 28, 2001
    Assignee: Chrontel, Inc.
    Inventor: David W. Ritter
  • Patent number: 6219101
    Abstract: A VGA to analog video converter is useful e.g. for displaying video and/or graphics data from a computer onto a large screen television or television monitor. The RGB video signals output from the personal computer are first converted to digital form. The analog-to-digital converter which does this is clocked by a clock signal generated by a phase-locked loop using the horizontal synchronizing signal from the personal computer. The digital RGB signals are then converted to a YCbCR format. A flicker filter eliminates the flickering appearing on the TV monitor by operating on the luminance (Y) component. The YCbCr signals are encoded into NTSC or PAL Standard, and output in composite analog video or S-VHS format. A color subcarrier synthesizer generates the color subcarrier signal to generate an accurate subcarrier frequency for the video output signals. An analog-to-digital clock phase adjustment is used to ensure that the input RGB signals are sampled at the proper instant by the analog-to-digital converters.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: April 17, 2001
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Mehdi H. Sani, De Dzwo Hsu, Willard K. Bucklen
  • Patent number: 6141056
    Abstract: A system processes an interlaced video image that contains at least a first line and a second line, where each of the first and second lines includes a plurality of pixels. The system generates an interpolated line with a plurality of interpolated pixels located intermediate the first and second lines. The system selects a first set of the pixels from the first line and selects a second set of pixels from the second line. The first set of pixels are fitted to a first function and the second set of pixels are fitted to a second function. Preferably, the first and second functions are quadratic and independent of each other. The system calculates a shift factor based on either the zero of a first derivative of the first function and a zero of the first derivative of the second function or a horizontal shift of a first edge feature in the first function and a second edge feature in the second function. Depending upon the system these two shift factor calculation factors may describe the same technique.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: October 31, 2000
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Larry Alan Westerman
  • Patent number: 6130723
    Abstract: The present invention provides a method and system for reducing flicker within an interlaced image. The method and system comprises identifying an area of the interlaced image where flicker needs to be reduced and adaptively adjusting a pattern of pixels derived from a non-interlaced spatial relationship of the interlaced image within the area based upon characteristics of the image. A flicker filter is provided which utilizes an adaptive technique whereby pixel-blending characteristics are constantly changed within the image depending on particular image attributes. It is unique in that high vertical resolution is maintained for detailed image content such as text and most graphics, while flicker is effectively reduced on image content that is flicker prone. The filter is based on psycho-visual studies and simulations performed by the company as well as numerous prior flicker filter implementations.
    Type: Grant
    Filed: January 15, 1998
    Date of Patent: October 10, 2000
    Assignee: Innovision Corporation
    Inventor: David Medin
  • Patent number: 6100934
    Abstract: An apparatus is disclosed to convert a non-interlaced computer graphics signal which consists of contiguous scan lines into an interlaced video signal which alternately consists of even fields and odd fields. The converting apparatus includes a receiving means, a low-pass filter and a line buffer. The receiving means sequentially receives a scan line. The line buffer stores the brightness signals of the first and the second scan lines before the received scan line. And the low-pass filter receives the sequential contiguous scan lines from the line buffer and the displaying scan line, weights the brightness signals of these scan lines and outputs the scan lines with the weighted brightness signal and a halved refresh rate to serve as the even field and the odd field of the interlace video signal.
    Type: Grant
    Filed: January 5, 1998
    Date of Patent: August 8, 2000
    Assignee: Winbond Electronics Corporation
    Inventors: Hsiung-Hao Liu, Rong-Chuan Tsai
  • Patent number: 6094226
    Abstract: A system and method for conversion of graphics from computer graphics formats to television formats is disclosed. More particularly, an improved scaling and flicker reduction system and method is disclosed for scaling personal computer (PC) graphics formats into different resolution television (TV) formats and for reducing flicker due to the conversion process of interlacing non-interlaced PC graphics to match interlaced TV formats. The scaling implementation reduces line buffer requirements by using a conditional scaling technique for converting graphics from a PC resolution format to a TV resolution format. The flicker reduction implementation provides a two-dimensional adaptive filter that selects between multiple filters so that different parts of an image may have different flicker reduction and different levels of trade off between flicker reduction and resolution.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: July 25, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Ligang Ke, Juergen M. Lutz
  • Patent number: 6084568
    Abstract: A device performs both 2-tap and 3-tap flicker filtering of non-interlaced lines of computer graphics data to form interlaced lines. The device includes a data packer, a data unpacker, and a filter circuit. The filter circuit combines lines that it receives to form filtered lines. The data packer writes the filtered lines to line buffers while the data unpacker reads the lines stored in the line buffers. The read lines are either sent to the filter circuit for further filtering or are outputted to be displayed as interlaced lines. Both 2-tap and 3-tap flicker filtering can be accomplished by varying the order and/or number of read, write, and filter operations.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: July 4, 2000
    Assignee: S3 Incorporated
    Inventors: Reena Premi, William S. Herz, Ignatius B. Tjandrasuwita
  • Patent number: 6072530
    Abstract: A television system (TV) with an interlaced display screen for displaying network application data. A flicker filter is preferably implemented as an infinite impulse response (IIR) filter to eliminate sharp transitions in the network application data images. A random access memory is used to store the lines of the filtered images and any adjacent lines used for the filtering operation. Alternate lines of the filtered images are retrieved from the random access memory to provide an interlaced image of the filtered network application data images. The interlaced images are displayed on an interlaced display unit of a television system.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: June 6, 2000
    Assignee: TeleCruz Technology, Inc.
    Inventor: Vlad Bril
  • Patent number: 6067120
    Abstract: A video signal conversion device of the present includes a flicker reduction section including a plurality of line buffers for storing data in accordance with an address thereof. The flicker reduction section receives non-interlaced signals, converts the non-interlaced signals to interlaced signals and performs a flicker reduction process.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: May 23, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Koji Horikawa, Hideaki Kawamura, Masayuki Ezawa
  • Patent number: 6064437
    Abstract: Video information which is organized in a first format is converted to a second format by first scaling the video information to produce scaled video information and then color correcting the scaled video information to produce color corrected video information at a network server. Scaling the video information may be accomplished by first applying a vertical scaling process to the video information to produce vertically scaled video information. Second, an anti-flicker filter may be applied to the vertically scaled video information to produce the scaled video information. The vertical scaling process includes a pixel-by-pixel conversion process wherein, for each group of six scan lines in a frame of the video information, color information for individual pixels which make up the group of six scan lines is scaled to provide color information for pixels in a corresponding group of five scan lines of a frame of the vertically scaled video information.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: May 16, 2000
    Assignee: Sharewave, Inc.
    Inventors: Michael H. Phan, Joseph D. Harwood
  • Patent number: 6061094
    Abstract: A method and apparatus is provided for the conversion of non-interlaced image data to interlaced image data while reducing flicker effects and simultaneously scaling the image data. A programmable discrete time oscillator (DTO) dynamically determines coefficients that are used in reducing flicker and vertical and horizontal scaling. The two functions are integrated which allow the flicker filter coefficient generated by the DTO to dynamically be modified and take into account desired vertical scaling. A similar DTO is provided to separately perform horizontal scaling using the dynamic coefficients.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: May 9, 2000
    Assignee: U.S. Philips Corporation
    Inventor: Michael Maietta
  • Patent number: 6055018
    Abstract: An image reconstruction system adaptively de-interlaces video stream content using image data comparison techniques when the interlaced input video stream does not contain pre-coded non-interlaced to interlaced conversion status data. In one embodiment, the system uses a signature generator which generates a plurality of field signature values on a per field basis by determining region values based on fluctuations in pixel data, such as luminance data within a horizontal scan line to detect changes in motion. The field signature values are then analyzed to determine a probability that the content is one of several types such as content that has undergone non-interlaced to interlaced conversion, such as pull down conversion for film captured content. Also, independent of whether conversion has occurred, the system analyzes the video streams to determine whether the video stream contains a paused image or slow motion playback of images and de-interlaces accordingly.
    Type: Grant
    Filed: November 4, 1997
    Date of Patent: April 25, 2000
    Assignee: ATI Technologies, inc.
    Inventor: Philip L. Swan
  • Patent number: 6008855
    Abstract: A flickerless television receiver displays image signals having the horizontal/vertical scanning frequencies thereof increased to two times the horizontal/vertical scanning frequencies of the broadcast signals to be received. Flickerless display performance can be confirmed with a single television receiver by generating signals to extract every other field for image displaying and showing two kinds of image signals, namely double-speed image signal and extracted image signal. A display unit displays double-speed image signals having horizontal and vertical scanning frequencies of image signals increased to two times by conversion, wherein extracted image signals formed by extracting every other field or frame from screen images are generated and two kinds of images formed of the double-speed image signals and extracted image signals are simultaneously displayed on one screen.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: December 28, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Ikai, Yoshihisa Uchida
  • Patent number: 6005630
    Abstract: A television system (TV) with an interlaced display screen for displaying network application data. Pixel data elements representing network application data display are received in a non-interlaced mode. The received data is filtered to reduce sharp transitions in the display. The filtered data is provided in an interlaced format (i.e., only alternate lines of a frame) for display on the television display screen. The interlaced image display is combined with the television signal display by selecting one of them on point by point basis. Flicker is reduced substantially in the final display of network application data due to the filtering.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: December 21, 1999
    Assignee: TeleCruz Technology, Inc.
    Inventor: Vlad Bril
  • Patent number: 6002442
    Abstract: The present invention discloses a system for adaptively reducing flickers in converting non-interlaced video signals to interlaced video signals. To preserve the original image quality in the non-interlaced video signals, the disclosed system examines the pixel values in at least two adjacent lines to decide if a reduction process should be turned on. If there is a need, the reduction process further examines the difference in the pixels from the adjacent lines to determine how to adjust a corresponding output to eliminate flickers in the resultant converted video signals. The adjusting means is based on an adjusting factor or the calculated difference between pixels which is further used in a function to eventually produce a converted interlaced signal with minimum visual errors.
    Type: Grant
    Filed: April 1, 1997
    Date of Patent: December 14, 1999
    Assignee: Aitech International Corp.
    Inventors: Jan-Kwei Jack Li, Huang-Jen Chen
  • Patent number: 5990965
    Abstract: An apparatus simultaneously flicker filters and vertically contracts a plurality of original lines to form compensated lines. The device uses a coefficient calculator and a line processor, both controlled by a controller. The coefficient calculator provides compensation coefficients to the line processor. The line processor forms weighted sums of the original lines, with the weightings determined by the compensation coefficients. The compensation coefficients are chosen to simultaneously implement flicker filtering and vertical contraction. Thus, the weighted sums are the compensated lines.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: November 23, 1999
    Assignee: S3 Incorporated
    Inventors: William S. Herz, Yichou Lin
  • Patent number: 5973746
    Abstract: An image data conversion processing device including an issue unit, plural line storing units and a generating unit for converting to a television signal image data stored in plural kinds of developing formats in a storing unit. The image data comprises plural lines, and the television signal comprises a predetermined number of lines. The issue unit issues a transmission instruction of image data to the storing unit in accordance with a period specified by a ratio of the number of lines of the image data to be converted and the number of lines of the television signal. The plural line storing units cyclically store the image data transmitted from the storing unit line by line on the basis of the transmission instruction of the issue unit.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: October 26, 1999
    Assignee: Fujitsu Limited
    Inventors: Makoto Nakamoto, Satoshi Nakamura, Akinori Takayama, Kazunori Takahashi, Akio Takigami, Yasuo Sato, Chiaki Ito, Yoichi Aoki
  • Patent number: 5963262
    Abstract: A system and method for conversion of graphics from computer graphics formats to television formats is disclosed. More particularly, an improved scaling and flicker reduction system and method is disclosed for scaling personal computer (PC) graphics formats into different resolution television (TV) formats and for reducing flicker due to the conversion process of interlacing non-interlaced PC graphics to match interlaced TV formats. The scaling implementation reduces line buffer requirements by using a conditional scaling technique for converting graphics from a PC resolution format to a TV resolution format. The flicker reduction implementation provides a two-dimensional adaptive filter that selects between multiple filters so that different parts of an image may have different flicker reduction and different levels of trade off between flicker reduction and resolution.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: October 5, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Ligang Ke, Juergen M. Lutz
  • Patent number: 5936675
    Abstract: A system for reducing flickers in converting non-interlaced video signals to interlaced video signals is disclosed. The non-interlaced video signals are first modified by two independent adjustable parameters, each having a different weight on the received signals. A FIFO line buffer is used to delay respectively and alternatively the two modified signals to generate a portion of output signals. The final output interlaced signals are generated by combining the delayed signal from the FIFO line buffer with one of the two modified signals. As a result and for the first time, only one FIFO line buffer is used in such system for producing a converted interlaced signal with minimum visual errors in video signal conversions.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: August 10, 1999
    Assignee: AI Tech International Corp.
    Inventors: Sunny Y. Zhang, Jack Jan-Kwe Li
  • Patent number: 5914753
    Abstract: A method and system is disclosed for scaling computer video in the process of scan rate conversion. In the disclosed system and method storage is provided for at least two lines of graphics pixels per video component composing the computer graphics signals and less than a full frame's worth of the graphics pixels. The graphics pixels are stored as they are provided so that the newest graphics pixels or a linear combination of the newest graphics pixels and stored graphics pixels overwrite previously-stored graphics pixels. In a repeating pattern for every RV VGA lines, where RV.gtoreq.2, television pixels composing the television video signals are generated from a weighted sum of the stored graphics pixels such that a different precomputed set of weights are used to compute the television pixels for each of the generated television lines.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: June 22, 1999
    Assignee: Chrontel, Inc.
    Inventor: Timothy J. Donovan
  • Patent number: 5910820
    Abstract: A method and apparatus for correcting the flicker artifact associated with noninterlaced to interlaced video conversion includes a Set-Interpolative-Threshold comparator function whereby weighted line averaging is used only if the difference in luminance, or other color component, of vertically adjacent pixels in the noninterlaced video exceeds a user set threshold value. When the differential value in luminance, or other color component, is greater than the threshold value, and such line averaging is used, the negative effects of the line averaging, such as blurring and darkening of the resulting video frame, are at least partially corrected by aperture/inverse aperture correction.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: June 8, 1999
    Assignee: S3, Incorporated
    Inventors: William S. Herz, Jon E. Graham
  • Patent number: 5907364
    Abstract: A display device for information signals which performs highly efficient image display of a standard television signal, a high definition television signal, a progressive scanning television signal or a stereoscopic television signal on the same screen has a first signal input unit applied with the standard television signal, a second signal input unit applied with the high definition television signal, progressive scanning television signal or stereoscopic television signal, a mode designation unit for designating a mode for display of one of the signals, a signal conversion unit including a write unit for writing the first signal, at a frequency thereof, to memories and a read unit for reading the memories at a frequency which is nearly twice that of the first signal, a signal switching unit, a signal processing unit and a deflection switching unit, whereby a first display signal from the signal conversion unit or a second display signal from the second input terminal is selected and image-displayed on the
    Type: Grant
    Filed: May 29, 1996
    Date of Patent: May 25, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Furuhata, Sadao Kubota, Shutoku Watanabe
  • Patent number: 5894330
    Abstract: An adaptive anti-flicker data conversion system for converting picture data in a video graphic adapter for displaying on a television. The conversion system reduces flickers adaptively according to the luminance of a pixel and neighboring pixels one line above and below. Contrast difference and mean value are defined based on the luminance of three neighboring pixels. A contrast ratio is computed by dividing the contrast difference by the mean value. Three threshold values are defined for examining the contrast ratio and selecting an appropriate anti-flicker filter. Pixels having higher contrast ratio are processed with filters having stronger anti-flicker effect. The adaptive anti-flicker method reduces flickers without blurring every pixel in the picture data.
    Type: Grant
    Filed: January 23, 1997
    Date of Patent: April 13, 1999
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Chien-Hsiu Huang, Ching-Mei Huang
  • Patent number: 5892551
    Abstract: A flicker reducing circuit that can prevent a degradation of an image by performing an outline blur correction together with a flicker reduction. In the flicker reducing circuit, a vertical contour detecting circuit detects an outline of the vertical component of a horizontal straight line. A switch selects an addition signal from the vertical low-pass filter for a period during which it is judged that an outline corresponds to the vertical component of a horizontal straight line according to the detection signal. The addition signal is obtained by adding the low-frequency component of a spatial frequency in a vertical direction to an output signal from the differentiating circuit. During other periods, the switch selects a delay display signal not subjected to a filtering process, output from the delaying circuit.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: April 6, 1999
    Assignee: NEC Corporation
    Inventor: Takeshi Uematsu