Abstract: In a method of expressing a gray level of a high load image and an apparatus for driving a Plasma Display Panel (PDP) using the method, a load ratio of the input image signal is calculated, and an error diffusion of a lower bit of gray level data corresponding to the input image signal is performed when it has been determined that the calculated load ratio is greater than or equal to a critical load ratio which is a lowest load ratio among the load ratios in which luminance at every gray level does not increase while the gray level increases at a low gray level area. The error-diffused gray level data is then displayed on the PDP.

Abstract: The present invention provides a solid-state imaging device which compensates a field curvature which occurs due to an aberration of the optical imaging system and surely receive light incident with a wide angle. Each pixel (pixel size of 2.2 ?m square) in a solid-state imaging device includes a light-transmitting film with the first effective refractive index distribution and a light-transmitting film with the second effective refractive index distribution, a light-receiving element, a wiring, a wavelength selection filter, and a Si substrate. A pixel (1) is a pixel placed an approximate center of the solid-state imaging device. A pixel (n) is a pixel placed in the periphery of the solid-state imaging device, and a pixel (n-x) is a pixel that are placed between the pixel (1) and the pixel (n). The light-transmitting film of each pixel has approximately same effective refractive index distribution. ?0, which is a main light angle on the light-receiving element side, is approximately same.

Abstract: A cathode ray tube display apparatus having a fly back transformer (FBT) to induce and output high voltage, the CRT apparatus including: a power controller controlling source power input into the FBT; a DC power detector to output a shut-off signal to shut off an operation of the power controller if the DC power detector is supplied with a direct current signal. The CRT display apparatus provides for normal operation of a system while protecting circuit components from abnormal operation of the system.

Abstract: The signal processing apparatus for setting a vertical blanking signal of the television set that allows to set the beginning position and end position of a horizontal blanking signal irrespective of the numbers of lines in the vertical synchronous signal interval, comprising: an up counter for counting the vertical synchronous signal interval, synchronizing with the horizontal synchronous signal to lock forcedly the interlace signal to become a non-interlace signal; and a down counter for loading and down counting the count value of the up counter, wherein the down counter loads the data of the up counter immediately before the up counter is reset at a timing of the vertical synchronous signal and down counts the data which is loaded in the down counter as the initial value.

Abstract: A method and circuit to strip the composite synchronization (sync) from a composite video signal is disclosed. This invention utilizes a phase-locked loop and a switchable input operational amplifier to remove the sync portion of the video signal without bandlimiting or introducing non-linearities to the video signal. The phase-locked loop creates a high frequency clock from which a signal can be created that fully encompasses the sync portion of the composite video signal. This signal controls the switchable input operational amplifier to select blank level voltage during sync or allow the video to pass when sync is not present.

Abstract: An apparatus and method are disclosed for generating timing pulses to control various functions in a video monitor including the switching of video amplifiers in cathode ray tube (CRT) devices, the control of the phase and frequency of phase locked loops, etc. Unlike previous methods, where switching is timed and controlled by monitoring the retrace voltage level, the system of the present invention monitors the change in direction of current in the retrace tuning capacitor. Monitoring the retrace capacitor current, provides an extremely accurate method for timing in horizontal deflection circuits. The apparatus of the present the invention comprises a small bead inductor placed in the current path of a horizontal retrace capacitor within the horizontal deflection circuit of the cathode ray tube device. Measuring the voltage across the bead inductor allows a very precise monitoring of the current through the retrace tuning capacitor.

Abstract: A blanking circuit generates a blanking signal by using a vertical fly-back pulse and/or an output signal of a vertical IC. The blanking signal is superimposed on a grid control signal obtained from a fly-back transformer and then provided to a grid control terminal of a CRT. The blanking circuit has an output signal stabilization part to generate a stable signal by restricting a peak value of a signal generated from the vertical IC within a predetermined limit, a pulse width extension part to widen a pulse width of a vertical fly-back pulse generated from the vertical IC and having a constant amplitude and a constant pulse width, and a blanking signal generating part to generate a blanking signal from the signal superimposing the stable signal on the vertical fly-back pulse having a wide pulse width. The blanking signal is superimposed on an output signal of a fly-back transformer and provided to a grid control terminal of the cathode ray tube.

Abstract: Disclosed is an image display screen controller for the control of a cathode-ray tube. There is produced a blanking logic signal that begins on a leading edge of the frame synchronization square-wave pulse and ends only on the trailing edge of the VFBACK signal generated from the frame flyback pulse without getting interrupted if the frame synchronization pulse and the pulse VFBACK corresponding to the frame flyback do not overlap. An RS flip-flop circuit is activated on the leading edge of the frame synchronization square-wave pulse VSYNC and is reset only by the trailing edge of the frame flyback pulse VFBACK. The output of the RS flip-flop is applied to an input of an OR gate that receives other inputs, notably the synchronization square-wave pulses and the line and frame flyback pulses. If the scanning disappears for example by the destruction of a transistor, the absence of a frame flyback pulse will prevent the reactivation of the beam and hence prevent a dot of the screen from being burned out.

Abstract: An arrangement for reproducing a composite blanking or sync signal includes a vertical deflection circuit having a supply boost stage. A first pulse voltage at a vertical rate is derived from an output signal of the boost stage. The vertical rate, first pulse voltage is coupled to a base terminal of an emitter follower via a voltage divider for producing a leading edge of an output pulse voltage of the emitter follower. The vertical rate first pulse voltage is also coupled via an R-C network to a regenerative switch. The regenerative switch is coupled to the base terminal of the emitter follower for producing a trailing edge of the output pulse voltage of the emitter follower. The trailing edge is produced after a predetermined interval has elapsed from the leading edge. The output pulse voltage of the emitter follower is combined with a horizontal rate pulse voltage for producing the composite sync signal.

Abstract: A circuit for displaying on the screen a mode frequency and screen control states of a monitor by using OSD letters is disclosed. The circuit delays the R, G, B signals of the OSD IC for a predetermined time until the output signals from the pre-amplifier are completely blanked according to a blanking signal of the OSD IC, to prevent the data received from the video card from being displayed on the screen during displaying the OSD letters on the screen, connects a mixer at a post-stage of the pre-amplifier, and further applies the horizontal flyback signal derived from the horizontal retrace pulse of the monitor to the pre-amplifier so as to allow the OSD signal level of the OSD IC to have the same level as the video signal level of the pre-amplifier, thereby preventing the degradation of the input characteristics and the undesirable change of the colors.

Abstract: A television receiver has a video muting processing function wherein a blanking added video signal is produced by superimposing on a video signal a blanking signal gradually varying in the width in the time direction and consists of a composite signal in which blanking signals are superimposed respectively on the front edge and rear edge of the video signal part.

Abstract: A dark level restoring circuit for a television receiver which receives a video signal, clamps a pedestal portion of the video signal to a reference pedestal level by a pedestal clamper, compares the output of the pedestal clamper with a reference dark level, and amplifies the compared result by a gain control amplifier. The output of the pedestal clamper and the amplified compared result are synthesized, the dark peak level is held, and the held dark peak level and the reference pedestal level are compared wherein the gain of the gain control amplifier is controlled by the compared result. A blanking signal is received, and a mute signal is generated which corresponds to a non-video signal portion when the effective raster size of the video signal is smaller than the size of a face plate of a cathode ray tube to which the video signal is supplied.

Abstract: The video muting apparatus is provided with a controlling apparatus which calculates the video muting time TM from the correlation between the power feeding time T1 counted by the first counter and the power feed stopping time T2 counted by the second counter and controls the operation of the switch on the basis of the calculated video muting TM. The switch will operate to be opened on the basis of the controlling signal from the controlling apparatus during the period from the starting time point when the power feed by the power supply circuit is started until the video muting time TM elapses and will operate to be closed on the basis of the controlling signal from the controlling apparatus immediately after the the video muting time TM elapses.