Abstract: An integrated circuit chip configured to be coupled to a single shared memory including, in combination, a memory access module, at least one video signal processing module, and a frame rate converter, wherein the memory access module is configured to coordinate access to the single shared memory by the at least one video signal processing module and the frame rate converter.

Abstract: The scan converter comprises first and second memories 3, 7, a frame memory 5; having a write period and a read period, a video data input circuit 2 for writing data at a first transfer rate into the memory 3, a video data output circuit 8 for outputting the data from the memory 7 at a third transfer rate. The transfer rate between the memories 3, 7 and the memory 5 is twice as fast as the first or third transfer rate, whichever is faster, and the memories 3 has data storage capacities greater than an amount of the data to be written into the memory 5 in each write period, and the memories 7 has data storage capacities greater than an amount of the data to be read from the memory 5 in each read period.

Abstract: An overtaking prediction method of, when input and output of data to and from a common memory are being performed with an input frame frequency and an output frame frequency made different from each other, predicting a frame in which overtaking occurs between the input and the output of the data to and from the memory. The overtaking prediction method includes a step of predicting the frame in which the overtaking occurs between the input and the output of the data, on the basis of a first parameter corresponding to a difference amount between a progress speed of a write address and a progress speed of a read address and a second parameter corresponding to a difference between a write address and a read address at an overtaking prediction point and to an offset address difference amount between an input offset address and an output offset address.

Abstract: An apparatus and method for displaying an out-of-range mode which has a resolution higher than a mode supported by a monitor is provided. The method for displaying an out-of-range mode in monitor displaying includes the steps of (a) sensing received horizontal and vertical synchronizing signals and determining a display mode, and (b) adjusting a sampling rate so that a received video signal is displayed in a supported display mode in a case where the display mode is a mode excluding a supported display mode as a result of determination in step (a). The out-of-range mode which has a resolution higher than a mode supported by an LCD monitor so that a user's system can be easily and conveniently converted into a supported mode without additional apparatus or equipment, can be displayed in the LCD monitor.

Abstract: One embodiment of the present invention provides a method that facilitates compression of video data in a computer system by performing the time-consuming task of computing the difference between successive frames of video data independently from the central processing unit. This frees the often-overburdened central processing unit from performing this time-consuming compression operation and can thereby improve the handling of video data. Thus, one embodiment of the present invention can be characterized as a method for compressing video data in a computer system. This method includes receiving a stream of data from a current video frame in the computer system. It also includes computing a difference frame from the current video frame and a previous video frame “on-the-fly” as the current video frame streams into the computer system. The method additionally includes storing the difference frame in a memory in the computer system.

Abstract: Disclosed are an apparatus and a method for compensating for an interlaced-scan type video signal for stably displaying the video signal in the LCD panel. An aft part of 264th data of a first field and a fore part of 23rd data of a second field are stored in memories. A present video signal is determined whether the present video signal is a first field signal or a second field signal through an equalizing pulse period. If the present video signal is the first field signal, a fore part of 23rd data is copied to the first data field, and if the present video signal is the second field signal, the aft part of the 263rd data is added to the second field data. In case of a PLA-type video signal, first data represent 23rd data, and final data represent 313rd data.

Abstract: A method of processing video data in a receiver/decoder including at least one port (31) for receiving data and memory means (40) including a data buffer area (45A0, 45A1) for storing incoming data for display, and a graphics buffer area (45Ai) for storing graphics data, said method including passing graphics data stored in the graphics buffer area to the data buffer area for combination with display data stored therein.

Abstract: One embodiment of the present invention provides an apparatus that facilitates compression of video data in a computer system by performing the time-consuming task of computing the difference between successive frames of video data. Thus, one embodiment of the present invention can be characterized as an apparatus for compressing video data. This apparatus includes a video input port, for receiving video data for a current video frame, and a video input buffer, for storing video data from the video input port. The apparatus additionally includes a previous frame buffer, for storing at least a portion of a previous video frame, as well as an operation unit, for performing an operation between video data from the video input buffer and video data from the previous frame buffer. The embodiment also includes a result buffer coupled to the operation unit, for storing the result of an operation from the operation unit.

Abstract: A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from an external memory. The video decoder requests to the memory controller to transfer the compressed video data using one of predetermined addressing patterns. The predetermined addressing patterns allow for more efficient transferring of the compressed video data to and from the external memory when compared to sequentially transferring a fixed number of data bytes starting at a fixed address. The use of the predetermined addressing patterns results in reading the compressed video data from the external memory in a predetermined order in a less number of clock cycles.

Abstract: A personal optical viewer enables a person to view images of how the person looks wearing an accessory and compare images of how the customer looks wearing different accessories. A seller provides an accessory to a person. A capturing device captures a photograph or a video of the person and stores the image in a memory device. The personal optical viewer displays each image to the person and the person chooses which images to keep, reject, delete, or compare. The personal optical viewer replaces rejected images with other images stored in the memory device, and when the stored images have been exhausted the personal optical viewer automatically enlarges the remaining displayed images.

Abstract: A double-rate signal achieved by subjecting a video signal to double-rate conversion is supplied to a scan line number converter. In the converter, the portion of the effective scan lines of the double-rate signal is written into a frame memory on the basis of a signal achieved by multiplying horizontal and vertical synchronous signals based on the double-rate signal. In the effective scan line section of HDTV signal, the video signal written in the frame memory is read out on the basis of horizontal and vertical reference signals based on'the HDTV signal. Out of the effective scan line section of the HDTV signal, a pedestal level signal written in a memory is read out on the basis of the horizontal and vertical reference signals based on the HDTV signal, thereby achieving HDTV signal whose vertical scan line number is equal to 1125 lines.

Abstract: The image processing apparatus according to the present invention comprises: DMA control means 112 having image input/output processing means 100, an external memory 111, DMA setting holding means 113, address generating means 114, DRAM control means 115, DMA request generating means 119, and DMA request adjusting means 120; a processor 116 including encoding/decoding processing means 117; and a DMA bus 118 as shown in FIG. 1. In the image processing apparatus so constructed, a transfer data group which can be previously subjected to DMA scheduling is divided into burst transfer units, and the DMA request generating means periodically issues the DMA request in the burst transfer units and performs DMA of the transfer data which cannot be subjected to the DMA scheduling during the period that the DMA of the transfer data is not performed, thereby avoiding concentration of specific DMA.

Abstract: Noise reduction is an important feature in consumer television. This is realized by spatial, temporal or spatio-temporal filters. Spatial filters require pixels from within one image, while temporal filters require samples from two or more successive images. The spatio-temporal filter unit (100) integrates spatial and implicit motion-compensated temporal noise reduction in one filter. For the motion compensation, no motion vectors are required. The spatio-temporal filter unit (100) is provided with a sigma filter (112) having one filter kernel (107) designed to operate on the pixels from both a current image and from the output of the spatio-temporal filter unit, being a temporally recursive filtered image. The operation of the spatio-temporal filter unit (100) can be adjusted by varying the thresholds of the sigma filter (112) and the selection of pixels. The adjustments can be controlled by a motion estimator (222), a motion detector (224) and a noise estimator (220).

Abstract: One embodiment of the present invention provides an apparatus that facilitates compression of video data in a computer system by performing the time-consuming task of computing the difference between successive frames of video data. This frees the often-overburdened central processing unit from this time-consuming compression operation and can thereby improve the handling of video data. Thus, one embodiment of the present invention can be characterized as an apparatus for compressing video data. This apparatus includes a video input port, for receiving video data for a current video frame, and a video input buffer, for storing video data from the video input port. The apparatus additionally includes a previous frame buffer, for storing at least a portion of a previous video frame, as well as an operation unit, for performing an operation between video data from the video input buffer and video data from the previous frame buffer.

Abstract: The invention relates to a process and a device for time-managing the utilization of data detected in a data flow and constituting a data set. The device comprises a circuit (MP) for calculating a minimum duration of utilization of the detected data, which is proportional to the amount (L) of data contained in the data set. The invention applies more particularly to the case in which the detected data are digital data representing subtitles detected in a flow of data conveyed according to the MPEG 2 System transport standard. The utilization of the data then corresponds to the displaying of the subtitles.

Abstract: A memory circuit achieves much higher bandwidth and reduced power consumption by maintaining the maximum number of memory arrays open simultaneously. Circuit area is also saved by sharing bit line sense amplifiers between adjacent arrays. When selected, an array remains open until a different row in the same array or an array adjacent to it is selected. Thus, as long as access is made to an open row of every other array, access time and power are reduced by eliminating the need to turn arrays on and off.

Abstract: A picture processing apparatus is composed of a plurality of picture processing systems. Each picture processing system includes an identical picture processing IC (integrated circuit) and a plurality of memories each capable of memorizing a picture frame and including at least two memories operating at different timings. The picture processing IC includes a picture processing unit, an operation timing signal generator, a plurality of control timing signal generators for controlling different memories, and a memory control signal selection circuit for selectively outputting one of at least two memory control timing signals. As a result, the number of output pins of each picture processing IC for outputting memory control signal can be reduced, whereby the picture processing apparatus can be produced at a lower cost while retaining an identically large size of the picture processing ICs.

Abstract: In a video-processing unit comprising a processing means, memory means and a memory manager, an output of the processing means is coupled to the memory manager for storing of the processed data from the processing means in the memory means to allow execution of different processes in video-processing unit by a single processing means.

Abstract: A method and a circuit arrangement for picture-in-picture insertion are described, in which, in order to prevent a write operation from being overtaken by a read operation and also to avoid the associated picture disturbances, a field is stored under an address which precedes a previous field by a number of N lines. A read address is then shifted to the same line of the older field in the event of a minimum distance to a write address being undershot.

Abstract: Television receiver furnished with a memory (21, 22, 23) for receiving service data comprising a processing module (11) which correlates usage criteria received together with the service data and storage criteria characterizing the memory or memories of the receiver. By correlating the two criteria, the module determines the conditions of storage. Advantageously, a reorganizing module (12) can process the content of the memory so as to free some space in order to store new service data. The invention also relates to the storage process.

Abstract: A method for picture-in-picture insertion is described, which is distinguished in particular by the fact that the inset pictures are written to a memory device (2) in a circulating manner under continuously incremented write addresses, the first and last address of each written-in inset picture is stored, an overtake signal is formed by comparing the instantaneous address with the previously stored address, said signal indicating whether a previous address has been reached again and, consequently, the corresponding picture content has been overwritten, by evaluation of the overtake signal, the current or preceding segment is selected for read-out depending on whether or not overtaking took place before the start of the read-out, and the inset picture stored in the selected segment is read out with continuously incremented read addresses and is inserted into the main picture. A corresponding circuit arrangement is also described.

Abstract: A picture data memory device which can be used universally comprises a central picture data memory for storing picture data of a plurality of picture data input channels, in which case the stored picture data can additionally be read out via a plurality of picture data output channels for different kinds of further processing. A memory controller is provided for coordinating the individual storage operations of the picture data input channels and the individual rend-out operations of the picture data output channels.

Abstract: A video apparatus with image memory function has a memory of three ports (one for write, two for read), memory read control units corresponding to two independent read ports and adapted to read a desired area (first area) from a first read port and an area (second area) which contains the first area and is wider than the first area from a second read port, and a memory write control unit. With this construction, an input video signal is written to the memory, starting with a write head address designated by the memory write control unit, the first and second fields to be read during the next field are determined during the period of vertical blanking, a next write head address is determined to be after the first area, and a signal of the first area is delivered as an output video signal.

Abstract: A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).

Abstract: A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.

Abstract: Apparatus and method for data transmission while performing encoding processing on a non-limited moving vector mode, which avoids an increase in required memory capacity and a reduction in processing load, the apparatus comprising a two dimensional address generating unit for generating an access address of an external memory and an address control unit for administrating the horizontal position and the vertical position of the extended logical space and generating an operation authorizing signal for the two dimensional address generating unit, and the two dimensional address generating unit and the address control unit are operated in relation to each other so that an access address to outside the effective video data region is controlled to be an address of a pixel data at the periphery of the effective video data region, thereby reducing the extended region in the external memory.

Abstract: A cache memory system for use in a motion estimation system is disclosed. The system includes: a first cache memory defined in terms of a first width and a first height, and a second cache memory defined in terms of a second width and a second height, wherein said second height is less than said first height, the cache memory system being operable in one of two modes: the first mode being characterized by banks of memory from the second cache memory being concatenated vertically such that their concatenated height is at least equal to the first height, and said concatenated banks being arranged to be appended to the width of the first cache memory to form a single contiguous address space; and the second mode being characterized by banks of memory from the first and second cache being stacked vertically, and being arranged to be addressed as two separate address spaces.

Abstract: Imaging apparatus having a video memory function includes a video memory having a plurality of read ports and a capacity of storing images in two fields or more, wherein CCD storage sensitivity enhancement means is connected to a write port; a write control circuit for storing a single-field image in each memory area provided by dividing the storage space of the video memory into a plurality of sub-spaces; a plurality of read control sections for reading a single-field image stored in each memory area; and memory control means for reading an image from the video memory by a delay amount corresponding to the timing of a synchronization signal from the CCD storage sensitivity enhancement means. This configuration allows adjustment of the delay amount and prevents an image write address from passing by an image read address so that image data given CCD storage sensitivity enhancement is processed normally.

Abstract: A method of rapidly generating motion vector predictions based on vertical and horizontal position categorization of macroblocks within a video object plane (VOP) for use within a video decoder or encoder. By way of example, the location of the subject macroblock is categorized vertically as either Upper_Edge or Not_Upper_Edge, and horizontally as either Left_Edge, Right_Edge, or Not_Edge. The position categories are utilized in conjunction with selected block number (Block1 through Block4) within the luminance macroblock within a decision-tree which generates three predictors MV1, MV2, and MV3. The prediction rules may be implemented within hardware, software, or combinations thereof, within both video encoders and decoders, such as according to the MPEG-4, H.263, or similar standards.

Abstract: Two memories respectively have memory capacities which are half of a memory capacity required to store data for one line. In a first time-period of a preceding line is read from a first address of the first memory. In a second time-period dot data of a current line is written in that first address, and data of the preceding line is read from a first address of the second memory. In a third time-period, data of the current line is written in the first address of the second memory, and data of the preceding line is read from a second address of the first memory. This is repeated for all current line data. Therefore, reading of the dot data of the preceding line stored in one memory and the writing of the dot data of the current line to another memory is performed in the same time-period.

Abstract: A method of implementing on screen display (OSD) function and a device thereof are provided. The method includes the steps of storing the graphic data in a dynamic random access memory (DRAM), obtaining the displaying information and a sequence for the graphic data by an OSD decoder, and showing the graphic data by an address generator on a screen according to the displaying information and the displaying sequence. The device includes a dynamic random access memory (DRAM) for storing the graphic data, an OSD decoder for obtaining a sequence according to the stored graphic data, and an address generator electrically connected to the DRAM and the OSD decoder for showing the graphic data on a screen according to the sequence.

Abstract: A memory controller is provided that has an access priority arbiter having a memory address bus and a memory data bus for connection with one or more memories and a plurality of requester buses, each for connection to a memory requester. It also has a RAM controller for connection with a RAM connected to the memory data and address buses and/or a ROM controller for connection with a ROM connected to the memory data and address buses. Each such RAM controller and/or ROM controller are connected to the access priority arbiter with one or more control lines. The access priority arbiter receives access requests on one or more of the requester buses and grants access to the memory address and data bus to one requester bus at any one time based on logic internal to the access priority arbiter.

Abstract: The present invention provides an image processing apparatus and an image processing method. The image processing apparatus includes: a first to a fourth writing FIFO unit and a first to a fourth reading FIFO unit (hereinafter referred to as “FIFO units”) for temporarily retaining image data to write to and read from a data retaining memory; a memory access control unit for performing access to the data retaining memory, the access being requested by the FIFO units; and a writing data control unit for shifting, at all times by a predetermined time, timing of the request made by at least one of the FIFO units to the memory access control unit in comparison with timing of the request made by the other FIFO units to the memory access control unit.

Abstract: A multi-standard channel decoder for real-time digital broadcast reception has a plurality of processors connected to a sample-based communication unit for sample-based processing and connected to a block-based communication unit for block-based processing. The channel decoder is able to use the same processors to channel decode sample-based transmissions such as 8-VSB broadcasts and block-based transmissions such as COFDM broadcasts.

Abstract: Plural encoders operating in parallel to achieve a desired data rate have their respective outputs combined by an autonomously operating arrangement for transfer of data to a direct memory access arrangement from respective encoders in order in response to a signal asserted upon completion of encoding and output of encoded data corresponding to a predetermined portion of input data. buffering of encoder output can be either internal or external to the encoders. Zero bytes which may be inherently generated at the beginning and end of an encoder output stream may be suppressed to improve encoded signal quality and efficiency.

Abstract: A method and apparatus are disclosed for capturing and storing digital high definition television signals. The signals are taken from an input device in 8-bit parallel fashion at a constant flow rate and put into each of four 8-bit first in-first out memory registers until they are half full. After the respective first in-first out memory registers are half filled, additional quantities of data equal to half filling the registers are added while the data from the first half register filling is presented to the system memory as 32 bit words. That data is filled into a first of two concurrent blocks of system memory and after the first block is filled, while the second block is filled, the data is written from the first of the two concurrent blocks into another part of the system memory. The transfer of the 32-bit data words is accomplished at a faster rate than the input rate of the 8-bit data.

Abstract: During image processing of video pictures, it is generally necessary to have fast, repeated access to adjacent picture blocks. Picture memories with a sufficient capacity to store complete video pictures do not have the necessary access time to perform image processing in real time. The invention therefore provides for the writing of picture blocks from a picture memory to a fast access memory. Only the pixels in the access memory are accessed when the image processing operation is performed. During the read-out, a further block from the picture memory is simultaneously read into the access memory. As a result, fast access to the picture data is possible in conjunction with little additional outlay in respect to memory. Areas of application for the method are in the image processing of video pictures.

Abstract: In a method of controlling a memory (5) to allow for a display of at least two images, write and read speeds of writing image data into and reading image data from the memory (5) are measured (9-15) to predict a crossing where a write action overtakes a read action or reversely, where a new field of said image data is written (13, 3) into the memory (5) from a same initial position as from which a previous field of the image data was written into the memory (5) if no crossing is predicted, and the new field of said image data is written (13, 3) into the memory (5) from an end position in the memory (5) at which an end of the previous field of the image data was written into the memory (5) if a crossing is indeed predicted, the memory (5) having a size being larger than that needed for one field but less than that needed for two fields of the image data at its largest read-out size.

Abstract: The invention provides a synchronizing conversion apparatus wherein outpacing compensation can be executed with a circuit construction including a comparatively small number of components. A read control circuit produces a read control signal including a read address and a read timing based on an outpacing detection signal from a phase comparison circuit, which is generated taking a time required for processing of a memory access arbitration circuit into consideration, and a scene change detection signal from a scene change detection circuit. The read control signal is outputted to the memory access arbitration circuit. The memory access arbitration circuit arbitrates requests from a write control circuit and the read control circuit to control writing into and reading out from a frame memory.

Abstract: Memory requirements in a video processor and display system are reduced by storing in memory processed video signals for a plurality of regions of a picture, processing video signals for additional regions of a picture while stored video signals are retrieved in controlling a display, and then storing the newly processed video signals in the memory space occupied by the retrieved video signals. An entire reconstructed frame of image signals is not needed in order to begin the display of the same frame, certain regions of the frame can be displayed while other regions are still being reconstructed. Overwrite protection is provided for stored image signals until the stored image signals are retrieved for image display.

Abstract: An information processing apparatus includes an address generation circuit for generating an address signal. A memory operates for storing an information signal containing a video signal in response to the address signal. The address signal is periodically updated. A compression processing circuit operates for reading out the information signal from the memory, and subjecting the readout information signal to a compressively encoding process. A head of every frame represented by the information signal is detected. A state of the address signal is stored which corresponds to the detected frame head. Detection is made as to whether or not the information signal becomes discontinuous. The updating of the address signal and also the operation of the compression processing circuit are suspended when it is detected that the information signal becomes discontinuous. Detection is made as to whether or not the information signal returns to a normally continuous state after the information signal becomes discontinuous.

Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.

Abstract: An embodiment of the present invention provides a system and method for adaptive resource access priority allocation. A method for adaptive resource access priority allocation includes determining whether a resource constrained mode is to be initiated, and responsive to a determination that the resource constrained mode is to be initiated, initiating the resource constrained mode, including modifying a resource access priority. For example, adaptive resource access priority allocation may include increasing the priority for graphical data transfer during intervals of high demand for memory and/or bus bandwidth resources.

Abstract: Under some circumstances, it is necessary to contiguously displaying pictures stored in one display buffer. In order to solve the problem mentioned above, the present invention discloses a method for reordering a decode order into a display order of images by inserting virtual pictures to minimize hardware and software cost.

Abstract: A method for storing video frame data in a memory includes the steps of: sequentially receiving the video frame data; dividing the video frame data into a first part and a second part; storing the first part in the memory; storing the second part in the memory while the stored first part is read from the memory for a certain purpose; and reading the second part stored in the memory for the certain purpose.

Abstract: A video compression technique is provided which reduces motion estimation computations. A digital signal processing system employs external memory. Detection speed is improved by loading a succession of refined search windows are loaded on-chip. By so doing, the search involves fewer accesses to external memory and so completes in a shorter amount of time.

Abstract: Memory requirements in a video processor and display system are reduced by storing in memory processed video signals for a plurality of regions of a picture, processing video signals for additional regions of a picture while stored video signals are retrieved in controlling a display, and then storing the newly processed video signals in the memory space occupied by the retrieved video signals. An entire reconstructed frame of image signals is not needed in order to begin the display of the same frame, certain regions of the frame can be displayed while other regions are still being reconstructed. Overwrite protection is provided for stored image signals until the stored image signals are retrieved for image display.

Abstract: Picture data read out from a VRAM 18 are sent via line buffers 75a to 75d to a selection synthesis unit 63. The line buffer 75d receives picture data supplied from outside for sending the received picture data to the VRAM 18. The VRAM 18 can write the picture data from outside supplied via the line buffer 75d and read out the picture data based on addresses from a controller in the same way as other picture data. On the other hand, cache memories 74a and 74b can read out picture data under control by the controller 71 to display plural pictures in a tiled pattern on a display screen.

Abstract: Device and method for transposing a matrix of video signals, is disclosed, the device including a memory part, a write control circuit for shifting and writing rows of the matrix of video signals on the memory part by any one unit either of a row unit or column unit, and a read control circuit for shifting and reading the matrix of video signals stored in the memory part by one unit different from the unit in the writing either of the row unit or the column unit,with rows of a matrix of video signal received at the next time written on a portion of the memory part emptied due to the shift in the reading.

Abstract: In the speckled broadcasting of HDTV and SDTV, an encoding transmitting apparatus and a decoding receiving apparatus can perform a parallel multichannel transmission and reception of SDTV with a simple construction. When an HDTV video signal is encoded and decoded, each of the transmission buffer 30 and the reception buffer 80 is used as a single buffer. On the other hand, when a plurality of SDTV video signals are encoded and decoded, the transmission buffer 30 and the reception buffer 80 are divided into the number of SDTV video signals to use them as a plurality of divided transmission buffers and a plurality of divided reception buffers, so as to perform a encoding and decoding processing.