Abstract: Disclosed is a substrate processing device which includes a substrate transfer part on which a transfer object is received and a jetting system part includes an ink jet body that jets and prints ink on the transfer object over an upper surface of the substrate transfer part, an ink module transfer part that transfers the ink jet body, an encoder disposed around the ink module transfer part to output a movement signal per unit movement distance of the ink module transfer part, an ink ejection controller that interworks with the ink jet body to control an ink jetting timing of the ink jet body, and a signal splitter that interworks with the encoder to count the movement signal, reset a width of the counted movement signal, and transmit the movement signal, the width of which is reset, to the ink ejection controller.

Abstract: A method and system are provided for data driven shrinkage compensation. The method includes calculating, by at least one processor operatively coupled to a memory device, one or more dimensions of an object modeled in a file from one or more directional strands disposed between facets of one or more predetermined facet pairs. The method further includes predicting, by the processor, dimensional changes in the one or more directional strands as a result of the fabrication of the object using an additive manufacturing process based on a shape shrinkage model. The method further includes correcting, by the processor, coordinate data of at least one facet of the one or more predetermined facet pairs to compensate for the one or more predicted dimensional changes in the one or more directional strands.

Abstract: A system and method for compensating for detected phase errors during communications between synchronized devices. In an embodiment, the two devices may be a touch screen device and a synchronized stylus device. To this end, the touch screen device includes a controller configured to receive data signals from the stylus at specific time intervals. The touch screen device generates an internal control signal for receiving the incoming data signals at an expected frequency. The touch screen device further includes circuitry for measuring differences in the time a data signal is actually received against when the data signal was expected to be received and determines a time difference (e.g., a phase error). Then, the internal control signal may be adjusted to compensate for the accumulated phase error. Such a measurement and compensation helps ensure that communications remain in synchronization without having to reestablish synchronization through a cumbersome synchronization process.

Abstract: A data interface is provided for point-to-point communications between two devices, such as a read channel and a disk controller in an HDD system. An interface for communications from a transmitting device to a receiving device comprises a data bus configured to communicate m bits of data and a corresponding n bit data tag, wherein a given n bit data tag identifies a data type of a corresponding m bits of data on the data bus. An acknowledge signal from the receiving device optionally indicates that data on the data bus has been received and that the data on the data bus can be changed to a new value. A valid flag optionally indicates when a new predefined m-bit data value and corresponding n-bit tag value are on the data bus.

Abstract: A pulse width modulation technique is disclosed for use in an image forming device such as a laser printer or a photocopier. The technique implements a pacer to synthesize the frequency of a serializer circuit by stretching (or shrinking) pixel pulse train data. The pacer stretches the pixel pulse train data in accord with increment data that is based upon information about the image forming device, such as the number of bits in the pixel pulse train data, the number of bits in print engine pulse train, the target print engine frequency, and the serializer frequency. The technique can be implemented with digital circuits that provide digital test data.

Abstract: When receiving data in a unit of frame, each frame including a plurality of bits, based on a spread clock signal, a receiving time per bit of receiving data is calculated based on a receiving rate, and the change cycle of the spread clock signal is adjusted according to the receiving time per bit.

Abstract: An image forming apparatus includes a profile storage section that stores distortion characteristic of a scanning line, a correcting section that corrects image data by lines in the sub scanning direction, and a registration sensor that detects a pattern image for detecting color misregistration amounts in a sub scanning direction of images formed on an intermediate transfer member. When the pattern image is formed, the distortion correcting section shifts image data of the pattern image by lines in the sub scanning direction so that, with reference to a detection position of the registration sensor, a positional displacement amount of the pattern image in the sub scanning direction becomes less than or equal to ½ of a scanning-line distance, in accordance with a positional displacement amount of the scanning line in the sub scanning direction at a detection position of the registration sensor along a main scanning direction.

Abstract: A method and apparatus for printing using a synchronization signal are provided. Printing processes are performed in the apparatus by determining points in time for performing the printing processes based on a synchronization signal so that it is possible to reduce a waiting time for printing.

Abstract: An image processing apparatus includes a plurality of circuit configuration units, each of which can be reconfigured into one of a plurality of types of circuit configurations, and reduces the overhead incurred in the switching time period by fixing a circuit configuration of an optimal type in accordance with the frequency of appearance of pixel data having a certain attribute in a plurality of pixel data and the number of times of switching of the attribute of the pixel data from one to another.

Abstract: A processing system may include a server group connectable to an image forming apparatus, a request processing unit, a backend processing unit, a receiving unit, a determination unit, and a sending unit. The receiving unit receives information relating to a document file corresponding to a processing request from the image forming apparatus. If the determination unit determines that that the processing method is a synchronous processing method, then the request processing unit processes the document file based on the processing request. If the determination unit determines that that the processing method is an asynchronous processing method, then the request processing unit requests the backend processing unit to process the processing request. After the document file has been processed according to the determined processing method, the sending unit sends a notification to the image forming apparatus that the document file has been processed.

Abstract: An image forming apparatus capable of performing control so as to prevent a line registration error from occurring, even if a timing to start counting a positional deviation becomes different between color plane images. A BD identification unit of the image forming apparatus identifies whether a main scanning sync signal is a sync signal for odd-numbered line or for even-numbered line, and outputs a first or second timing edge signal. According to the timing edge signal, a sub-scan timing controller controls an output timing of an image signal to a printer controller. When the top of a page is detected based on the timing edge signal first input from the BD identification unit, the sub-scan timing controller is made enabled. If the first timing edge signal is subsequently input, the image signal output timing is controlled according to the second timing edge signal which is next input.

Abstract: Conventional analog front ends or AFEs for scanners are implemented using multiple integrated circuits or ICs. As a result, there is typically a problem of skew (due at least in part to manufacturing process variations) for these different ICs in the AFE. Here, an AFE is provided which serializes input data so as to compensate for skew.

Abstract: A disclosed control device includes a first unit configured to generate image data of multiple images to be superposed one on the other to form a single image and transmit the image data. The second control unit transmits to the first control unit a horizontal sync reference signal for achieving synchronization of the images in a horizontal direction. Based on the horizontal sync reference signal, the first control unit transmits to the second control unit a transfer clock signal that indicates transmission timing of the image data and an effective area signal that indicates an effective area of the image data. The first control unit asserts the effective area signal for an effective-area-signal assertion period that occurs between two consecutive reference-signal assertion periods during which the horizontal sync reference signal is asserted.

Abstract: A pulse generator with a filter section limiting a band of an input signal, and a pulse generating section generating a plurality of pulses which are sequentially delayed one after another by a time period (?) substantially equal to a reciprocal of a center frequency of the band of the filter section, and inputting the plurality of pulses to the filter section.

Abstract: An image scanning device includes a CCD pair provided with two rows of photodiode arrays for scanning an image on a paper, a motor drive circuit for causing the CCD pair to sub-scan the image on the paper, and an adder for superimposedly combining two outputs of the CCD pair with a predetermined time lag therebetween. A control unit controls the adder to add the two outputs of the CCD pair without the time lag when received an instruction of a low resolution that corresponds to ½ of a high resolution by a resolution switch and thereby doubles a speed of the sub-scan by the motor drive circuit.

Abstract: A method and apparatus for printing using a synchronization signal are provided. Printing processes are performed in the apparatus by determining points in time for performing the printing processes based on a synchronization signal so that it is possible to reduce a waiting time for printing.

Abstract: A delay-type phase adjusting circuit including a first variable delay circuit for receiving a reference clock signal and adding a delay to the reference clock signal, for output a phase comparator for receiving an output of the first variable delay circuit and the reference clock signal and detecting a phase difference therebetween a control circuit for generating a control signal for variably controlling a delay value of the first variable delay circuit based on a result of phase comparison by said phase comparator a second variable delay circuit for receiving an input signal and adding a delay to the input signal, for output a computation circuit for receiving a predetermined value and the control signal and variably controlling a delay value of the second variable delay circuit.

Abstract: The present invention relates to an image processing method, an image processing apparatus and an image processing program for dealing with inverted characters (outlined characters) constituted by white pixels on a black ground in a tree structure same as that of normal characters constituted by black pixels on a white ground. In the present invention, black pixel blocks and white pixel blocks are sampled recursively from a binary image, tree structure data indicating a positional relation between the sampled black pixel blocks and white pixel blocks is created, an inverted image is created by white-black-inverting the insides of black pixel blocks that can include inverted characters, of black pixel blocks included in the tree structure data, white pixel blocks and black pixel blacks are sampled from the created inverted image, and data regarding the sampled white pixel blocks and black pixel blocs is added to corresponding nodes of the tree structure data.

Abstract: A sync detection device and method for a GNSS receiver. In modernized GNSS, each satellite transmits a data signal and a pilot signal. Correlations are performed between a data symbol stream converted from the data signal with possible hypotheses to find a leading edge of a frame of the data signal (i.e. frame sync detection) and between a pilot symbol stream converted from the pilot signal with possible hypotheses to find a leading edge of a code sequence of the pilot signal (i.e. pilot sync detection). The possible hypotheses for the frame sync detection are selected according to a result of pilot sync detection when pilot sync is done. Frame sync can be efficiently achieved since a range of the selected possible hypotheses is quite limited.

Abstract: In a multiplied pulse generation device, a detection signal is outputted every time a driven object is driven by a specific amount. An actual cycle indicating a time interval between the detection signal and a previous detection signal is measured. An estimated cycle is estimated based on at least past two actual cycles including the actual cycle measured. A multiplied pulse is sequentially generated in such a manner that a multiplied cycle indicating a time interval per which the multiplied pulse is generated is sequentially changed according to an amount of change from the actual cycle to the estimated cycle.

Abstract: An image forming apparatus using a synchronization signal generator can easily generate a pixel clock that enables both a magnification correction in a main scanning direction and a correction of expansion and contraction of pixel width in the main scanning direction. Each of pixel clock generation units generates a clock signal by dividing a frequency of a high-frequency clock so as to generate pulses of a reference period, a long period longer than the reference period and a short period shorter than the reference period, and outputs, as the pixel clock, one of the pulses that is designated by an output selection signal. A pixel clock correction data synthesizing unit synthesizes a first selection signal, which is generated base on a time-series distribution of the pulses of each period defined by a first set of data, and a second selection signal, which is based on a time-series distribution of the pulses of each period defined by a second set of data, so as to generate the output selection signal.

Abstract: Data is recovered in an asynchronous environment where a sampling clock is generated internally, and is not externally frequency locked, by using programmable delay modules each providing a number of delay tap outputs. To recover data, two of the delay modules are used with a first delay module designated as a monitor delay module to monitor the clock edge transitions, while a second delay module is designated as a data delay module that provides a data output. A controller provides for incrementing or decrementing the tap delay of both delay modules to assure clock data falls at the center of the monitoring window as determined using the monitor delay module. The controller further selects between the two delay modules as to which provides data and which is used as for clock edge monitoring when the clock edge transitions drifts to an edge of the monitoring window.

Abstract: A sampling-error phase compensating device and a method thereof for sequentially sampling data signals and outputting sampled data signals.

Abstract: A multimedia processing system and method thereof are provided. The system and method provide for synchronizing a first clock of a multimedia decoder of a first multimedia processing device to a second clock of a multimedia encoder of a second multimedia processing device, synchronizing a first timing reference of the multimedia decoder to a second timing reference of the multimedia encoder, receiving, at a network interface of the first multimedia processing device, an encoded multimedia data stream from a network interface of the second multimedia processing device, wherein the encoded multimedia data stream is encoded by the multimedia encoder based on the second clock and the second timing reference, and decoding the encoded multimedia data stream at the multimedia decoder based on the first clock and the first timing reference.

Abstract: In accordance with the present invention, a method and a system for promoting scanning speed are provided. The method comprises steps of determining a transmission rate of a transit interface, adjusting system clock responsive to the transmission rate of the transit interface to change a data generated rate, and scanning an original to generate data at the rate controlled by the system clock. The key aspect of the present invention is by adjusting system clock to change the data generated rate corresponding to the transmission rate of the transit interface. Therefore, in response to the transmission rate of the transit interface, the system clock is adjusted to produce the data at a rate that can reduce the possibility of memory buffer full leading to the reduction in the time wasting on start-stop processes and therefore promote the scanning speed without requiring the increase in size of a memory buffer.

Abstract: Disclosed is a method, system and program product for performing multiple-pel print quality enhancement (PQE). As in known methods of PQE, a determination is made of an adjusted sub-pulse value of each pel of an image. In accordance with embodiments of the present invention, at least two adjacent pels are then grouped together and a determination is made of a combined pulse width value to charge the combined area of the at least two adjacent pels. Also determined is position information indicating the alignment of the pulse width within the combined area. The combined pulse width and position information is sent as input to a pulse width modulator operating at a speed equal to the video data rate of the printer divided by the number of pels for which the pulse width data is combined.

Abstract: A system and method for facilitating facsimile transmissions has one or more store and forward facilities. The store and forward facilities include a computer for controlling operations and mass data storage equipment. Subscriber mailboxes are provided as part of the mass storage, which can be accessed by a subscriber to have his messages delivered to any facsimile machine he designates. Secure facsimile transmission is achieved through use of subscriber PIN numbers. The system can also be used in cooperation with a paperless facsimile machine which directly displays the facsimile message on a screen and is capable of entering outgoing facsimile messages to the store and forward facility.

Abstract: This invention is to obtain a multi-beam scanning apparatus which always executes synchronization detection at the same timing to prevent any jitter, and an image forming apparatus using the apparatus. In a multi-beam scanning apparatus which guides a plurality of light beams emitted from a light source to an optical deflector, guides the plurality of light beams deflected by the optical deflector onto a target scanning surface through a scanning lens system, and guides some of the plurality of light beams deflected by the optical deflector to a synchronization detecting unit to execute synchronization using a sync signal obtained by the synchronization detecting unit, the synchronization detecting unit includes a BD slit which determines the synchronization detecting timing, and the BD slit has a smooth member.

Abstract: When correction data is set, a CPU 3 reads out the correction data from an EEPROM 8 through strobe signal lines STB1-N to STB4-N and supplies it as print data signals DATA3 to DATA0 to an LED driver IC 6. When the driving of an LED array 7 according to print data is instructed, the CPU 3 supplies a group selection signal to the LED array 7 through the strobe signal lines STB1-N to STB4-N. An electrophotographic printer which can realize a high speed of the operation and contribute to the improvement of the reliability is provided.

Abstract: An image forming apparatus which forms an image on a recording material, which has: a writing section to write according to the image data; an oscillator to generate a synchronized synchronizing clock signal; a spreading clock generator to spread the band of a synchronized reference clock and generate spreading clock signals; and a plurality of control circuits to control the image forming apparatus and each section of the image forming apparatus including a writing control circuit to control the writing section. More than one control circuits in the control circuits other than the writing control circuit are driven by the spreading clock signals, and the writing control circuit is driven by the synchronizing clock signal.

Abstract: A printer comprises, from upstream to downstream, a loader for articles to be printed, a printing device and transfer elements to direct sequentially the articles from the outlet of the loader to the printing device and from the printing device toward collection elements for the printed articles. The outlet drive element for the articles from the loader, has a cylinder in contact with the articles to be printed by an opening provided in a wall of the loader, and is moved by a motor common to the transfer elements. The contact between the cylinder and the articles is sequentially interrupted by an isolating device moved by a mechanical connection with the motor of the printing device.

Abstract: When serial data 110, which includes synchronous data 110A and effective data 110B, is received, a hold signal 130 is set at “1” and the PLL control is stopped while the effective data 110B is being received. As a result, low-cost, high-speed data transmission can be realized. Here, when one frame is composed of a start bit, the synchronous data 110A, and the effective data 110B, when the serial data 110 is composed of a plurality of frames, and when the bit length of data that has been transmitted either between the rising edges or between the falling edges of the synchronous data of the consecutive frames is an integral multiply of the dividing ratio of a divided clock signal, phase synchronization by the PLL with minimum transmission period of the synchronous data can be realized. As a result, the efficiency of image data transmission can be improved.

Abstract: A clock dividing section receives a system clock and generates and outputs clock signals of two or more types. Selectors select any of the clock signals of two or more types outputted by the clock dividing section and feed it to a printing control block or reading control block. A decision divider monitors operational states of each block and gives control so that a frequency to be supplied to a functional block in an idle state where any operation is not required is lower than that to be supplied to a functional block being in an active state. Power consumption of the whole custom IC can be more reduced compared with a configuration wherein a clock of fixed frequency is constantly supplied to each functional block and a noise can be controlled.

Abstract: The invention concerns an image-forming apparatus employing a clock-generating circuit, which generates dot clock pulses utilized for an image-writing section of the image-forming apparatus. The clock-generating circuit includes a digital-delay dot clock adjusting section to generate first dot clock pulses having a predetermined number of pulses within a predetermined time interval at a constant exposing range of the image-writing section, wherein each period of the first dot clock pulses is slightly increased or reduced by changing a selection for a plurality of delayed clock pulses, which are generated by delaying clock-pulses, outputted from a reference oscillator, in slightly different delay times; and a jitter suppressing section to suppress a jitter component included in the first dot clock pulses, wherein the jitter suppressing section divides the first dot clock pulses to generate second dot clock pulses, and then, multiplies the second dot clock pulses to generate the dot clock pulses.

Abstract: An image processing apparatus capable of preventing main scanning magnification discrepancies among a plurality of image data at low cost and with high precision. The apparatus includes a memory for storing control information specified by a CPU, an oscillator for generating a clock having a basic period equivalent to that of a unit pixel or less; variable frequency generators for adjusting a frequency of the clock to a predetermined level independently of each other on the basis of the control information; an image input connection for receiving predetermined data from an external device; image processors for converting parallel image data to serial image data on the basis of a frequency of clock outputted from associated one of the variable frequency generators; and an image output connection for transferring the serial image data to an external device.

Abstract: A method for identifying image data bits, especially where the image data is to be reliably co-identified with collateral document has been disclosed. Such “identification-bits” should be carried with the image data through various stages of processing, so the image's identity can be maintained at each processing station, and can be transferred to a downstream processing station. A salient object hereof is to identify image data; especially with “sync bits”.

Abstract: A stabilized frequency oscillating circuit outputs a pixel clock signal to an image scanner for controlling pixel rate at various writing positions along a scan line. The circuit includes a synchronization circuit having a first control signal component output to adjust a nominal output frequency of the oscillator; and a frequency profiling circuit having a second control signal component output which varies as a function of writing position along the scan line to determine a corrected output frequency of the oscillator which varies as a function of writing position along the scan line.

Abstract: A circuit for detecting a data segment sync signal of data segment consisting of a plurality of symbols in a high-definition television, includes a correlator for detecting a correlation value from a received data segment signal, a segment integrator for accumulating the detected correlation value by segments and attenuating the accumulated correlation value in response to an overflow prevention signal, a maximum-value detector for detecting a maximum accumulated correlation value in the segment from the segment integrator output, an overflow prevention circuit for generating the overflow prevention signal by comparing the detected maximum accumulated correlation value with a predetermined reference value, a sync position detector for detecting a symbol position having the detected maximum accumulated correlation value, and a synchronization signal generator for generating a synchronization signal at the symbol position corresponding to the detected maximum accumulated correlation value.

Abstract: A simplified transmission mechanism is provided for an image information apparatus. The transmission mechanism mainly includes a first pair of supports for guiding an illuminating unit, a second pair of supports beneath and parallel to the first pair of supports for guiding a photoelectric converting unit, four pulleys each located at the corners and on the same side of a housing, and a conveying device surrounding four pulleys in the shape of a closed loop for driving the illuminating unit to slide along the first pair of supports in a first direction and the photoelectric converting units to slide along the second pair of supports in a second direction at the same time and at the same speed.

Abstract: A method and apparatus which writes image information into a memory and reads the image information out of the memory using different synchronizing signals. A first synchronizing signal which is used to write scanned image data into the memory is generated to have a predetermined regularity, for example using a clock signal. The second synchronizing signal is based on an output of a photosensor which detects laser light reflecting off a polygonal mirror and is based on the rotating speed of the motor. The image information in the memory is read out in synchronism with the writing of the image information by the laser beam and polygonal mirror onto the photoconductive element using the second synchronizing signal. Therefore, it is not necessary for the polygonal mirror and the motor driving the polygonal mirror to be at a predetermined stable speed during the scanning operation.

Abstract: The invention relates to a method and to an arrangement for the synchronization of the image recording of monochrome recordings and color recordings with photosensitive line sensors. A line-scanning pattern is generated by a programmable counter arrangement, wherein the timer measures the phase position of the line-scanning pattern, generated by the counter arrangement, with the aid of the computer and the programmable counter arrangement at the point in time of the impinging of a pulse of the incremental transmitter, wherein the timer compares these with a coordinated calculated or tabulated reference value, and wherein the timer employs the thus obtained phase difference in order to influence a counter, preconnected to the line counter CT2, in its count volume (FIGS. 1 and 2).

Abstract: A pixel clock generator in which the frequency of a pixel clock signal is changed over for every scanning face prior to start of image record scanning, comprises a first scanning time detection circuit for detecting scanning period of time from the start of image scanning to the end of the image scanning; a reference clock signal generation circuit for generating a reference clock signal to make the frequency of the reference clock signal variable; a number-of-pixel-clocks setting circuit for setting the number of pixel clocks corresponding to forecast scanning time; a second scanning time detection circuit for counting the pixel clocks generated based the reference clock signal by the number set by the number-of-pixel-clocks setting circuit to detect the scanning time corresponding to the forecast scanning time; a comparison circuit for comparing the time detected by the first scanning time detection circuit with the time detected by the second scanning time detection circuit to obtain a comparison result; a

Abstract: In response to a vertical synchronizing signal generated from a vertical synchronizing signal generator, a microcomputer forms a predetermined image on a print sheet using a printer head on the basis of image data applied from an image memory. The microcomputer controls the rotation of a motor so that the move position of the print sheet is set to a predetermined position with a vertical synchronizing signal as the reference after an edge of the print sheet is detected by a sheet sensor.

Abstract: An image reading device has a photoelectric transducer for scanning an image to read it line by line and converting the resulting optical data to an electric signal. A driver drives the photoelectric transducer in response to a synchronizing signal. An internal period signal generating circuit generates an internal period signal having a predetermined period. A period setting circuit sets the predetermined period of the internal period signal. A synchronization switching circuit selects and outputs either of the internal period signal or an external period signal sent from the outside of the image reading device as the synchronizing signal. Even when an external period signal from an image recorder including a polygon motor or similar external apparatus is not available or when the external apparatus is not operated, the device can surely read a document.

Abstract: A highly accurate and stable, but continuous fixed-phase fixed-frequency, quartz crystal oscillator frequency source, typically of 80 Mhz frequency, is used as the primary frequency standard for (i) synchronized, and (ii) variable, pixel placement timing in a bee-scanning image generator. A fixed-frequency timing chain appropriately synchronized to the scanning energy beam is generated by selecting, in accordance with a sensed start-of-scan condition, from among a number, typically 23, of variably-phase-delayed, typically by less than 1 nanosecond and normally by 0.8 nanosecond, replications of a fixed-phase timing chain that is produced from the crystal oscillator. The synchronized fixed-frequency timing chain so derived is then converted to the required variable-frequency pixel placement timing chain by timing-data-driven recombination of variably-phase-delayed replications, typically 13 such replications at a delay of 1.

Abstract: A reliable, low cost system for generating precisely aligned pixel clock and index signals for a digital scanning or printing system is based on the use of a phase locked loop multiplier to generate a sampling clock precisely synchronized to the drum position encoder sensor output. The sample clock frequency is chosen to be a large, known multiple M of the pixel clock frequency. The pixel clock is chosen to be the sample clock divided by M, making it the proper frequency. Pixel clock phase is established by resetting, on the trailing edge of an index signal generated by a line start index sensor, a .div.M counter used in deriving the pixel clock from the sample clock. The rising edge of the pixel clock is then established to within .+-.(1/M) pixel clock periods of the trailing edge of the index signal.

Abstract: An image reading system including a charge storing type image sensor drives a manuscript or an image sensor in accordance with a driving pulse from a driving unit. A speed of the driving pulse from the driving unit is determined by a speed setting unit, depending on a change of a period of the apparatus scan. The driving pulse is stopped for a certain period of time, so that the difference in a speed of the driving pulse between the different apparatus scan periods is decreased.

Abstract: The present invention is a clock signal apparatus for a document scanner that only produces a clock signal when pixel data is output. The apparatus includes a timing and control unit 94 that not only controls the sensor analog output process along with the conversion of the analog signals to digital data, but also provides a video clock signal only when the sensor data is present at the output of the scanner. The unit 94 also provides an intersensor period during which no pixel data is output and no clock signal is produced. The unit 94 supplies a horizontal synchronization signal before the video clock is started and a horizontal synchronization signal immediately after the last data is transmitted. The receiving unit 72 latches the data synchronous with the video clock signal. The video clock signal includes multiple edges allowing the various edges to control various stages of further processing of the sensor data.

Abstract: A fundamental period calculation circuit calculates a fundamental period in accordance with a plurality of pulses including reproduction target pulses included in binary reproduced output signal pulses sequentially input as digital signal pulses to be reproduced. A clock generator generates a demodulation clock having the fundamental period calculated by the fundamental period calculation circuit. A phase error amount detecting circuit detects a phase error amount in accordance with a phase difference between the demodulation clock generated by the clock generator and a plurality of pulses including the reproduction target pulses. A synchronizing circuit controls the phase error amount of a generation timing of the demodulation clock by the clock generator to a predetermined value in accordance with the phase error amount detected by the phase error amount detecting circuit so that the demodulation clock generated by the clock generator is synchronized with each of the reproduction target pulses.

Abstract: A system and method has one or more store and forward facilities, (SAFF) each associated with a plurality of subscriber facsimile machines. The SAFF include a computer for controlling operations and mass data storage equipment. A subscriber to the system delivers an outgoing facsimile message to the SAFF with which it is associated, which records the fax message, together with data as to originating facsimile machine and destination facsimile machine. The SAFF then delivers the facsimile message to the intended receiver facsimile machine, either directly or through another SAFF. If unsuccessful on an initial attempt, the SAFF periodically retries to send the facsimile message. The system also provides spooling of all facsimile messages for an intended receiver machine, which are all spooled upon connection with the receiver machine. Subscriber mailboxes are provided as part of the mass storage, which can be accessed by a subscriber to have his messages delivered to any facsimile machine he designates.